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| BUS IC DC/DC CONVERTER MOTOR DRIVER IC Fan control y EC motor control Steppermotor driver RIPPLE COUNTER DRIVER IC I/O IC SENSOR IC SENSOR INTERFACE IC y EC motor control FEATURES y y y y y y y y y y y y y y y High voltage supply in the range VS = 6.0 V to 58 V Drive of up to 6 external n-channel Power FETs (3 high side- and 3 low side switches) Programmability of functions and parameters by SPI P interface Self adjusting driver timing and power FET protection High power efficiency Low RF emission due to the field programmable driver technology Three current measurement amplifiers and programmable over current protection On chip and external over temperature detection and protection Programmable analog measurement channels (temperature and motor currents) Position detection by BEMF Sleep / Wake up mode system 5V or 3.3V interface to control device Developmentkits available (programmable board and software with PC Interface) - 40C to + 125C operating temperature PLCC68 package The device works in typical motor regulator systems as physical interface between a C or a special controller hardware and the power FET-motor load configuration. The user has the complete control over the logical behaviour by software implementation in the C. In this way all control/regulation strategies of the motor can be realised by software development. DESCRIPTION The IC is a PWM EC brushless motor driver/controller to implement a motor regulator together with n-channel power FET B6configuration and a C The programmability of parameters (e.g. threshold values of over current, over temperature, motor failures, EMC conditions, etc.) can be used to drive motors in a widely different range. These programmability features and the driver channel control inputs and allow this chip to act in general motor regulator applications, too. The special programmable switching technology (pendingpatent) enables an excellent EMC behavior. APPLICATION y y y y EC or DC motor drive / regulation Fan cooler Air-conditioning Pumps system evaluation chip PINNING Pin 1 2 3 4 5-7 8 9 10 11-13 14-16 17 18 19 20 21 22 23 24 25-27 28-29 30-31 E910.46 PACKAGE Description A_CUR_SH_A A_CUR_SH_C A_CUR_SH_B ANAMUX ISENH_A ISENH_B ISENL_A ISENL_C ISENL_B ISENH_C DGND VDD42 VDD5 n.c. PGND Name ISENH_A ISENL_A DGND VDD A_CUR_SH_[C-A] TP ANAMUX IREF SH_[A-C] SIGN[A-C] VDD3 VSSA CS SCL MOSI MISO FAIL WAKE POS_[A-C] VDS_OVER_A[H,L] VDS_OVER_B[H,L] VDS_OVER_C[H,L] VDD3 AGND [A-C]_HI [A-C]_LO VS PGND GC_LO, GB_LO GA_LO Negative current measurement input, channel A Digital ground 9 TP 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 IREF 10 SH_A 11 SH_B 12 SH_C 13 SIGNA 14 SIGNB 15 SIGNC 16 VDD3 17 VSSA 18 CS 19 SCL 20 MOSI 21 MISO 22 FAIL 23 WAKE 24 POS_A 25 POS_B 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 n.c. 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 Positive current measurement input, channel A CP1 VPUMP VDD12P CP2 PHA GA_HI PHB GB_HI PHC GC_HI SP n.c. GA_LO n.c. GB_LO n.c. GC_LO 5V supply Current measurement output, channel [A-C], S&H Temperature sensor input Analog MUX output Reference current output Sample and hold control input, channel [A-C] Sign of current output, channel [A-C] VDS_OVER_BH VDS_OVER_CH POS_C VDS_OVER_AL AGND A_LO B_HI VDS_OVER_BL VDS_OVER_CL VDS_OVER_AH 3.3 V or 5 V supply of control interface Analog ground Enable signal of SPI Clock of SPI Data input of SPI Data output of SPI Failure signal, high active Wake up signal, low active Position signal of BEMF detection, channel [A-C] AVAILABILITY Samples Series available tbd. Pin 50 51 52,54, 56 53 55 57 58,63 59 60 62 64,66 67-68 Name SP GC_HI PHC, PHB, PHA GB_HI GA_HI CP2 VBAT, VS VPUMP CP1 PGND ISENH_C, ISENL_C ISENH_B, ISENL_B Description Star point connection Driver output, gate HS power FET, channel C Phase C-A Driver output, gate HS power FET, channel B Driver output, gate HS power FET, channel A VDS detection, high/low side switch, channel A VDS detection, high/low side switch, channel B VDS detection, high/low side switch, channel C BLOCK DIAGRAM VBAT RREF CVCP CCP VBAT VCP CP1 CP2 MISO MOSI SCL CS Fail Wake x-HI 3 x-LO 3 Charge Pump IREF optional VDD analog bus digital bus 32-33 VS VCP IREF VDD3 Rmeas (optional) 34 35 36-38 39-41 42 43 3.3V or 5V supply of control interface Analog ground Ctrl input of HS switch, channel [A-C], high active Ctrl input of LS switch, channel [A-C], high active VDD slewrate control prog. T1 T2 T3 3 Gx_HI Switch capacitor connection 2 of charge pump Pumped voltage, storage capacitor connection 12V supply, high voltage supply Switch capacitor connection 1 of charge pump Power ground Pos/Neg current measurement input, channel C Pos/Neg current measurement input, channel B SPI Rmeas Rmeas control S/H Rmeas + _ 3 ISENH_x 3 ISENL_x 12V supply Power ground Driver output, gate LS FET, channel c/b Driver output, gate LS power FET, channel A overcurrent detection PROG analog digital C VDS_OVER_xH 3 VDS_OVER_xL 3 PFET Monitor slewrate control prog. SP (opt.) VS 3 PH_x T4 T5 T6 44,46 48 3 Gx_L0 VDD R1 POS_x 3 + _ SH_x 3 A_CUR_SH_x 3 SIGN_x 3 analog MUX ANAMUX ext. & int. overtemperature detection IP Note ELMOS Semiconductor AG (below ELMOS) reserves the right to make changes to the product contained in this publication without notice. ELMOS assumes no responsibility for the use of any circuits described herein, conveys no licence under any patent or other right, and makes no representation that the circuits are free of patent infringement. While the information in this publication has been checked, no responsibility, however, is assumed for inaccuracies. ELMOS does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of a life-support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications. Copyright (c) 2005 ELMOS Reproduction, in part or whole, without the prior written consent of ELMOS, is prohibited. www.elmos.de | sales@elmos.de 40 VDD12 PGND B_LO VDD3 C_LO A_HI C_HI elmos product catalog june 2005 41 |
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