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[AKD4634-A]
AKD4634-A
AK4634 Evaluation board Rev.1
GENERAL DESCRIPTION AKD4634-A is an evaluation board for the AK4634, 16bit mono CODEC with MIC/SPK/VIDEO amplifier. The AKD4634-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D D/A). AKD4634-A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD4634-A --- Evaluation board for AK4634 (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this. This control software does not support Windows NT.)
FUNCTION * DIT/DIR with optical input/output * BNC connector for an external clock input * 10pin Header for serial control mode
AVDD DVDD SVDD 5V 3.3V Regulator GND
MIC-Jack MIC/ MICP LIN/ MICN AOUT SPK-Jack
Control Data 10pin Header
DSP
AK4634
10pin Header
AK4114
Opt In Opt Out
Clock Gen
Figure 1. AKD4634-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual.
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Evaluation Board Manual Operation sequence
1) Set up the power supply lines. 1-1) When AVDD, DVDD, SVDD and VCC are supplied from the regulator.
JP3 AVDD_SEL
JP4 SVDD_SEL
JP9 DVDD_SEL
JP10 LVC_SEL
JP11 VCC_SEL
REG
[REG] [AVDD] [DVDD] [SVDD] [VCC] [AVSS] [SVSS] [DGND]
AVDD SVDD
(red ) (orange) (orange) (blue) (orenge) (black) (black) (black) = 5V = open = open = open = open = 0V = 0V = 0V
REG DVDD AVDD VCC
DVDD VCC
LVC
: 3.3V is supplied to AVDD of AK4634 from regulator. : 3.3V is supplied to DVDD of AK4634 from regulator. : 3.3V is supplied to SVDD of AK4634 from regulator. : 3.3V is supplied to logic block from regulator. : for analog ground : for analog ground : for logic ground
1-2) When AVDD, DVDD, SVDD and VCC are supplied from the power supply connectors.
JP3 AVDD_SEL
JP4 SVDD_SEL
JP9 DVDD_SEL
JP10 LVC_SEL
JP11 VCC_SEL
REG
[REG] [AVDD] [DVDD] [SVDD] [VCC] [AVSS] [SVSS] [DGND]
AVDD SVDD
REG DVDD AVDD VCC
DVDD VCC
LVC
(red) (orange) (orange) (blue) (orenge) (black) (black) (black)
= open. = 2.2 3.6V = 2.7 3.6V = 2.2 4.0V = 2.7 3.6V = 0V = 0V = 0V
: for AVDD of AK4634 (typ. 3.3V) : for DVDD of AK4634 (typ. 3.3V) : for SVDD of AK4634 (typ. 3.3V) : for logic (typ. 3.3V) : for analog ground : for analog ground : for logic ground
* Each supply line should be distributed from the power supply unit. DVDD and VCC must be same voltage level. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4634 and AK4114 should be reset once bringing SW1, 2 "L" upon power-up.
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Evaluation mode
In case of AK4634 evaluation using AK4114, it is necessary to correspond to audio interface format for AK4634 and AK4114. About AK4634's audio interface format, refer to datasheet of AK4634. About AK4114's audio interface format, refer to Table 2 in this manual. Applicable Evaluation Mode (1) Evaluation of loop-back mode (A/D D/A) : PLL, Master Mode (Default) (2) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) (3) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK pin) (4) Evaluation of loop-back mode (A/D D/A) : EXT, Master Mode (5) Evaluation of using DIR/DIT of AK4114 (opt-connector) : EXT, Slave Mode
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(1) Evaluation of loop-back mode (A/D D/A) : PLL, Master Mode (Default) a) Set up jumper pins of MCKI clock Set "No.8 of SW3" to "H". X'tal of 12MHz, 13.5MHz, 24MHz or 27MHz can be set in X1. X'tal of 12MHz (Default) is set on the AKD4634-A. When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock generator.
JP17 XTE JP21 MCLK_SEL JP18 MKFS
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock Output frequency (16fs/32fs/64fs) of BICK should be set by "BCKO1-0 bit" in the AK4634. There is no necessity for set up JP19.
JP19 BICK_SEL
JP20 BICK
JP27 BICK
JP29 BICK_INV
64fs 32fs 16fs EXT
INV
THR
DIR ADC
INV
THR
c) Set up jumper pins of FCK clock
JP22 FCK_SEL JP28 FCK
DIR 2fs 1fs EXT
ADC
d) Set up jumper pins of DATA When the AK4634 is evaluated by loop-back mode (A/D D/A), the jumper pins should be set to the following.
JP30 SDTI JP26 4632_SDTI
DIR
ADC
DAC/LOOP ADC
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[AKD4634-A] (2) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) a) Set up jumper pins of MCKI clock X'tal of 12MHz, 13.5MHz, 24MHz or 27MHz can be set in X1. X'tal of 12 MHz (Default) is set on the AKD4634-A. In this case, the AK4634 corresponds to PLL reference clock of 12MHz. In this evaluation mode, the output clock from MCKO-pin of the AK4634 is supplied to a divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Then "MCKO bit" in the AK4634 is set to "1". When an external clock through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock generator.
JP17 XTE JP21 MCLK_SEL JP18 MKFS
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock Input frequency of BICK should be set 64fs/32fs/16fs by JP19.
JP19 BICK_SEL
JP20 BICK
JP27 BICK
JP29 BICK_INV
64fs 32fs 16fs EXT
INV
THR
DIR ADC
INV
THR
c) Set up jumper pins of FCK clock
JP22 FCK_SEL JP28 FCK
DIR 2fs 1fs EXT
ADC
d) Set up jumper pins of DATA When the AK4634 is evaluated by loop-back mode (A/D D/A), the jumper pins should be set to the following.
JP30 SDTI
JP26 4632_SDTI
DIR
ADC
DAC/LOOP ADC
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(3) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK pin) a) Set up jumper pins of MCKI clock An external clock through a RCA connector (J8: EXT/BICK), BICK and FCK clocks are generated by the divider. JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock generator.
JP17 XTE JP21 MCLK_SEL JP18 MKFS
XTL DIR EXT 256fs 512fs 1024fs MCKO
*When BICK and FCK clocks through a RCA connector (J8, J9) is supplied, select XTL on JP21. *When X'tal is used, X'tal of 256fs, 512fs or 1024fs can be set in X1. Set OPEN on JP17, and select XTL on JP21. b) Set up jumper pins of BICK clock Input frequency of BICK should be set 64fs/32fs/16fs by JP19.
JP19 BICK_SEL
JP20 BICK
JP27 BICK
JP29 BICK_INV
64fs 32fs 16fs EXT
INV
THR
DIR ADC
INV
THR
*When BICK and FCK clocks through a RCA connector (J8, J9) is supplied, select EXT on JP19. JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock generator. c) Set up jumper pins of FCK clock
JP22 FCK_SEL
JP28 FCK
DIR 2fs 1fs EXT
ADC
*When BICK and FCK clocks through a RCA connector (J8, J9) is supplied, select EXT on JP22. JP24 (EXT1) and R27 should be properly selected in order to much the output impedance of the clock generator. d) Set up jumper pins of DATA When the AK4634 is evaluated by loop-back mode (A/D D/A), the jumper pins should be set to the following.
JP30 SDTI JP26 4632_SDTI
DIR
ADC
DAC/LOOP ADC
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[AKD4634-A] (4) Evaluation of loop-back mode (A/D D/A) : EXT, Master Mode
a) Set up jumper pins of MCKI clock Set "No.8 of SW3" to "H". An external clock (256fs, 512fs or 1024fs) through a RCA connector (J8: EXT/BICK) is supplied. JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock generator.
JP17 XTE JP21 MCLK_SEL JP18 MKFS
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock Output frequency (32fs or 64fs) of BICK should be set by "BCKO1-0 bit" in the AK4634. There is no necessity for set up JP19.
JP19 BICK_SEL
JP20 BICK
JP27 BICK
JP29 BICK_INV
64fs 32fs 16fs EXT
INV
THR
DIR ADC
INV
THR
c) Set up jumper pins of FCK clock
JP22 FCK_SEL JP28 FCK
DIR 2fs 1fs EXT
ADC
d) Set up jumper pins of DATA When the AK4634 is evaluated by loop-back mode (A/D D/A), the jumper pins should be set to the following.
JP30 SDTI JP26 4632_SDTI
DIR
ADC
DAC/LOOP ADC
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(5) Evaluation of using DIR/DIT of AK4114 (opt-connector) : EXT, Slave Mode
a) Set up jumper pins of MCKI clock
JP17 XTE JP21 MCLK_SEL JP18 MKFS
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock
JP19 BICK_SEL
JP20 BICK
JP27 BICK
JP29 BICK_INV
64fs 32fs 16fs EXT
INV
THR
DIR ADC
INV
THR
c) Set up jumper pins of FCK clock
JP22 FCK_SEL
JP28 FCK
DIR 2fs 1fs EXT
ADC
d) Set up jumper pins of DATA When D/A converter of the AK4634 is evaluated by using DIR of AK4114, the jumper pins should be set to the following.
JP30 SDTI JP26 4632_SDTI
DIR
ADC
DAC/LOOP ADC
When A/D converter of the AK4634 is evaluated by using DIT of AK4114, the jumper pins should be set to the following.
JP30 SDTI JP26 4632_SDTI
DIR
ADC
DAC/LOOP ADC
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DIP Switch set up
[SW3] (MODE) : Mode Setting of AK4634 and AK4114 ON is "H", OFF is "L". No. 1 2 3 4 5 6 7 8 Name OFF ("L") ON ("H") Default DIF0 AK4114 Audio Format Setting Off DIF1 See Table 2 Off DIF2 On CM0 Clock Operation Mode select Off CM1 See Table 3 On OCKS0 Master Clock Frequency Select Off OCKS1 See Table 4 Off M/S Slave mode Master mode On Note. When the AK4634 is evaluated Master mode, "M/S" is set to "H". Table 1. Mode Setting for AK4634 and AK4114
Setting for AK4114 Audio Interface Format
Register setting for AK4634
DIF1 bit DIF0 bit DIF0 DIF1 DIF2 DAUX SDTO 0 1 L L L 24bit, Left justified 16bit, Right justified 1 0 L L H 24bit, Left justified 24bit, Left justified Default 1 1 H L H 24bit, I2S 24bit, I2S Note. When the AK4634 is evaluated by using DIR/DIT of AK4114, "No.8 of SW3" is set to "L". Table 2. Setting for AK4114 Audio Interface Format Mode 0 1 2 3 CM0 L H L H CM1 L L UNLOCK PLL X'tal Clock source ON OFF PLL OFF ON X'tal 0 ON ON PLL H 1 ON ON X'tal H ON ON X'tal ON: Oscillation (Power-up), OFF: STOP (Power-down) Table 3. Clock Operation Mode select No. 0 2 OCKS0 L L OCKS1 L H MCKO1 256fs 512fs MCKO2 256fs 256fs X'tal 256fs 512fs SDTO RX DAUX RX DAUX DAUX
Default
Default
Table 4. Master Clock Frequency Select
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Other jumper pins set up
1. JP1 (GND) OPEN SHORT : Analog ground and Digital ground : Separated. : Common. (The connector "DGND" can be open.)
2. JP3 (AVDD_SEL) : AVDD of the AK4634 REG : AVDD is supplied from the regulator ("AVDD" jack should be open). < Default > AVDD : AVDD is supplied from "AVDD " jack. 3. JP4 (SVDD_SEL) : SVDD of the AK4634 REG : SVDD is supplied from the regulator ("SVDD" jack should be open). < Default > SVDD : SVDD is supplied from "SVDD " jack. 4. JP9 (DVDD_SEL) : DVDD of the AK4634 AVDD : DVDD is supplied from "AVDD". < Default > DVDD : DVDD is supplied from "DVDD " jack. 5. JP10 (LVC_SEL) : Logic block of LVC is selected supply line. DVDD : Logic block of LVC is supplied from "DVDD". < Default > VCC : Logic block of LVC is supplied from "VCC " jack. 6. JP11 (VCC_SEL) : Logic block is selected supply line. LVC : Logic is supplied from supply line of LVC. < Default > VCC : Logic block of LVC is supplied from "VCC " jack. 7. JP25 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114. MCKO1 : The check from MCKO1 of AK4114 is provided to MCKI of the AK4634. < Default > MCKO2 : The check from MCKO2 of AK4114 is provided to MCKI of the AK4634. 8. JP102 (I2C) OPEN SHORT 9. JP103 (MCKO) OPEN SHORT : Control Interface is selected mode. : 3-wire Serial Control Mode. < Default > : I2C-bus Control Mode. (Not used in this board.) : Master Clock Frequency is selected from AK4634. : Not supply. : Supplied from AK4634. < Default >
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The function of the toggle SW
[SW1] (DIR) : Power control of AK4114. Keep "H" during normal operation. Keep "L" when AK4114 is not used. : Power control of AK4634. Keep "H" during normal operation.
[SW2] (PDN)
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
Serial Control
The AK4634 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (CTRL) with PC by 10 wire flat cable packed with the AKD4634-A
Connect PC
CSN CCLK CDTI
AKD4635
10 wire flat cable
10pin Connector
10pin Header
Figure 2. Connect of 10 wire flat cable
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Analog Input / Output Circuits
(1) Input Circuits a) MIC/MICP Input Circuit
J1 MIC-JACK
6 4 3
JP105 MPI MPI JP12 MIC_SEL R112 2.2k MIC/MICP C108 1u
AVSS J3 MIC/MICP
JACK RCA
2 3 1
MR-552LS AVSS
Figure 3. MIC/MICP Input Circuit (a-1) Analog signal is input to MIC pin via J1 connector.
JP12 MIC_SEL JP105 MPI
RCA JACK
(a-2) Analog signal is input to MIC/MICP pin via J3 connector.
JP12 MIC_SEL JP105 MPI
RCA JACK
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b) LIN/MICN Input Circuit
J4 LIN/MICN
2 3 1
C112 1u LIN/MICN R18 47k JP113 MICN R113 2.2k
MR-552LS
AVSS
Figure 4. LIN/MICN Input Circuit (b-1) LIN is input from J4.
JP104 MICN
(b-2) MICN is input from J4.
JP104 MICN
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(2) Output Circuits a) AOUT Output Circuit
C28 AOUT
1
+
2
R20 220
1u
R21 20k AVSS
2 3 1
J5 AOUT
MR-552LS
AVSS
Figure 5. AOUT Output Circuit
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C) SPK Output Circuit Note. When mini-jack is inserted or pulled out J2 (SPK-JACK) connector, JP13 (SPP_SEL) and JP14 (SPN_SEL) should be open, or "PMSPK bit" in the AK4634 should be set to "0".
JP31 Dynamic J2 SPK-JACK
R15 10 SPP JP13
K
SVSS
3 4 6
D1
A
Dynamic(EXT) Piezo(EXT) Dynamic CN5 Dynamic(EXT) Piezo(EXT) Dynamic
2
SPK1 020S16 R
SVSS
DIODE ZENER D2
A K
SPP_SEL JP14
SVSS
DIODE ZENER
SPN_SEL
1
R17 10 SPN
L
Figure 6. SPK Output Circuit (C-1) "Dynamic Speaker" of external is evaluated by using J2 (SPK-JACK) connector.
JP13 SPP_SEL JP14 SPN_SEL JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
(C-2) "Piezo (Ceramic) Speaker" of external is evaluated by using J2 (SPK-JACK) connector.
JP13 SPP_SEL JP14 SPN_SEL JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
(C-3) Analog signal of SPP/SPN pins are output "Dynamic Speaker" on the evaluation (SPK1).
JP13 SPP_SEL JP14 SPN_SEL JP31 Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
Dynamic Dynamic(EXT) Piezo(EXT)
AKEMD assumes no responsibility for the trouble when using the above circuit examples. - 15 2007/07
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Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4634-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4634-A by 10-line type flat cable (packed with AKD4634-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AKD4634 Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "akd4634.exe" to set up the control program. 5. Then please evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button. 3. Click "Write default" button
Explanation of each buttons
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. [Port Reset] : [Write default] : [All Write] : [Function1] : [Function2] : [Function3] : [Function4] : [Function5] : [SAVE] : [OPEN] : [Write] : [Filter] : Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of the AK4634. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Set Programmable Filter (HPF, LPF, EQ1~5) of AK4634 easily.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to the AK4634, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal.
If you want to write the input data to the AK4634, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate IVOL, OVOL.
There are dialogs corresponding to register of 09h and 0Ah. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to the AK4634 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to the AK4634, click [OK] button. If not, click [Cancel] button.
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4. [SAVE] and [OPEN]
4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is "akr". (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is "akr". 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK4634. The file type is the same as [SAVE]. (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button.
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5. [Function3 Dialog]
The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [OPEN] button on the Function3 window. The extension of file name is "aks".
Figure 7. [F3] Window
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6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 8 opens.
Figure 8. [F4] window
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6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 9.
Figure 9. [F4] window (2) (2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is "*.ak4". [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change.
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7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 10 opens.
Figure 10. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 11. (2) Click [WRITE] button, then the register setting is executed.
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Figure 11. [F5] window (2)
7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is "*.ak5". [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change.
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8. [Filter Dialog]
A calculation of a coefficient of Digital Programmable Filter such as HPF,EQ filter ,a write to a register and check frequency response such as HPF,EQ filter. Window to show to Figure 12 opens when push a [Filter] button .
Figure12. [Filter] Window
8-1. Setting of a parameter (1) Please set a parameter of each Filter. Item Contents Setting range Sampling Rate Sampling frequency (fs) 7350Hz fs 48000Hz HPF Cut Off Frequency High pass filter cut off frequency fc/fs 0.0001 (fc min = 1.6Hz at 16kHz) LPF Cut Off Frequency Low pass filter cut off frequency fc/fs 0.05 (fc min = 2205Hz at 44.1kHz) 5 Band Equalizer EQ1-5 Center Frequency EQ1-5 Center Frequency fon / fs < 0.497 EQ1-5 Band Width EQ1-5 Band Width (Note 1) EQ1-5 Gain EQ1-5 Gain (Note 2) -1 Kn < 3 Note 1. A gain difference is a bandwidth of 3dB from center frequency. Note 2. When a gain is smaller than 0 , EQ becomes a notch filter.
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(2) "LPF", "HPF", "HPFAD", "EQ1", "EQ2", "EQ3", "EQ4", "EQ5" Please set ON/OFF of Filter with a check button. When checked it, Filter becomes ON. When checked "Notch Filter Auto Correction", perform automatic revision of center frequency of a notch filter. ("Cf. 8-4. automatic revision of center frequency of a notch filter")
Figure13. Filter ON/OFF setting button 8-2. A calculation of a register A register set value is displayed when push a [Register Setting] button. When a value out of a setting range is set, error message is displayed, and, a calculation of register setting is not carried out.
Figure14. A register setting calculation result When it is as follows that a register set value is updated. (1) When [Register Setting] button was pushed. (2) When [Frequency Response] button was pushed. (3) When [UpDate] button was pushed on a frequency characteristic indication window. (4) When set ON/OFF of a check button "Notch Filter Auto Correction"
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[AKD4634-A]
8-3.Indication of a frequency characteristic A frequency characteristic is displayed when push a [Frequency Response] button. In addition, a register set point is updated then, too. Change "Frequency Range", and indication of a frequency characteristic is updated when push a [UpDate] button.
Figure15. A frequency characteristic indication result When it is as follows that a register set point is updated. (1) When [Register Setting] button was pushed. (2) When [Frequency Response] button was pushed. (3) When [UpDate] button was pushed on a frequency characteristic indication window. (4) When set ON/OFF of a check button "Notch Filter Auto Correction"
8-4. Automatic revision of center frequency of a notch filter When set a gain of 5 band Equalizer to -1, Equalizer becomes a notch filter. When center frequency of plural notch filters is adjacent, produce a gap to central frequency (Figure 16). When check "a Notch Filter Auto Correction" button, perform automatic revision of central frequency of a notch filter, display register setting after automatic revision and a frequency characteristic (Figure 17). This automatic revision is availability for Equalizer Band which set a gain to "-1". (Note) When distance among center frequency is smaller than band width, there is a possibility that automatic revision is not performed definitely. Please confirm a revision result by indication of a frequency characteristic.
- 26 -
2007/07
[AKD4634-A]
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common) Figure16. When there is no revision of center frequency
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common) Figure17. When there is revision of center frequency
- 27 -
2007/07
[AKD4634-A]
Revision History
Date 07/04/05 07/07/02 Manual Revision KM088300 KM088301 Board Revision 0 1 Reason First Edition Device Rev. changed Contents
AK4634: Rev.A Rev.B
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
- 28 -
2007/07
A
B
C
D
E
8
7
6
5
4
3
2
TP102 (open) 1
E
TP100 AVDD 1 TP101 AVSS JP100 (open)
E
R100 51 TP104 PDN 1 TP103 (open)
1
1
JP101 (open) DC SAG
SAG 2
DC
C101 10u
2 1
1
1
C1
C2
A1
D1
U100
AVDD
TST1
TST3
D
VSS1
TST2
E1
R102 51
9
TP105 CSN
B2 1 CSN/SDA VCOC E2
10
A2
PDN
VCOM
D2
+
TP106 R103 51 CCLK
1
TP124 VCOM
1
R104 51
11
TP107 CDTI
C3 CDTIO MPI D3 1
C109 0.1u
JP105 MPI R112 2.2k TP122 MIC
1 31
TP108 R105 51 SDTI
12 1
B3
CCLK/SCL
MIC/MICP
E3
1
R106 51
13
C
TP109 SDTO
A3 FCK 1
TP110 R107 51 FCK
14 1
AK4634
C4
MCKI
R108 51
15
TP111 BICK
A4 BICK SVDD D5
TP112 DVDD
16 1
1
C106 0.1u +
B4 SDTI
1
2
CN104 8P JP102
A5
SDTO
SPP
E5
1
A6
I2C MCKO DVDD VSS2 VSS3 SPN
I2C R101 10k
B5
B6
C6
C5
C104 0.1u
R110 open
1 2
L100 open
2
D6
B
1
TP115 MCKO
1
JP103
C105 10u
+
MCKO
TP114 MCKI 1 TP113 AVSS 1 R109 51
A
17
18
19
20
21
22
23
CN103 8P
24
A
B
+
+
C103 (open)
2
C102 (open)
C100 0.1u
1
CN102 8P
TP116 SPN
C
+
D
TP125 VCOC R111 10k
11 2
C111 4700p TP123 AVSS
32
C110 2.2u
30
C108 1u
LIN/MICN E4
29
C
AOUT
D4
28
C107 10u
TP121 AOUT
27
26
25
NC
E6
CN101 8P
C112 1u
B
R113 2.2k
JP104 MICN
TP117 SPP 1
1
TP119 SVSS 1
1 1
TP118 SVDD
TP120 LIN
Title Size Document Number
A
AKD4634-A
Rev
A3
Date:
D
AK4634_SUB_29CSP
Monday, February 26, 2007
Sheet
E
0
of
1
1
A
B
C
D
E
REG_IN T1 TA48033F
GND IN OUT 1
JP1 GND REG INT C2 0.1u AVSS SVSS MOUT AOUT BEEP C3 + 47u
E
C1 0.1u
E
2
AVSS
AVSS CN1 32pin_4
32 31 30 29 28 27 26 25
REG T45_R
1
AVDD T45_O
1
DVDD T45_O
1
VVDD (NMT)
1
AVSS T45_BK
1
VCC T45_O
1
SVDD T45_BU
1
SVSS T45_BK
1
DGND T45_BK
1
D
AVSS
32
R1 C6 C7 (NMT) (NMT) (NMT)
1 31 30 29 27 28 26 25
1
VCOM
MICOUT
BEEP
MIC
AIN
REG CN2 AVDD_IN L1
1 1 2
C8 (NMT) AVSS
1 2 1
1
MOUT
AOUT
MPI
R2 (NMT)
U1
VCOC
2
AVSS
SVDD
1
3 2
22
47u
C
AVSS
4
AVSS
2
1
AVSS AVDD JP8 AVDD (NMT) L3
1 1 2
R5 (NMT) VIN VOUT
5 6 7 5
R4 (NMT)
1
JP5 (NMT)
VIN
SPN
20 19 18
SAGC00 + SAGC11 SAGC00
7 2 1 6
C17 (NMT) +
VOUT
MCKO
19
4632_MCKO SVSS 4632_MCKI
VVDD
PDN VVDD
8
DVDD
SDTO
CCLK
C19 (NMT)
+
2
(NMT)
32pin_1
1 SAGC11 2 JP7 C18 (NMT) (NMT) 8
VSAG
MCKI
18
JP6 (NMT)
17
AVSS
PDN BICK CDTI SDTI CSN FCK DVSS 17
R6 (NMT)
32pin_3
AVSS
B
C20 (NMT)
B
9
10
11
12
13
14
15
AVDD JP9 AVDD DVDD_SEL L4
1 1 2
16
+
R7 R8 R9 R10 R11 R12 R13 (NMT) (NMT) (NMT) (NMT) (NMT) (NMT) (NMT) R1410 DVDD DVDD R40 (short) DVDD JP10 LVC_SEL
10 11 12 13 14 15
1
2
AVSS
DVDD_IN
C21 (NMT)
C22 47u
+
2
(short)
LVC AVSS VCC_IN L5
A
VCC LVC
2
32pin_2 JP11 VCC_SEL CSN D3.3V CCLK CDTI
4632_SDTO
4632_SDTI
4632_BICK
4632_FCK
1 1
DVDD
16
CN4
9
2
C23 47u
+
2
(short)
VCC
A
B
+
C13
+
(short)
AVDD
AVDD
3
C14 (NMT)
C15 (NMT)
4 VVDD
R3 (NMT) (NMT)
SPP 21
20
C
+
C9 (NMT)
C11 (NMT)
2
REG
JP3 AVDD_SEL
2
+
C10 (NMT)
AVDD
+
+ +
C4 (NMT)
2
C5 (NMT)
2
JP2 (NMT)
REG_IN AVDD_IN DVDD_IN
VVDD
AVSS
VCC_IN
SVDD
SVSS
D
MIN
24
CN3
SVSS 23 24
REG MIN REG JP4 SVDD_SEL
1
C12 (NMT)
SVSS
23
SVSS
22
SVDD L2
2
SVDD
21
SPP SPN
(short)
C16 + 47u
C
A
Title Size Document Number
AKD4634-A
AK4634
Sheet
E
Rev
A3
Date:
D
0 1
of
Monday, February 26, 2007
5
A
B
C
D
E
J1 MIC-JACK
6 4 3
JP31 Dynamic J2 SPK-JACK
3 4 6
E
AVSS J3 MIC
2 3 1
JACK RCA
JP12 MIC_SEL INT SPP
R15 10
SVSS
E
D1
A K
JP13
MR-552LS AVSS
2
Dynamic(EXT) Piezo(EXT) Dynamic CN5 Dynamic(EXT) Piezo(EXT) Dynamic
2
SPK1 020S16 R
C24 (NMT)
1
SVSS MOUT C25 (NMT) SVSS
ZD5.1 D2
A K
SPP_SEL JP14
J4 BEEP/MIN/MOUT
2 3 1
JP15 (MIN short)
OUT IN
R16 (NMT) AVSS
+
ZD5.1
SPN_SEL
1
MR-552LS
D
AVSS C26 (short)
2 1
JP16 MOUT MIN BEEP (MIN short) (NMT) MIN R19 BEEP
R17 10 SPN
L
D
+ + R18 47k AVSS
C28 AOUT
1
+
R20 220
2 2 3 1
J5 AOUT
1u
R21 20k AVSS
MR-552LS
C
C
AVSS
J6 (NMT)
2 3 1
C29 VIN (NMT) R23 (NMT) R41 (NMT) VOUT
R22 (NMT)
2 3 1
J7 (NMT)
AVSS AVSS
B
AVSS AVSS
B
A
A
Title Size Document Number
AKD4634-A
Input/Output
Sheet
E
Rev
A3
Date:
A B C D
0 2
of
Monday, February 26, 2007
5
A
B
C
D
E
for 74HCU04,74AC74,74VHC4040,74HC14,74HC14,74HC541,74HCT04
D3.3V X1 12MHz
1 2
E
C30 0.1u
C31 0.1u
C32 0.1u
C33 0.1u
C34 0.1u
C35 0.1u
C36 0.1u
1
+ C37 47u
E
R24 1M
U2C
5 6 3
U2B
4
74HCU04 JP17 XTE C38 5p C39 5p
74HCU04
D
2
D
EXT_MCLK
D3.3V
D3.3V JP18 MKFS
10 11
10
4
U4A 74AC74
Q 5 12 11 D CLK
U4B 74AC74
Q 9
PR
DIR_MCLK
C
XTL DIR EXT
JP21
R25 short
D CLK
PR
2 3
256fs 512fs 1024fs MCKO
U3
CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1
64fs 32fs 16fs EXT
JP19 BICK_SEL
THR
1 2
JP20 BICK EXT_BICK
CL
Q
6
CL
Q
8
MCLK_SEL
13
U5A 74HC14 JP22
INV
C
1
74VHC4040 MCKO
2fs 1fs EXT
EXT_FCK FCK_SEL
J8 EXT/BICK
B
2 3 1
MR-552LS AVSS
R26 51 JP23 EXT1
B
J9 FCK
2 3 1
MR-552LS AVSS
A
R27 51 JP24 EXT2
Title Size Document Number
A
AKD4634-A
CLOCK
Sheet
E
Rev
A3
Date:
A B C D
0 3
of
Monday, February 26, 2007
5
A
B
C
D
E
C40 C41 0.1u 0.1u D3.3V
1
D3.3V L6 (short)
E
R28 10k U5B
4 3 6
K
PORT1
VCC GND OUT 3 2 1
C42 0.1u R29 470 C43 10u
2 1
U5C
5
3
C45 0.1u
C44 0.1u
2
1
TORX141
D3.3V
74HC14
74HC14
L
A
D3 HSU119
E
2
H SW1 DIR
+
C46 0.47u
R30 18k
45
41
39
47
43
48
46
44
D
DIF0 DIF1 DIF2 CM0 CM1 OCKS0 OCKS1 M/S
SW3
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
U6
42
VCOM
AVSS
40
R
TEST1
AVDD
NC
NC
38
INT1
RX3
RX2
RX1
RX0
37
D
U7D
INT0 36 9 8
R31 1k
K
LED1 ERF
A
1
IPS0
D3.3V
74HC04
2 NC OCKS0 35
OCKS0
RP1
9 8 7 6 5 4 3 2 1 3 DIF0 OCKS1 34
OCKS1
CM0 CM1 OCKS0 OCKS1 M/S
4
TEST2
CM1
33
CM1
5
DIF1
CM0
32
CM0
C
47k
C
6
NC
1
7
DIF2
AK4114
PDN
31
C47 5p
XTI 30
X2 11.2896MHz
IPS1 XTO 2 8 29
C48 5p
9
P/SN
DAUX
28
DAUX
10
XTL0
MCKO2
27
11
B
XTL1
BICK
26
DIR_BICK
B
12
VIN MCKO1 DVDD COUT UOUT BOUT VOUT DVSS DVSS TVDD LRCK TX0 TX1
SDTO
25
DIR_SDTI
13
14
15
16
17
18
19
20
21
22
23
C49 0.1u +
C50 0.1u +
24
DIR_FCK
JP25 MCKO_SEL MCKO2 MCKO1 DIR_MCLK
1
2
1
2
C51 10u D3.3V PORT2
A
C52 10u D3.3V
A
IN VCC GND
3 2 1
D3.3V C53 0.1u
Title Size Document Number
TOTX141
AKD4634-A
DIR/DIT
Sheet
E
Rev
A3
Date:
A B C D
0 4
of
Monday, February 26, 2007
5
A
B
C
D
E
U9
E
U8
LVC
20
1 11 Y8 A8 9
DIR
VCC
E
M/S
19 G GND 10
C54 0.1u
MCKO
12
Y7
A7
8
4632_MCKO RP2 RP3
7 6 5 4 3 2 1 2 A1 B1 18 7 6 5 4 3 2 1
4632_MCKI
13
Y6
A6
7
EXT_MCLK
3
DAUX
14
Y5
A5
6
4632_SDTO JP26 4632_SDTI DAC/LOOP 47k
A2
B2
17
4
4632_SDTI
15
Y4
A4
5 5
A3
B3
16
47k
16
D
Y3
A3
4
ADC
6
A4
B4
15
D
17
Y2
A2
3 7
A5
B5
14
18
Y1
A1
2 8
A6
B6
13
JP27 BICK
12
ADC DIR
EXT_BICK DIR_BICK
10
GND
G2
19
4632_BICK
A7
B7
C55 0.1u
20 VCC G1 1
4632_FCK
9
A8
B8
11
JP28 FCK
ADC DIR
EXT_FCK DIR_FCK
74HC541
74LVC245
C
C
LVC + C56 47u
13
U10F
12
JP29 INV THR BICK_INV
2
1
74HC14
D3.3V
R32 R34 R36
10k 10k 10k
R33 R35 R37
470 470 470
U11
2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11
CSN CCLK CDTI PDN
4632_MCKI MCLK BICK FCK SDTI VCC
1 2 3 4 5
PORT3
10 9 8 7 6
PORT4
1 2 3 4 5 10 9 8 7 6
CSN CCLK CDTI
ROM
B
B
CTRL
74HC541
R38 D3.3V 10k ADC
D3.3V
K
DAUX
A
D4 HSU119
R39 10k U5D
9 8 11
JP30 SDTI DIR
10
DIR_SDTI
U5E 74HC14 U2A
1 2 13
L
3 1
H SW2 PDN
2
74HC14
U2F
12 1
U7A
2 3
U10B
4
74HCU04 C57 0.1u U2D
9 8 3
74HCU04 U7B
4 11
74HC04 U7E
10 5
74HC14 U10C
6 11
U10E
10
A
A
74HCU04 U2E
11 10 5
74HC04 U7C
6 13
74HC04 U7F
12 9
74HC14 U10D
8 1
74HC14 U10A
2 Title Size
74HCU04
74HC04
74HC04
74HC14
74HC14
AKD4634-A
Document Number
A3
Date:
A B C D
LOGIC
Sheet
E
Rev
0 5
of
Monday, February 26, 2007
5

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