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XPS 16550 UART (v1.00a)
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Product Specification
Introduction
This document provides the specification for the XPS 16550 UART (Universal Asynchronous Receiver/Transmitter) Intellectual Property (IP). The XPS 16550 UART described in this document has been incorporating features described in National Semiconductor PC16550D UART with FIFOs data sheet. The National Semiconductor PC16550D data sheet is referenced throughout this document and should be used as the authoritative specification. Differences between the National Semiconductor PC16550D and the XPS 16550 UART are highlighted in Specification Exceptions section.
Supported Device Family Version of Core
LogiCORETM Facts
Core Specifics SpartanTM-3E, Spartan-3, Spartan-3A, Spartan-3AN, VirtexTM-4 and Virtex-5 xps_uart16550 Resources Used Min Slices LUTs FFs Block RAMs Special Features N/A N/A Provided with Core Documentation Design File Formats Constraints File Verification Instantiation Template Reference Designs & Application notes Additional Items Product Specification VHDL N/A N/A N/A N/A N/A Refer to the Table 17, Table 18 and Table 19 Max v1.00a
Features
* PLB v4.6 based PLB interface * Hardware and software register compatible with all standard 16450 and 16550 UARTs * Implements all standard serial interface protocols - 5, 6, 7 or 8 bits per character - Odd, Even or no parity detection and generation - 1, 1.5 or 2 stop bit detection and generation - Internal baud rate generator and separate receiver clock input - Modem control functions - Prioritized transmit, receive, line status and modem control interrupts - False start bit detection and recover - Line break detection and generation - Internal loop back diagnostic functionality - Independent 16 word transmit and receive FIFOs
Design Tool Requirements Xilinx Implementation Tools Verification Simulation Synthesis ISE 9.1i or later Modelsim SE /EE6.0c or later ModelSim SE/EE 6.0c or later XST 9.1i or later
(c) 2006=2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
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XPS 16550 UART (v1.00a)
Functional Description
The XPS 16550 UART implements the hardware and software functionality of the ubiquitous National Semiconductor 16550 UART, that works in both 16450 and 16550 UART modes. For complete details please refer the National Semiconductor data sheet. The XPS 16550 UART performs parallel to serial conversion on characters received from the CPU and serial to parallel conversion on characters received from a modem or microprocessor peripheral. The XPS 16550 UART is capable of transmitting and receiving 8, 7, 6, or 5 bit characters, with 2, 1.5 or 1 stop bits and odd, even or no parity. The XPS 16550 UART can transmit and receive independently. The device can be configured and it's status monitored via the internal register set. The XPS 16550 UART is capable of signaling receiver, transmitter and modem control interrupts. These interrupts can be masked, are prioritized and can be identified by reading an internal register. The device contains a 16 bit, programmable, baud rate generator and independent 16 word transmit and receive FIFOs. The FIFOs can be enabled or disabled through software control. The top-level block diagram for the XPS 16550 UART is shown in Figure 1.
Figure Top x-ref 1
PLB
PLB Interface Module
IPIC Interface
IPIC_IF
UART Interface UART16550
Serial Interface Modem Interface
Figure 1: XPS UART16550 Top-level Block Diagram
The top level modules of the XPS 16550 UART are: * PLB Interface Module * IPIC_IF * UART16550 The detailed block diagram for the XPS 16550 UART is shown in Figure 2.
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DS577 April 18, 2007 Product Specification
XPS 16550 UART (v1.00a)
Figure Top x-ref 2
IP2INTC_Irpt
Freeze
UART16550 Bus2IP_Clk Bus2IP_Reset Receiver rxrdyN rclk sin sout txrdyN
IPIC_IF
wr rd
PLB
IP2Bus_Ack IP2Bus_Error Bus2IP_Data[24:31] IP2Bus_IntrEvent IP2Bus_Data[24:31]
Decode and Control
RBR FIFO 1 THR FIFO 2 FCR LCR LSR IER IIR MCR MSR SCR DLL DLM
1
PLB Interface Module
Transmitter
baudoutN
Baud Generator
Modem Logic
xin xout ctsn dcdn dsrn rin dtrn rtsn out1N out2N ddis
Note: 1. 16450 UART mode does not support the FIFOs
2. 16450 UART mode does not support the FCR
Figure 2: XPS 16550 UART Detailed Block Diagram
PLB Interface Module PLB Interface Module provides bidirectional interface between UART 16550 IP core and the PLB. The base element of the PLB Interface Module is slave attachment, which provides the basic functionality of PLB slave operation. IPIC_IF IPIC_IF module incorporates logic to acknowledge the write and read transactions initiated by the plbv46 slave single module to write into the UART 16550 module registers and read from UART 16550 module registers. UART 16550 UART 16550 provides all the core features for transmission, reception of data and modem features of UART. The UART 16550 module of XPS 16550 UART can be configured for 16450 or 16550 mode of operation. This is accomplished by the usage of generic C_IS_A_16550. If C_IS_A_16550 set to one, the UART 16550 module has FIFOs instantiated to support 16550 mode of operation. When C_IS_A_16550 is set to zero, the UART 16x550 module works without FIFOs in 16450 mode.
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XPS 16550 UART (v1.00a)
XPS 16550 UART I/O Signals
The XPS 16550 UART I/O signals are listed and described in Table 1.
Table 1: XPS 16550 UART I/O Signals
Port
Signal Name
Interface
I/O
Initial State
Description
System Signals P1 Freeze System I Freezes UART for software debug (active high) Device interrupt output to microprocessor interrupt input or system interrupt controller (active high) PLB clock PLB reset (active high)
P2
IP2INTC_Irpt
System
O
0
P3 P4
SPLB_Clk SPLB_Rst
System System
I I
-
PLB Master Interface Signals P5 P6 P7 P8 P9 P10 P11 P12 PLB_ABus[0 : C_SPLB_AWIDTH-1] PLB_PAValid PLB_masterID[0 : C_SPLB_MID_WIDTH - 1] PLB_RNW PLB_BE[0 : [C_SPLB_DWIDTH/8] - 1] PLB_size[0 : 3] PLB_type[0 : 2] PLB_wrDBus[0 : C_SPLB_DWIDTH - 1] PLB PLB PLB PLB PLB PLB PLB PLB I I I I I I I I PLB address bus PLB primary address valid indicator PLB current master identifier PLB read not write PLB byte enables PLB transfer size PLB transfer type PLB write data bus
Unused PLB Master Interface Signals P13 P14 P15 P16 P17 P18 P19 P20 P21 PLB_UABus[0 : 31] PLB_SAValid PLB_rdPrim PLB_wrPrim PLB_abort PLB_busLock PLB_MSize[0 : 1] PLB_TAttribute[0 : 15] PLB_lockerr PLB PLB PLB PLB PLB PLB PLB PLB PLB I I I I I I I I I PLB upper address bits PLB secondary address valid PLB secondary to primary read request indicator PLB secondary to primary write request indicator PLB abort bus request PLB bus lock PLB data bus width indicator PLB transfer attribute PLB lock error
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DS577 April 18, 2007 Product Specification
XPS 16550 UART (v1.00a)
Table 1: XPS 16550 UART I/O Signals (Contd)
Port
P22 P23 P24 P25 P26 P27 P28
Signal Name
PLB_wrBurst PLB_rdBurst PLB_wrPendReq PLB_rdPendReq PLB_rdPendPri[0 : 1] PLB_wrPendPri[0 : 1] PLB_reqPri[0 : 1]
Interface
PLB PLB PLB PLB PLB PLB PLB
I/O
I I I I I I I
Initial State
-
Description
PLB burst write transfer PLB burst read transfer PLB pending bus write request PLB pending bus read request PLB pending read request priority PLB pending write request priority PLB current request priority
PLB Slave Interface Signals P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 Sl_addrAck Sl_SSize[0 : 1] Sl_wait Sl_rearbitrate Sl_wrDack Sl_wrComp Sl_rdBus[0 : C_SPLB_DWIDTH-1] Sl_rdDack sl_rdComp Sl_MBusy[0 : C_SPLB_NUM_MASTERS - 1] Sl_MWrErr[0 : C_SPLB_NUM_MASTERS - 1] Sl_MRdErr[0 : C_SPLB_NUM_MASTERS - 1] PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB PLB O O O O O O O O O O O O 0 0 0 0 0 0 0 0 0 0 0 0 Slave address acknowledge Slave data bus size Slave wait indicator Slave rearbitrate bus indicator Slave write data acknowledge Slave write transfer complete indicator Slave read data bus Slave read data acknowledge Slave read transfer complete indicator Slave busy indicator Slave write error indicator Slave read error indicator
Unused PLB Slave Interface Signals P41 P42 P43 P44 Sl_wrBTerm Sl_rdWdAddr[0 : 3] Sl_rdBTerm Sl_MIRQ[0 : C_SPLB_NUM_MASTERS - 1] PLB PLB PLB PLB O O O O 0 0 0 0 Slave terminate write burst transfer Slave read word address Slave terminate read burst transfer Master interrupt request
UART Signals P45 baudoutN Serial O 1 Transmitter clock
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XPS 16550 UART (v1.00a)
Table 1: XPS 16550 UART I/O Signals (Contd)
Port
Signal Name
Interface
I/O
Initial State
Description
Receiver 16x clock (Optional, may be driven by baudoutN under control of the C_HAS_EXTERNAL_RCLK parameter) Serial data input Serial data output Baud rate generator reference clock (Optional, may be driven by SPLB_Clk under control of the C_HAS_EXTERNAL_XIN parameter) Inverted xin Clear to send (active low) Data carrier detect (active low) Data set ready (active low) Data terminal ready (active low) Ring indicator (active low)
P46
rclk
Serial
I
-
P47 P48
sin sout
Serial Serial
I O
1
P49
xin
Serial
I
-
P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61
xout ctsN dcdN dsrN dtrN riN rtsN ddis out1N our2N rxrdyN txrdyN
Serial Modem Modem Modem Modem Modem Modem User User User User User
O I I I O I O O O O O O
~xin 1
1 1 1 1 1 0
Request to send (active low) Driver disable. Low when CPU is reading XPS UART User controlled output User controlled output DMA control signal DMA control signal
XPS 16550 UART Design Parameters
To allow the user to create a XPS 16550 UART that is uniquely tailored for the user's system, certain features are parameterizable in the XPS 16550 UART design. This allows the user to have a design that
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DS577 April 18, 2007 Product Specification
XPS 16550 UART (v1.00a)
utilizes only the resources required by the system and runs at the best possible performance. the features that are parameterizable in the XPS 16550 UART core are as shown in Table 2.
Table 2: Design Parameters
Generic
Parameter Description
Parameter Name
System Parameters
Allowable Values
Default Value
VHDL Type
G1
XILINX FPGA Family
C_FAMILY
spartan3e, spartan3, spartan3a, spartan3an, virtex4, virtex5
virtex5
string
PLB Parameters G2 XPS 16550 UART Base Address XPS 16550 UART High Address PLB Data Bus Width PLB Address Bus Width PLB Point-to-Point or shared topology PLB master ID bus width Number of PLB masters Width of slave data bus Burst support C_BASEADDR Valid Word Aligned Address(1) C_HIGHADDR -C_BASEADDR must be a power of 2 >= to C_BASEADDR+1FFF(1) 32, 64, 128 32 0 : PLB shared topology 1 : Reserved log2(C_SPLB_NUM_MA STERS) with a minimum value of 1 1 - 16 32 0 None(2) std_logi c_vector std_logi c_vector integer integer integer
G3
C_HIGHADDR
None(2)
G4 G5 G6
C_SPLB_DWIDTH C_SPLB_AWIDTH C_SPLB_P2P C_SPLB_MID_WIDT H C_SPLB_NUM_MAST ERS C_SPLB_NATIVE_D WIDTH C_SPLB_SUPPORTS _BURST 16550 UART Interface
32 32 0
G7
3
integer
G8 G9 G10
8 32 0
integer integer integer
G11
External xin
C_HAS_EXTERNAL_ XIN C_HAS_EXTERNAL_ RCLK C_IS_A_16550
0 : xin is open 1 : xin is driven by SPLB_Clk 0 : rclk is open 1 : rclk is driven by baudoutN 0 : 16450 mode 1 : 16550 mode
0
integer
G12
External rclk Select 16450/16550 UART
0
integer
G13
1
integer
Notes: 1. Address range specified by C_BASEADDR and C_HIGHADDR must be at least 0x2000 and must be a power of 2. 2. No default value will be specified to insure that the actual value is set, i.e. if the value is not set, a compiler error will be generated.
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XPS 16550 UART (v1.00a)
Parameter - Port Dependencies
The dependencies between the XPS 16550 UART core design parameters and I/O signals are described in Table 3. In addition, when certain features are parameterized out of the design, the related logic will no longer be a part of the design. The unused input signals and related output signals are set to a specified value.
Table 3: Parameter-Port Dependencies
Generic or Port
Name
Affects Depends
Design Parameters
Relationship Description
G4 G5 G7
C_SPLB_DWIDTH C_SPLB_AWIDTH C_SPLB_MID_WIDTH
P9, P12, P35 P5 P7 P38, P39, P40 P49 P46 I/O Signals
G8
Affects the size of the PLB data bus Affects the size of the PLB address bus Affects the width of the PLB master ID Identify the specific master on the PLB Connects xin to baudoutN Connects rclk to SPLB_Clk
G8 G11 G12
C_SPLB_NUM_MASTERS C_HAS_EXTERNAL_XIN C_HAS_EXTERNAL_RCLK
-
P5 P7 P9 P12 P35 P38 P39 P40
PLB_ABus[0:C_SPLB_AWIDTH 1] PLB_masterID[0: C_SPLB_MID_WIDTH - 1] PLB_BE[0:[C_SPLB_DWIDTH/8] 1] PLB_wrDBus[0:C_SPLB_DWIDTH - 1] Sl_rdBus[0:C_SPLB_DWIDTH - 1] Sl_MBusy[0:C_SPLB_NUM_MAST ERS - 1] Sl_MWrErr[0:C_SPLB_NUM_MAS TERS - 1] Sl_MRdErr[0:C_SPLB_NUM_MAS TERS - 1] rclk
-
G5 G7 G4 G4 G4 G8 G8 G8
Width varies with the size of the PLB address bus Width varies with the size of the number of masters on the PLB Width varies with the size of the PLB data bus Width varies with the size of the PLB data bus Width varies with the size of the PLB data bus Width varies with the number of masters on the PLB Width varies with the number of masters on the PLB Width varies with the number of masters on the PLB This input is unconnected and rclk is connected to baudoutN, if C_HAS_EXTERNAL_RCLK = 0 This input is unconnected and xin is connected to SPLB_Clk, if C_HAS_EXTERNAL_XIN = 0
P46
P3
G12
P49
xin
P45
G11
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DS577 April 18, 2007 Product Specification
XPS 16550 UART (v1.00a)
XPS 16550 UART Register Definition
XPS 16550 UART Interface
The internal registers of the XPS 16550 UART are offset from the base address C_BASEADDR. Additionally, some of the internal registers are accessible only when bit 7 of the Line Control Register (LCR) is set. The XPS 16550 UART internal register set is described in Table 4.
Table 4: XPS 16550 UART Registers
Register Name
Receiver Buffer Register (RBR) Transmitter Holding Register (THR) Interrupt Enable Register (IER) Interrupt Identification Register (IIR) FIFO Control Register (FCR)(3) FIFO Control Register(2), (3) Line Control Register (LCR) Modem Control Register (MCR) Line Status Register (LSR) Modem Status Register (MSR) Scratch Register (SCR) Divisor Latch Register (DLL) Divisor Latch Register (DLM)
LCR(7)+ C_BASEADDR + Address
0 + C_BASEADDR + 0x1000 0 + C_BASEADDR + 0x1000 0 + C_BASEADDR + 0x1004 0 + C_BASEADDR + 0x1008 X + C_BASEADDR + 0x1008 1 + C_BASEADDR + 0x1008 X(1) + C_BASEADDR + 0x100C X(1) + C_BASEADDR + 0x1010 X(1) + C_BASEADDR + 0x1014 X(1) + C_BASEADDR + 0x1018 X(1) + C_BASEADDR + 0x101C 1 + C_BASEADDR + 0x1000 1 + C_BASEADDR + 0x1004
Access
Read Write Read/Write Read Write Read Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
Notes: 1. X denotes a don't care 2. FIFO Control Register is write only in the National PC16550D 3. 16450 UART mode implementation does not include this register
XPS 16550 UART Register Logic
This section tabulates the internal XPS 16550 UART registers, including their reset values (if any). Please refer to the National Semiconductor PC16550D UART with FIFOs data sheet (June, 1995) for a more detailed description of the register behavior. Receiver Buffer Register This is an 8-bit read register as shown in Figure 3. The Receiver Buffer Register contains the last received character. The bit definitions for the register are shown in Table 5. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 3
Reserved 0
RBR 23 24 25 26 27 28 29 30 31
Figure 3: Receiver Buffer Register (RBR)
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XPS 16550 UART (v1.00a)
Table 5: Receiver Buffer Register Bit Definitions
Bit
0-23 24-31
Name
Reserved RBR
Access
N/A Read
Reset Value
N/A "00000000"
Description
Reserved. Set to zeroes on read Last received character
Transmitter Holding Register This is an 8-bit write register as shown in Figure 4. The Transmitter Holding Register contains the character to be transmitted next. The bit definitions for the register are shown in Table 6. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 4
Reserved 0
THR 23 24 25 26 27 28 29 30 31
Figure 4: Transmit Holding Register (THR) Table 6: Transmitter Holding Register Bit Definitions
Bit
0-23 24-31
Name
Reserved THR
Access
N/A Write
Reset Value
N/A "11111111" Reserved
Description
Holds the character to be transmitted next
Interrupt Enable Register This is an 8-bit read/write register as shown in Figure 5. The Interrupt Enable Register contains the bits which enable interrupts. The bit definitions for the register are shown in Table 7. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 5
Reserved
0
EDSSI ETBEI 23 24 25 26 27 28 29 30 31
ELSI
ERBFI
Figure 5: Interrupt Enable Register (IER) Table 7: Interrupt Enable Register Bit Definitions
Bit
0-23 24-27 28
Name
Reserved N/A EDSSI
Access
N/A Read/Write Read/Write
Reset Value
N/A "0000"(1) '0' Reserved
Description
Always returns "0000" Enable Modem Status Interrupt '0' = Disables Modem Status Interrupts '1' = Enables Modem Status Interrupts Enable Receiver Line Status Interrupt '0' = Disables Receiver Line Status Interrupts '1' = Enables Receiver Line Status Interrupts
29
ELSI
Read/Write
'0'
10
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DS577 April 18, 2007 Product Specification
XPS 16550 UART (v1.00a)
Table 7: Interrupt Enable Register Bit Definitions (Contd)
Bit
Name
Access
Reset Value
Description
Enable Transmitter Holding Register Empty Interrupt '0' = Disables Transmitter Holding Register Empty Interrupts '1' = Enables Transmitter Holding Register Interrupts Enable Received Data Available Interrupt '0' = Disables Received Data Available Interrupts '1' = Enables Received Data Available Interrupts
30
ETBEI
Read/Write
'0'
31
ERBFI
Read/Write
'0'
Notes: 1. Reading these bits always return "0000"
Interrupt Identification Register This is an 8-bit read register as shown in Figure 6. The Interrupt Identification Register contains the priority interrupt identification. The bit definitions for the register are shown in Table 8. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 6
Reserved 0
FIFOEN
"00"
INTID2 INTPEND
23 24 25 26 27 28 29 30 31
Figure 6: Interrupt Identification Register (IIR) Table 8: Interrupt Identification Register Bit Definitions
Bit
0-23 24-25 26-27
Name
Reserved FIFOEN(3) N/A
Access
N/A Read Read
Reset Value
N/A "00" "00"(1) Reserved
Description
FIFOs Enabled. Always zero if not in FIFO mode Always returns "00" Interrupt ID "011" = Receiver Line Status (Highest) "010" = Received Data Available (Second) "110" = Character Timeout (Second) "001" = Transmitter Holding Register Empty (Third) "000" = Modem Status (Fourth) Interrupt Pending. Interrupt is pending when cleared
28(3)-30
INTID2
Read
"000"
31
INTPEND(2)
Read
'1'
Notes: 1. Reading these bits always return "00" 2. If INTPEND = '0', interrupt is pending. See National Semiconductor PC16550D data sheet for more detail 3. Bits are always zero in 16450 UART mode
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XPS 16550 UART (v1.00a)
FIFO Control Register(1) This is an 8-bit write/read register as shown in Figure 7. The FIFO Control Register contains the FIFO configuration bits. The bit definitions for the register are shown in Table 9. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 7
Reserved 0
RCVR FIFO DMA Mode RCVR FIFO Reset Trigger Level Select 23 24 25 26 27 28 29 30 31 "00" XMTFIFO FIFOEN Reset
Figure 7: FIFO Control Register (FCR) Table 9: FIFO Control Register Bit Definitions(1)
Bit
0-23
Name
Reserved RCVR FIFO Trigger Level Reserved DMA Mode Select XMIT FIFO Reset RCVR FIFO Reset FIFOEN
Access
N/A
Reset Value
N/A Reserved
Description
24-25
Read/Write
"00"
RCVR FIFO Trigger Level. "00" = 1 byte "01" = 4 bytes "10" = 8 bytes "11" = 14 bytes Always returns "00" DMA Mode Select '0' = Mode 0 '1' = Mode 1 Transmitter FIFO Reset '1' = Resets XMIT FIFO Receiver FIFO Reset '1' = Resets RCVR FIFO FIFO Enable '1' = Enables FIFOs
26-27 28
Read/Write Read/Write
"00"(2) '0'
29 30 31
Read/Write Read/Write Read/Write
'0' '0' '0'
1. FCR is not included in 16450 UART mode 2. Reading these bits always return "00"
Line Control Register This is an 8-bit write/read register as shown in Figure 8. The Line Control Register contains the serial communication configuration bits. The bit definitions for the register are shown in Table 10. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 8
Reserved 0
DLAB
Stick Parity
PEN
WLS
23 24 25 26 27 28 29 30 31 Set Break EPS STB
Figure 8: Line Control Register (LCR)
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DS577 April 18, 2007 Product Specification
XPS 16550 UART (v1.00a)
Table 10: Line Control Register Bit Definitions
Bit
0-23 24
Name
Reserved DLAB
Access
N/A Read/Write
Reset Value
N/A '0' Reserved
Description
Divisor Latch Access Bit. '1' = Allows access to the Divisor Latch Registers and reading of the FIFO Control Register Set Break '1' = Sets SOUT to '0' Stick Parity '1' = When bits 28, 27 are logic1 the Parity bit is transmitted and checked as a logic 0. If bit 28 is a logic 0 then the Parity bit is transmitted and checked as a logic 1. '0' = Stick Parity is disabled Even Parity Select '1' = Selects Even parity '0' = Selects Odd parity Parity Enable '1' = Enables parity Number of Stop Bits '0' = 1 Stop bit '1' = 2 Stop bits or 1.5 if 5 bits/character selected Word Length Select "00" = 5 bits/character "01" = 6 bits/character "10" = 7bits/character "11" = 8bits/character
25
Set Break
Read/Write
'0'
26
Stick Parity
Read/Write
'0'
27
EPS
Read/Write
'0'
28
PEN
Read/Write
'0'
29
STB
Read/Write
'0'
30-31
WLS
Read/Write
"00"
Modem Control Register This is an 8-bit write/read register as shown in Figure 9. The Modem Control Register contains the modem signalling configuration bits. The bit definitions for the register are shown in Table 11. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 9
Reserved
"000"
Out2
RTS
0
23 24 25 26 27 28 29 30 31 Loop Out1
DTR
Figure 9: Modem Control Register (MCR) Table 11: Modem Control Register Bit Definitions
Bit
0-23 24-26 27
Name
Reserved N/A Loop
Access
N/A Read/Write Read/Write
Reset Value
N/A "000"(1) '0' Reserved Always "000"
Description
Loop Back '1' = Enables loop back
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XPS 16550 UART (v1.00a)
Table 11: Modem Control Register Bit Definitions (Contd)
Bit
28
Name
Out2
Access
Read/Write
Reset Value
'0'
Description
User Output 2 '1' = Drives OUT2N low '0' = Drives OUT2N high User Output 1 '1' = Drives OUT1N low '0' = Drives OUT1N high Request To Send '1' = Drives RTSN low '0' = Drives RTSN high Data Terminal Ready '1' = Drives DTRN low '0' = Drives DTRN high
29
Out1
Read/Write
'0'
30
RTS
Read/Write
'0'
31
DTR
Read/Write
'0'
Notes: 1. Reading these bits always return "000"
Line Status Register This is an 8-bit write/read register as shown in Figure 10. The Line Status Register contains the current status of receiver and transmitter. The bit definitions for the register are shown in Table 12. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 10
Reserved
Error in RCVR FIFO THRE
FE
OE
0
23 24 25 26 27 28 29 30 31 TEMT BI PE DR
Figure 10: Line Status Register (LSR) Table 12: Line Status Register Bit Definitions
Bit
0-23 24 25 26 27
Name
Reserved Error in RCVR FIFO TEMT THRE BI
Access
N/A Read/Write Read/Write Read/Write Read/Write
Reset Value
N/A '0' '1' '1' '0' Reserved
Description
Error in RCVR FIFO RCVR FIFO contains at least one receiver error Transmitter Empty Transmitter Holding Register Empty Break Interrupt Set when SIN is held low for an entire character time Framing Error Character missing a stop bit. Receiver resynchronizes with next character, if possible
28
FE
Read/Write
'0'
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XPS 16550 UART (v1.00a)
Table 12: Line Status Register Bit Definitions (Contd)
Bit
29 30 31
Name
PE OE DR
Access
Read/Write Read/Write Read/Write
Reset Value
'0' '0' '0' Parity Error
Description
Overrun Error RBR not read before next character is received Data Ready
Modem Status Register This is an 8-bit write/read register as shown in Figure 11. The Modem Status Register contains the current state of the Modem Interface. The bit definitions for the register are shown in Table 13. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 11
Reserved 0
DCD
DSR
DDCD DDSR
23 24 25 26 27 28 29 30 31 RI CTS TERI DCTS
Figure 11: Modem Status Register (MSR) Table 13: Modem Status Register Bit Definitions(1)
Bit
0-23 24 25 26 27 28 29 30 31
Name
Reserved DCD RI DSR CTS DDCD TERI DDSR DCTS
Access
N/A Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
Reset Value
N/A 'X' 'X' 'X' 'X' '0' '0' '0' '0' Reserved
Description
Data Carrier Detect Complement of DCDN input Ring Indicator Complement of RIN input Data Set Ready Complement of DSRN input Clear To Send Complement of CTSN input Delta Data Carrier Detect Change in DCDN since last MSR read Trailing Edge Ring Indicator RIN has changed from a low to a high Delta Data Set Ready Change in DSRN since last MSR read Delta Clear To Send Change in CTSN since last MSR read
Notes: 1. X represents bit driven by external input
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15
XPS 16550 UART (v1.00a)
Scratch Register This is an 8-bit write/read register as shown in Figure 11. The Scratch Register can be used to hold user data. The bit definitions for the register are shown in Table 14. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 12
Reserved 0
Scratch 23 24 25 26 27 28 29 30 31
Figure 12: Scratch Register (SCR) Table 14: Scratch Register Bit Definitions
Bit
0-23 24-31
Name
Reserved Scratch
Access
N/A Read/Write
Reset Value
N/A "00000000" Reserved
Description
Hold the data temporarily
Divisor Latch (Least Significant Byte) Register This is an 8-bit write/read register as shown in Figure 13. The Divisor Latch (Least Significant Byte) Register holds the least significant byte of the baud rate generator counter. The bit definitions for the register are shown in Table 15. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 13
Reserved 0
DLL 23 24 25 26 27 28 29 30 31
Figure 13: Divisor Latch (Least Significant Byte) Register
Divisor Latch (Most Significant Byte) Register
Table 15: Divisor Latch (Least Significant Byte) Register Bit Definitions
Bit
0-23 24-31
Name
Reserved DLL
Access
N/A Read/Write
Reset Value
N/A "00000000" Reserved
Description
Divisor Latch Least Significant Byte
This is an 8-bit write/read register as shown in Figure 14. The Divisor Latch (Most Significant Byte) Register holds the most significant byte of the baud rate generator counter. The bit definitions for the register are shown in Table 16. The offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
16
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XPS 16550 UART (v1.00a)
Figure Top x-ref 14
Unused
( g Register (DLL)
y)
0
23 24 25 26 27 28 29 30 31
Figure 14: Divisor Latch (Most Significant Byte) Register Table 16: Divisor (Most Significant Byte) Register Bit Definitions
Bit
0-23 24-31
Name
Reserved DLM
Access
N/A Read/Write
Reset Value
N/A "00000000" Reserved
Description
Divisor Latch Most Significant Byte
User Application Hints The use of the XPS 16550 UART in 16550 mode is outlined in the steps below. 1. The system programmer specifies the format of the asynchronous data communications exchange i.e Data bits (5,6,7 or 8), setting of parity ON and selecting on the even or odd parity, setting of the number stop bits for the transmission and set the Divisor latch access bit by programming the Line Control Register. Write Interrupt Enable Register to activate the individual interrupts Write to the FIFO Control Register to enable the FIFO's, clear the FIFO's, set the RCVR FIFO trigger level. Write to Divisor Latch least significant byte first and Divisor Latch most significant byte second for proper setting of the baud rate of the UART. Service the interrupts when ever an interrupt is triggered by the XPS 16550 UART.
2. 3. 4. 5.
An example use of the XPS 16550 UART with the operating mode set to the following parameters in 16550 mode explained below. - baud rate: 56Kbps - Enabled and Threshold settings for the FIFO receive buffer. - Format of asynchronous data exchange 8 data bits, Even parity and 2 stop bits 1. 2. Write 0x0000_0080 to Line Control Register.This configures DLAB bit which allows the writing into the Divisor Latch's Least significant and Most significant bytes. Write 0x0000_0002 to Divisor Latch's Least significant byte and write 0x0000_0000 to Divisor Latch's Most significant byte in that order. This configures the baud rate setup of UART to 56Kbps operation. Write 0x0000_001F to Line Control Register. This configures word length to 8 bits, Number of stop bits to 2, Parity is enabled and set to Even parity and DLAB bit is set to value 0 to enable the use of Transmit Holding register and Receive buffer register data for transmitting and reception of data. Write 0x0000_0011 to Interrupt Enable Register. This enables the Transmitter holding register empty interrupt and Receive data available interrupt. Write the buffer to Transmit Holding register and read the data received from Receive Holding register by servicing the interrupts generated.
3.
4. 5.
Design Implementation
Target Technology
The intended target technology is Virtex-4, Virtex-5 and Spartan-3 Family FPGAs.
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17
XPS 16550 UART (v1.00a)
Device Utilization and Performance Benchmarks
Since the XPS 16550 UART core will be used with other design modules in the FPGA, the utilization and timing numbers reported in this section are estimates only. When the XPS 16550 UART core is combined with other designs in the system, the utilization of FPGA resources and timing of the XPS 16550 UART design will vary from the results reported here. The XPS 16550 UART resource utilization for various parameter combinations measured with Virtex-4 as the target device are detailed Table 17.
Table 17: Performance and Resource Utilization Benchmarks on Virtex-4 (xc4vlx40-ff1148-11)
Parameter Values
C_HAS_EXTERNAL_RCLK C_SPLB_NUM_MASTERS C_HAS_EXTERNAL_XIN
Device Resources
Performance
C_SPLB_DWIDTH
Slice Flip-Flops
C_IS_A_16550
C_SPLB_P2P
0 0 0 0 1 1 1 1
1 4 8 8 8 1 1 16
1 0 0 0 0 0 0 0
32 64 128 128 64 128 128 128
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
293 413 437 505 408 415 447 508
271 322 325 374 368 360 359 383
401 404 577 564 543 554 544 577
214 206 203 202 222 210 220 206
The XPS 16550 UART resource utilization for various parameter combinations measured with Virtex-5 as the target device are detailed Table 18.
Table 18: Performance and Resource Utilization Benchmarks on Virtex-5 (xc5vlx50-ff1153-2)
Parameter Values
C_HAS_EXTERNAL_RCLK C_SPLB_NUM_MASTERS C_HAS_EXTERNAL_XIN
Device Resources
Performance
C_SPLB_DWIDTH
Slice Flip-Flops
C_IS_A_16550
C_SPLB_P2P
0 0 0
1 4 8
1 0 0
32 64 128
0 0 1
0 1 0
258 313 319
292 298 303
18
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fMAX (MHz)
LUTs
247 212 213
fMAX (MHz)
Slices
LUTs
XPS 16550 UART (v1.00a)
Table 18: Performance and Resource Utilization Benchmarks on Virtex-5 (xc5vlx50-ff1153-2) (Contd)
0 1 1 1 1
8 8 1 1 16
0 0 0 0 0
128 64 128 128 128
1 0 0 1 1
1 0 1 0 1
369 365 356 356 379
409 402 397 398 385
210 215 228 267 231
The XPS 16550 UART resource utilization for various parameter combinations measured with Spartan-3E as the target device are detailed Table 19.
Table 19: Performance and Resource Utilization Benchmarks on Spartan-3E (xc3s1600e-fg484-5)
Parameter Values
C_HAS_EXTERNAL_RCLK C_SPLB_NUM_MASTERS C_HAS_EXTERNAL_XIN
Device Resources
Performance
C_SPLB_DWIDTH
Slice Flip-Flops
C_IS_A_16550
C_SPLB_P2P
0 0 0 0 1 1 1 1
1 4 8 8 8 1 1 16
1 0 0 0 0 0 0 0
32 64 128 128 64 128 128 128
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
306 406 374 541 488 464 456 487
261 316 322 375 371 362 362 385
358 362 369 555 552 545 548 567
136 115 115 119 118 119 126 126
Specification Exceptions
FIFO Control Register
The FIFO control register has been made read/write. Read access is controlled by setting Line Control Register bit 7.
System Clock
The asynchronous microprocessor interface of the National Semiconductor PC16550D is synchronized to the system clock input of the UART.
Register Addresses
All internal registers reside on a 32 bit word boundary not on 8-bit byte boundaries
Reference Documents
The following documents contain reference information important to understand the UART design:
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fMAX (MHz) 19
Slices
LUTs
XPS 16550 UART (v1.00a)
* National Semiconductor PC16550D UART with (http://www.national.com/pf/PC/PC16550D.html)
FIFOs
data
sheet
(June,
1995)
* IBM CoreConnect 128-Bit Processor Local Bus: Architecture Specifications version 4.6
Revision History
Date
10/10/06 4/20/07
Version
1.0 1.1 Initial Xilinx Release. Added Spartan-3 support.
Revision
20
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