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TECHNICAL NOTE
HIGH GRADE Specification HIGH RELIABILITY series
I2C BUS Serial EEPROMs
Supply voltage 1.8V~5.5V Operating temperature -40C~+85C type
BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W, BR24L16-W, BR24L32-W, BR24L64-W
Description
BR24L -W series is a serial EEPROM of I2C BUS interface method.
Features
Completely conforming to the world standard I2C BUS. All controls available by 2 ports of serial clock (SCL) and serial data (SDA) Other devices than EEPROM can be connected to the same port, saving microcontroller port 1.8 ~ 5.5V*1 single power source action most suitable for battery use Page write mode useful for initial value write at factory shipment Highly reliable connection by Au pad and Au wire Auto erase and auto end function at data rewrite Low current consumption At write action (5V) : 1.2mA (Typ.)*2 At read action (5V) : 0.2mA (Typ.) At standby action (5V) : 0.1A (Typ.) Write mistake prevention function Write (write protect) function added Write mistake prevention function at low voltage SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J compact package *3 *4 Data rewrite up to 1,000,000 times Data kept for 40 years Page write Noise filter built in SCL / SDA terminal Number of Shipment data all address FFh
*1 *2 *3 *4 BR24L16-W, BR24L32-W : 1.7~5.5V BR24L32-W, BR24L64-W: 1.5mA BR24L32-W: SOP8/SOP-J8/ SSOP-B8/TSSOP-B8 BR24L64-W: SOP8/SOP-J8
pages
8 Byte
16 Byte
32 Byte
Product number
BR24L01A-W BR24L02-W
BR24L04-W BR24L08-W BR24L16-W
BR24L32-W BR24L64-W
BR24L series
Capacity 1Kbit 2Kbit 4Kbit 8Kbit 16Kbit 32Kbit 64Kbit Bit format 128 x 8 256 x 8 512 x 8 1K x 8 2K x 8 4K x 8 8K x 8 Type BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W
Power source voltage
SOP8
SOP-J8
SSOP-B8
TSSOP-B8
MSOP8
TSSOP-B8J
1.8 ~ 5.5V 1.8 ~ 5.5V 1.8 ~ 5.5V 1.8 ~ 5.5V 1.7 ~ 5.5V 1.7 ~ 5.5V 1.8 ~ 5.5V
Ver.B Oct.2005
Absolute maximum ratings (Ta=25C)
Parameter
Impressed voltage
Recommended action conditions
Parameter Symbol
Power source voltage Input voltage
Memory cell characteristics (Ta = 25C, Vcc = 1.8 ~ 5.5V)*1
Parameter Number of data rewrite times Data hold years
*2 *2
Symbol
Limits
Unit
Limits
Unit
*1
Limits
VCC
-0.3 ~ +6.5
V
*1 *2 *3 *4 *5
VCC VIN
1.8 ~ 5.5 0 ~ VCC
V V
Min. 1,000,000 40
Typ. -
Max. -
Unit Times Years
450 (SOP8) 450 (SOP-J8)
Permissible dissipation
*1 BR24L16/L32-W : 1.7~5.5V
Pd
300 (SSOP-B8) 330 (TSSOP-B8) 310 (MSOP8)
mW
Shipment data all address FFh
*1 BR24L16/L32-W : 1.7~5.5V *2 Not 100% TESTED
310 (TSSOP-B8J) *6
Storage temperature range Action temperature range
Tstg Topr -
-65 ~ +125 -40 ~ +85 -0.3 ~ VCC+1.0
C C
V
Terminal voltage
* When using at Ta = 25C or higher, 4.5mW (*1, *2), 3.0mW (*3), 3.3mW (*4) 3.1mW (*5,*6) to be reduced per 1C
Action timing characteristics
*1
SCL frequency Data clock "HIGH" time Data clock "LOW" time SDA,SCL rise time SDA,SCL fall time
*2 *2
Electrical characteristics
Parameter
"HIGH" input voltage 1 "LOW" input voltage 1 "HIGH" input voltage 2 "LOW" input voltage 2 "HIGH" input voltage 3 *3 "HIGH" input voltage 3 *4 "LOW" input voltage 3 *2 "LOW" output voltage 1 "LOW" output voltage 2 Input leak current Output leak current Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIH3 VIL3 VOL1 VOL2 ILI ILO ICC1 ICC2 Standby current ISB Min. 0.7VCC -0.3 *2 0.8VCC -0.3 *2 0.8VCC 0.9VCC -0.3 -1 -1 Limits Typ. Max. VCC+1.0 *2 0.3VCC VCC+1.0 *2 0.2VCC VCC+1.0 VCC+1.0 0.1VCC 0.4 0.2 1 1 2.0 *5 3.0 *6 0.5 2.0 Unit V V V V V V V V V A A mA mA A Conditions 2.5VVCC5.5V 2.5VVCC5.5V 1.8VVCC<2.5V 1.8VVCC<2.5V 1.7VVCC<1.8V 1.7VVCC<1.8V 1.7VVCC<1.8V IOL=3.0mA, 2.5VVCC5.5V, (SDA) IOL=0.7mA, 1.7VVCC<2.5V, (SDA) VIN=0V ~ VCC VOUT=0V ~ VCC (SDA) VCC=5.5V, fSCL=400kHz, tWR=5ms, Byte write, page write
(Unless otherwise specified, Ta=-40 ~ +85C, Vcc=1.8 ~ 5.5V)
Parameter
*1
(Unless otherwise specified, Ta = -40 ~ +85C, Vcc = 1.8 ~ 5.5V)
Symbol fSCL tHIGH tLOW tR tF
FAST-MODE 2.5VVcc5.5V Min. 0.6 1.2 0.6 0.6 0 100 0.1 0.1 0.6 1.2 0 0.1 1.0 Typ. Max. 400 0.3 0.3 0.9 5 0.1 -
STANDARD-MODE 1.8VVcc5.5V Min. 4.0 4.7 4.0 4.7 0 250 0.2 0.2 4.7 4.7 0 0.1 1.0 Typ. Max. 100 1.0 0.3 3.5 5 0.1 -
Unit kHz s s s s s s ns ns s s s s ms s ns s s
Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition setup time Bus release time before transfer start Internal write cycle time Noise removal valid period (SDA,SCL terminal) WP hold time WP setup time WP valid time
tHD:STA tSU:STA tHD:DAT tSU:DAT
tPD
tDH tSU:STO
tBUF tWR tl
Current consumption at action
VCC=5.5V, fSCL=400kHz Random read, current read, sequential read VCC=5.5V, SDA*SCL=VCC, A0, A1, A2=GND, WP=GND
tHD:WP tSU:WP tHIGH:WP
Radiation resistance design is not made.
*1 *2 *3
BR24L16/L32-W : 1.7~5.5V BR24L16/L32-W BR24L16-W
*4 *5 *6
BR24L32-W BR24L01A/L02/L04/L08/L16-W BR24L32/L64-W
*1 BR24L16/L32-W : 1.7~5.5V *2 Not 100% tested.
FAST-MODE and STANDARD-MODE FAST-MODE and STANDARD-MODE are of same actions, and mode is not changed. They are distinguished by action speeds. 100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the maximum action frequency, so 100kHz clock may be used in FAST-MODE. When power source voltage goes down, action at high speed is not carried out, therefore, at Vcc = 2.5V ~ 5.5V, 400kHz, namely, action is made in FASTMODE. (Action is made also in STANDARD-MODE) Vcc = 1.8V ~ 2.5V is only action in 100kHz STANDARD-MODE.
Sync data input / output timing
tR SCL tHD : STA SDA (Input) tBUF SDA (Output) tPD tDH
WP
tF
tHIGH
SCL
tSU : DAT
tLOW
tHD : DAT
SDA D1
DATA (1) D0
DATA (n)
ACK
ACK tWR
Stop condition
Input read at the rise edge of SCL Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
tSU : WP
Fig.1-(d) WP timing at write execution
tHD : WP
SCL
SCL tSU : STA SDA
SDA D1
tHD : STA
tSU : STO
DATA (1) D0 DATA (n)
ACK
ACK
START BIT
STOP BIT
WP
tHIGH : WP
tWR
Fig.1-(b) Start - stop bit timing
SCL
At write execution, in the area from the DO taken clock rise of the first DATA (1), to tWR, set WP = "LOW". By setting WP "HIGH" in the area, write can be cancelled. When it is set WP = "HIGH" during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again.
D0
Write data (n-th address)
SDA
ACK tWR
Stop condition
Fig.1-(e) WP timing at write cancel
Start condition
Fig.1-(c) Write cycle timing
2/16
Block diagram
*2
A0
1
7bit 11bit 8bit 12bit 9bit 13bit 10bit
1Kbit ~ 64Kbit EEPROM array
*1
8 8bit
VCC
*2
A1
*2
2
Address decoder
7bit 11bit 8bit 12bit 9bit 13bit 10bit
*1
Slave - word address register
STOP
Data register
7
WP
A2
3
START
Control circuit ACK
High voltage generating circuit Power source voltage detection
6
SCL
GND
4
5
SDA
*1
Pin assignment and description
7bit : BR24L01A-W 8bit : BR24L02-W 9bit : BR24L04-W 10bit : BR24L08-W 11bit : BR24L16-W 12bit : BR24L32-W 13bit : BR24L64-W
: BR24L04-W *2 A0=N.C. : BR24L08-W A0, A1=N.C. A0, A1=N.C. A2=Don't Use : BR24L16-W
Fig.2 Block diagram
A0
1
8
VCC
Terminal name
VCC
Input / output Input Input Input Input Input/ output Input
Function
BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W
Connect the power source. Reference voltage of all input / output, 0V
Slave address setting Slave address setting Slave address setting Slave address setting Slave address setting Slave address setting Not connected Slave address setting Slave address setting Not connected Not connected Slave address setting Not connected Not connected Not used Slave address setting Slave address setting Slave address setting Slave address setting Slave address setting Slave address setting
A1
2
A2
3
BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W
7
WP
GND A0 A1 A2 SCL
6 SCL
Serial clock input Slave and word address, Serial data input serial data output Write protect terminal
GND
4
5 SDA
SDA
WP
Characteristic data (The following values are Typ. ones.)
6
H INPUT VOLTAGE : VIH (V)
6
L OUTPUT VOLTAGE : VOL (V)
1 0.8 0.6
Ta=25C
4 3 2 1 0 0
SPEC
L INPUT VOLTAGE : VIL (V)
5
5 4 3 2 1 0 0
Ta=85C Ta=-40C Ta=25C
0.4
SPEC
Ta=85C Ta=-40C Ta=25C
Ta=85C
0.2
Ta=-40C
*1
1 2 3 4 5 6
SUPPLY VOLTAGE : VCC (V)
SPEC
Fig.3 H input voltage VIH (A0,A1,A2,SCL,SDA,WP) *1
1
L OUTPUT VOLTAGE : VOL (V)
BR24L16-W No A0, A1, A2 BR24L08-W No A0, A1 BR24L04-W No A0
INPUT LEAK CURRENT : ILI (A)
1
2
3
4
5
6
0 0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
L OUTPUT CURRENT : IOL (mA)
Fig.4 L input voltage VIL (A0,A1,A2,SCL,SDA,WP) *1
1.2 1 0.8 0.6 0.4 0.2 0 0
Ta=85C Ta=25C Ta=-40C
Fig.5 L output voltage VOL-IOL(VCC=1.8V)
1.2
OUTPUT LEAK CURRENT : ILO (A)
SPEC SPEC
0.8 0.6
SPEC
1 0.8 0.6 0.4 0.2 0 0
Ta=85C Ta=25C Ta=-40C
0.4
Ta=25C
0.2 0 0
Ta=85C
Ta=-40C
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
6
L OUTPUT CURRENT : IOL (mA)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.6 L output voltage VOL-IOL(VCC=2.5V)
Fig.7 Input leak current ILI (A0,A1,A2,SCL,WP) *1
Fig.8 Output leak current ILO (SDA)
3/16
Characteristic data
2.5
CURRENT CONSUMPTION AT WRITING : ICC1 (mA)
3.5
CURRENT CONSUMPTION AT WRITING : ICC1 (mA)
[BR24L01A/02/04/08/16 series] SPEC fSCL=400kHz DATA=AAh
2 1.5
3 2.5 2 1.5 1 0.5 0 0 1 2 3
fSCL=400kHz DATA=AAh
CURRENT CONSUMPTION AT READING : ICC2 (mA)
[BR24L32/64 series] SPEC
0.6
SPEC
0.5 0.4 0.3
Ta=85C Ta=25C fSCL=400kHz DATA=AAh
Ta=25C
Ta=25C Ta=85C Ta=-40C
1
Ta=85C Ta=-40C
0.2 0.1 0 0
Ta=-40C
0.5
0 0
1
2
3
4
5
6
4
5
6
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.9 Consumption current at write action ICC1 (fSCL=400kHz)
2.5
CURRENT CONSUMPTION AT WRITING : ICC1 (mA)
[BR24L01A/02/04/08/16 series] SPEC fSCL=100kHz DATA=AAh
Fig.10 Consumption current at write action ICC1 (fSCL=400kHz)
3.5
CURRENT CONSUMPTION AT WRITING : ICC1 (mA)
[BR24L32/64 series] SPEC
fSCL=100kHz DATA=AAh
Fig.11 Consumption current at read action ICC2 (fSCL=400kHz)
0.6
CURRENT CONSUMPTION AT READING : ICC2 (mA)
SPEC
2
3 2.5 2 1.5 1 0.5 0 0 1 2
0.5 0.4 0.3 0.2 0.1 0 0
Ta=85C Ta=25C fSCL=100kHz DATA=AAh
1.5
Ta=25C
Ta=25C Ta=85C Ta=-40C
1
Ta=85C Ta=-40C
0.5
Ta=-40C
0 0
1
2
3
4
5
6
3
4
5
6
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.12 Consumption current at write action ICC1 (fSCL=100kHz)
2.5
STANDBY CURRENT : ISB (A)
SPEC
Fig.13 Consumption current at write action ICC1 (fSCL=100kHz)
10000
DATA CLK H TIME : tHIGH (s)
SCL FREQUENCY : fSCL (kHz)
Ta=85C Ta=25C Ta=-40C
Fig.14 Consumption current at read action ICC2 (fSCL=100kHz)
5 4 3 2 1 0 0
Ta=-40C Ta=25C Ta=85C SPEC2
2 1.5 1 0.5
Ta=85C Ta=25C Ta=-40C
1000
SPEC1
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
100
SPEC2
10
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
SPEC1
0 0
1
2
3
4
5
6
1 0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
Fig.15 Standby current ISB
START CONDITION HOLD TIME : tHD:STA (s)
Fig.16 SCL frequency fSCL
START CONDITION SET UP TIME : tSU:STA (s)
Fig.17 Data clock "H" time tHIGH
6 5 4 3 2 1 0 0
Ta=-40C Ta=25C Ta=85C SPEC1 SPEC2
5
SPEC2
5 4 3 2 1 0 0
Ta=-40C Ta=25C Ta=85C SPEC2
DATA CLK L TIME : tLOW (s)
4 3 2 1 0 0
Ta=85C Ta=25C Ta=-40C SPEC1
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
SPEC1
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.18 Data clock "L" time tLOW
Fig.19 Start condition hold time tHD:STA
50
INPUT DATA HOLD TIME : tHD:DAT (ns)
Fig.20 Start condition setup time tSU:STA
INPUT DATA HOLD TIME : tHD:DAT (ns)
SPEC1,2
SPEC1,2
INPUT DATA SET UP TIME : tSU:DAT (ns)
50 0
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
300 200 100 0 -100 -200 0
Ta=85C Ta=25C Ta=-40C SPEC2
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
0
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
-50 -100 -150 -200 0
Ta=85C Ta=25C Ta=-40C
-50 -100 -150
Ta=25C Ta=-40C Ta=85C
SPEC1
1
2
3
4
5
6
-200 0
1
2
3
4
5
6
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.21 Input data hold time tHD:DAT(HIGH)
Fig.22 Input data hold time tHD:DAT(LOW)
Fig.23 Input data setup time tSU:DAT(HIGH)
4/16
Characteristic data
INPUT DATA SET UP TIME : tSU:DAT (ns)
300 200 100 0 -100 -200 0
Ta=25C Ta=85C SPEC2
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
4
OUTPUT DATA DELAY TIME : tPD (s) OUTPUT DATA DELAY TIME : tPD (s)
SPEC2
4
SPEC2
3
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
3
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
SPEC1
2
Ta=85C Ta=25C Ta=-40C
2
Ta=85C Ta=25C Ta=-40C
Ta=-40C
1
SPEC1
1
SPEC1
SPEC2
SPEC2
1
2
3
4
5
6
0 0
SPEC1
1
2
3
4
5
6
0 0
SPEC1
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.24 Input data setup time tSU:DAT(LOW)
Fig.25 "L" output data delay time tPD0
Fig.26 "L" output data delay time tPD1
5
INTERNAL WRITING CYCLE TIME : tWR (ms) BUS OPEN TIME BEFORE TRANSMISSION : tBUF (s)
SPEC2
6 5 4 3
Ta=85C Ta=-40C Ta=25C
NOISE REDUCTION EFFECTIVE TIME : tI (SCL H) (s)
SPEC1,2
0.6
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
4 3 2
SPEC1
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
0.5
Ta=-40C
0.4
Ta=25C
0.3
Ta=85C
2 1
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
0.2 0.1
SPEC1,2
1 0 0
Ta=-40C Ta=25C Ta=85C
1
2
3
4
5
6
0 0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
0 0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
Fig.27 Bus release time before transfer start tBUF
Fig.28 Internal write cycle time tWR
Fig.29 Noise removal valid time tI (SCL H)
0.6
NOISE REDUCTION EFFECTIVE TIME : tI (SCL L) (s) NOISE REDUCTION EFFECTIVE TIME : tI (SDA H) (s)
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
0.6 0.5 0.4 0.3 0.2 0.1
SPEC1,2 Ta=25C Ta=-40C
0.6
NOISE REDUCTION EFFECTIVE TIME : tI (SDA L) (s)
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
0.5 0.4 0.3
Ta=-40C
0.5 0.4 0.3 0.2 0.1
SPEC1,2 Ta=-40C Ta=25C Ta=85C
Ta=85C
0.2 0.1
Ta=25C Ta=85C SPEC1,2
0 0
1
2
3
4
5
6
0 0
1
2
3
4
5
6
0 0
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.30 Noise removal valid time tI (SCL L)
Fig.31 Noise removal valid time tI (SDA H)
Fig.32 Noise removal valid time tI (SDA L)
0.2
WP EFFECTIVE TIME : tHIGH:WP (s) WP SET UP TIME : tSU:WP (s)
SPEC1,2
1.2 1 0.8
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
0
SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE
SPEC1,2
-0.2
Ta=85C
0.6 0.4 0.2 0 0
Ta=-40C Ta=25C Ta=85C
-0.4
Ta=25C
Ta=-40C
-0.6 0
1
2
3
4
5
6
1
2
3
4
5
6
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
Fig.33 WP setup time tSU:WP
Fig.34 WP valid time tHIGH:WP
5/16
I2C BUS communication
I2C BUS data communication I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial clock (SCL). Among devices, there are "master" that generates clock and control communication start and end, and "slave" that is controlled by addresses peculiar to devices. EEPROM becomes "slave". And the device that outputs data to bus during data communication is called "transmitter", and the device that receives data is called "receiver".
SDA
SCL S
1-7
8
9
1-7
8
9
1-7
8
9 P
START ADDRESS condition
R/W
ACK
DATA
ACK
DATA
ACK
STOP condition
Fig.35 Data transfer timing
Start condition (start bit recognition) Before executing each command, start condition (start bit) where SDA goes from "HIGH" down to "LOW" when SCL is "HIGH" is necessary. This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is satisfied, any command is executed. Stop condition (stop bit recognition) Each command can be ended by SDA rising from "LOW" to "HIGH" when stop condition (stop bit), namely, SCL is "HIGH" Acknowledge (ACK) signal This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (-COM at slave address input of write command, read command, and this IC at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. The device (this IC at slave address input of write command, read command, and -COM at data output of read command) at the receiver (receiving) side sets SDA "LOW" during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) "LOW". Each write action outputs acknowledge signal (ACK signal) "LOW", at receiving 8bit data (word address and write data). Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) "LOW". When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (-COM) side, this IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop condition (stop bit), and ends read action. And this IC gets in standby status. Device addressing Output slave address after start condition from master. The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to "1010". Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. The most insignificant bit (R/W --- READ/WRITE) of slave address is used for designating write or read action, and is as shown below. Setting R/W to 0 --- write (setting 0 to word address setting of random read) Setting R/W to 1 --- read
Type Slave address
Maximum number of connected buses
A0
1
8
VCC
BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W
1 1 1 1 1 1 1
0 0 0 0 0 0 0
1 1 1 1 1 1 1
0 0 0 0 0 0 0
A2 A2 A2 A2 P2 A2 A2
A1 A1 A1 P1 P1 A1 A1
A0 A0 PS P0 P0 A0 A0
R/W R/W R/W R/W R/W R/W R/W
8 8 4 2 1 8 8
A1
2
A2
3
BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W
7
WP
6 SCL
GND
4
5 SDA
PS, P0 ~ P2 are page select bits.
Note) Up to 4 units of BR24L04-W, up to 2 units of BR24L08-W, and one unit of BR24L16-W can be connected. Device address is set by "H" and "L" of each pin of A0, A1, and A2.
6/16
Command
Write cycle Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24L32 / L64-W)
S T A R T SDA LINE W R I T E
WA 7
SLAVE ADDRESS
1 0 1 0 A2 A1 A0
WORD ADDRESS
WA 0
DATA
S T O P
D0
D7
*1 As for WA7, BR24L01A-W becomes Don't Care.
A C K
Note)
RA /C WK
*1
A C K
Fig.36 Byte write cycle (BR24L01A/02/04/08/16-W)
S T A R T SDA LINE
SLAVE ADDRESS
1 0 1 0 A2 A1 A0
W R I T E
1st WORD ADDRESS ***
WA WA 12 11
2nd WORD ADDRESS
WA 0
DATA
S T O P
D0
D7
*1 As for WA12, BR24L32-W becomes Don't care.
A C K
Note)
RA /C WK
*1
A C K
A C K
Fig.37 Byte write cycle (BR24L32/64-W)
S T A R T SDA LINE
SLAVE ADDRESS
W R I T E
WORD ADDRESS (n)
DATA (n)
DATA (n+15)
*2
S T O P
1 0 1 0 A2 A1 A0
WA 7
WA 0
D7
D0
D0
*1
A C K A C K A C K
As for WA7, BR24L01A-W becomes Don't care. As for BR24L01A/L02-W becomes (n+7).
Note)
RA / C *1 WK
*2
Fig.38 Page write cycle (BR24L01A/02/04/08/16-W)
S T A R T SDA LINE
SLAVE ADDRESS
W R I T E
1st WORD ADDRESS (n)
2nd WORD ADDRESS (n)
DATA (n)
DATA (n+31)
S T O P
1 0 1 0 A2 A1 A0
*** RA /C WK
WA WA 12 11
WA 0
D7
D0
D0
*1
A C K
As for WA12, BR24L32-W becomes Don't care.
Note)
*1
A C K
A C K
A C K
Fig.39 Page write cycle (BR24L32/64-W)
Data is written to the address designated by word address (n-th address). By issuing stop bit after 8bit data input, write to memory cell inside starts. When internal write is started, command is not accepted for tWR (5ms at maximum). By page write cycle, the following can be written in bulk: Up to 8 bytes (BR24L01A-W, BR24L02-W) Up to 16 bytes (BR24L04-W, BR24L08-W, BR24L16-W) Up to 32 bytes (BR 24L32-W, BR24L64-W) And when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (Refer to "Internal address increment" of "Notes on page write cycle" in P8/16.) As for page write cycle of BR24L01A-W and BR24L02-W, after the significant 5 bits (4 significant bits in BR24L01-W) of word address are designated arbitrarily, and as for page write command of BR24L04-W, BR24L08-W, and BR24L16-W, after page select bit (PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bits in BR24L01A-W, and BR24L02-W) is incremented internally, and data up to 16 bytes (up to 8 bytes in BR24L01A-W and BR24L02-W) can be written. As for page write cycle of BR24L32-W and BR24L64-W, after the significant 7 bits (in the case of BR24L32-W) of word address, or the significant 8 bits (in the case of BR24L64-W) of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
Note)
*1*2*3
1 0 1 0 A2A1A0
Fig.40 Difference of slave address of each type
*1 In BR24L16-W, A2 becomes P2. *2 In BR24L08-W, BR24L16-W, A1 becomes P1. *3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0.
7/16
Notes on write cycle continuous input
At STOP (stop bit), write starts.
S T A R T SDA LINE
SLAVE ADDRESS
W R I T E
*1
WORD ADDRESS (n)
DATA (n)
DATA (n+7) *2 *3
S T O P
1010
1 0 1 0 A2 A1 A0
WA 7
WA 0
D7
D0
D0
Note)
RA /C WK
A C K
A C K
A C K
Next command
tWR (maximum : 5ms) Command is not accepted for this period.
*1 BR24L01A-W becomes Don't Care. *2 BR24L04W-W, BR24L08-W, and BR24L16-W become (n + 15). *3 BR24L32-W and BR24L64-W become (n + 31). Fig.41 Page write cycle
Note) Note) 1 0
3 1 * 1 * 2 * 3
11 0 01 0 A2A1A0 A2 A1 A0
*1 In BR24L16-W, A2 becomes P2. *2 In BR24L08-W, BR24L16-W, A1 becomes P1. *3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0.
Fig.42 Difference of each type of slave address Fig.42
Notes on page write cycle List of numbers of page write
Number of pages
8 Byte BR24L01A-W BR24L02-W
16 Byte BR24L04-W BR24L08-W BR24L16-W
32 Byte BR24L32-W BR24L64-W
Internal address increment Page write mode (in the case of BR24L02-W)
WA7 0 0 0 WA4 0 0 0 WA3 0 0 0
Product number
WA2 0 0 0
WA1 WA0 0 0 1 0 1 0
Increment
The above numbers are maximum bytes for respective types. Any bytes below these can be written.
In the case of BR24L02-W, 1 page = 8 bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write. It does not stand 5ms at maximum x 8 bytes = 40ms (Max.).
06h
0 0 0
0 0 0
0 0 0
1 1 0
1 1 0
0 1 0
Significant bit is fixed. No digit up
For example, when it is started from address 06h, therefore, increment is made as below, 06h 07h 00h 01h ---, which please note. * 06h --- 06 in hexadecimal, therefore, 00000110 becomes a binary number.
Write protect terminal (WP) Write protect function (WP) When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of all addresses is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open. At extremely low voltage at power ON/OFF, by setting the WP terminal "H", mistake write can be prevented. During tWR, set the WP terminal always to "L". If it is set "H", write is forcibly terminated.
8/16
Command
Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession.
S T A R T SDA LINE
SLAVE ADDRESS
W R I T E
WA 7
WORD ADDRESS(n)
WA 0
S T A R T
SLAVE ADDRESS
R E A D
D7
DATA(n)
S T O P
It is necessary to input "H" to the last ACK.
*1 As for WA7, BR24L01A-W become Don't care.
1 0 1 0 A2A1A0
1 0 1 0 A2A1A0
D0
Note)
R A *1 /C WK
A C K
RA /C WK
A C K
Fig.43 Random read cycle (BR24L01A/02/04/08/16-W)
S T A R T SDA LINE
SLAVE ADDRESS
W R I T E
1st WORD ADDRESS(n)
WA WA 12 11
2nd WORD ADDRESS(n)
WA 0
S T A R T
SLAVE ADDRESS
R E A D
D7
DATA(n)
S T O P
1 0 1 0 A2A1A0
***
1 0 1 0 A2A1A0
D0
*1 Note)
RA /C WK
*1
As for WA12, BR24L32-W become Don't care.
A C K
A C K
RA /C WK
A C K
Fig.44 Random read cycle (BR24L32/64-W)
S T A R T SDA LINE
SLAVE ADDRESS
R E A D
DATA
S T O P
It is necessary to input "H" to the last ACK.
1
0
1
0 A2 A1 A0
D7
D0
Note)
RA /C WK
A C K
Fig.45 Current read cycle
S T A R T SDA LINE
SLAVE ADDRESS
1 0 1 0 A2 A1 A0
R E A D
D7
DATA(n)
DATA(n+x)
D0 D7 D0
S T O P
It is necessary to input "H" to the last ACK.
A C K
Note)
RA /C WK
A C K
A C K
Fig.46 Sequential read cycle (in the case of current read cycle)
In random read cycle, data of designated word address can be read. When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n-th) address, i.e., data of the (n+1)-th address is output. When ACK signal "LOW" after D0 is detected, and stop condition is not sent from the master (-COM) side, the next address data can be read in succession. Read cycle is ended by stop condition where "H" is input to ACK signal after D0 and SDA signal is started at SCL signal "H". When "H" is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input "H" to ACK signal after D0, and to start SDA at SCL signal "H". Sequential read is ended by stop condition where "H" is input to ACK signal after arbitrary D0 and SDA is started at SCL signal "H".
Note)
*1*2*3
1 0 1 0 A2A1A0
Fig.47 Difference of slave address of each type
*1 In BR24L16-W, A2 becomes P2. *2 In BR24L08-W, BR24L16-W, A1 becomes P1. *3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0.
9/16
Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig. 48 (a), Fig. 48 (b) and Fig. 48 (c).) In dummy clock input area, release the SDA bus ("H" by pull up). In dummy clock area, ACK output and read data "0" (both "L" level) may be output from EEPROM, therefore, if "H" is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices.
Dummy clock x 14 SCL 1 2 13 14
Start x 2
Normal command
SDA
Normal command
Fig.48-(a) The case of dummy clock + START + START + command input
Start
Dummy clock x 9
Start
SCL
1
2
8
9
Normal command
SDA
Normal command
Fig.48-(b) The case of START + 9 dummy clocks + START + command input
Start x 9 SCL 1 2 3 7 8 9
Normal command
SDA
Normal command
Fig.48-(c) START x 9 + command input
* Start normal command from START input.
Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back "L", then it means end of write action, while if it sends back "H", it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal sends back "L", then execute word address input and data output and so forth.
First write command
During internal write, ACK = HIGH is sent back.
S T A R T
Write command
S T O P
S T A R T
Slave address
A C K H
S T A R T
Slave address
A C K H
tWR
Second write command
S T A R T
Slave address
A C K H
S T A R T
Slave address
A C K L
Word address
A C K L
Data
A C K L
S T O P
tWR
After completion of internal write, ACK = LOW is sent back, so input next word address and data in succession.
Fig.49 Case to continuously write by acknowledge polling
10/16
WP valid timing (write cancel)
WP is usually fixed to "H" or "L", but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, in cancel valid area, by setting WP = "H", write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data (in page write cycle, the first byte data) is cancel invalid area. WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP = "H" during tWR, write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig. 50.) After execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
Rise of D0 taken clock SCL SCL D1 D0 ACK
Rise of SDA D0 ACK Enlarged view
SDA
SDA
Enlarged view
SDA
S T A R T
Slave address
A C K L
Word address
A C K L
D7
D6
D5
D4
D3
D2
D1
D0
A C K L
Data
A C K L
S T O P
tWR
WP cancel invalid area WP
WP cancel valid area
Write forced end
Data is not written.
Data not guaranteed
Fig.50 WP valid timing
Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig. 51.) However, in ACK output area and during data read, SDA bus may output "L", and in this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Fig.51 Case of cancel by start, stop condition during slave address input
11/16
I/O peripheral circuit
Pull up resistance of SDA terminal SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance value from microcontroller VIL, IL, and VOL - IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the larger the consumption current at action. Maximum value of RPU The maximum value of RPU is determined by the following factors. (1) SDA rise time to be determined by the capacity (CBUS) of bus line of RPU and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. (2) The bus electric potential A to be determined by input leak total (IL) of device connected to bus at output of "H" to SDA bus and RPU should sufficiently secure the input "H" level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2VCC.
VCC-ILRPU - 0.2VCCVIH RPU = 0.8VCC-VIH IL Ex.) When VCC = 3V, IL = 10A, VIH = 0.7VCC, from ( 2 ) RPU 0.8 x3-0.7x 3 -6
10 x 10
Microcontroller RPU
BR24LXX
A
SDA terminal
IL
IL Bus line capacity CBUS
300[k ]
Fig.52 I/O circuit diagram
Minimum value of Rpu The minimum value of Rpu is determined by the following factors. (1) When IC outputs LOW, it should be satisfied that VOLMAX = 0.4V and IOLMAX = 3mA. VCC - VOL IOL
RPU RPU
VCC - VOL IOL
(2) VOLMAX = 0.4V should secure the input "L" level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1VCC. VOLMAX VIL - 0.1VCC Ex.) When VCC = 3V, VOL = 0.4V, IOL = 3mA, microcontroller, EEPROM VIL = 0.3VCC From (1),
RPU
3 - 0.4 3 x10-3
867[ ] And VOL =0.4[V] VIL =0.3 x 3 =0.9[V]
Therefore, the condition (2) is satisfied. Pull up resistance of SCL terminal When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes "Hi-Z", add a pull up resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller.
A0, A1, A2, WP process
Process of device address terminals (A0, A1, A2) Check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And, pins (N, C, PIN) not used as device address may be set to any of "H", "L", and "Hi-Z". Types with N.C. PIN BR24L16/F/FJ/FV/FVT/FVM/FVJ-WA0A1A2 BR24L08/F/FJ/FV/FVT/FVM/FVJ-WA0A1 BR24L04/F/FJ/FV/FVT/FVM/FVJ-WA0
Process of WP terminal WP terminal is the terminal that prohibits and permits write in hardware manner. In "H" status, only READ is available and WRITE of all addresses is prohibited. In the case of "L", both are available. In the case to use it as an ROM, it is recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect it to pull down or GND.
12/16
Cautions on microcontroller connection
Rs In I2C BUS, it is recommended that SDA port is of open drain input /output. However, when to use CMOS input / output of tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open drain input / output, Rs can be used.
ACK
RPU RS
SCL
SDA "H" output of microcontroller "L" output of EEPROM
Microcontroller
EEPROM
Over current flows to SDA line by "H" output of microcontroller and "L" output of EEPROM.
Fig.53 I/O circuit diagram
Fig.54 Input / output collision timing
Maximum value of Rs The maximum value of Rs is determined by the following relations. (1) SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. (2) The bus electric potential A to be determined by Rpu and Rs at the moment when EEPROM outputs "L" to SDA bus should sufficiently secure the input "L" level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC
RPU
A
RS IOL VOL
(VCC-VOL) x RS + VOL+0.1VCC VIL RPU+RS RS VIL-VOL-0.1VCC 1.1VCC-VIL x RPU
Bus line capacity CBUS
Example) When Vcc = 3V, VIL = 0.3Vcc, VOL = 0.4V, RPU = 20k ,
from (2), RS 0.3x3-0.4-0.1x3 1.1x3-0.3x3 x 20x103
VIL
Microcontroller
EEPROM
1.67 [k ]
Fig.55 I/O circuit diagram
Minimum value of Rs The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to EEPROM 10mA or below.
VCC I RS
RPU RS "L" output
RS
VCC I
Over current I "H" output
Example) When Vcc = 3V, I = 10mA, RS 3 10x10-3
Microcontroller
EEPROM
300 [ ]
Fig.56 I/O circuit diagram
13/16
I2C BUS input / output circuit
Input (A0, A2, SCL)
Fig.57 Input pin circuit diagram
Input / output (SDA)
Fig.58 Input / output pin circuit diagram
Input (A1, WP)
Fig.59 Input pin circuit diagram
14/16
Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following conditions at power on. 1. Set SDA = "H" and SCL = "L" or "H". 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR VCC
Recommended conditions of tR, tOFF, Vbot tR tOFF Vbot 10ms or below 10ms or higher 0.3V or below
Vbot
tOFF 0
100ms or below 10ms or higher 0.2V or below
Fig.60 Rise waveform diagram
3. Set SDA and SCL so as not to become "Hi-Z". When the above conditions 1 and 2 cannot be observed, take the following countermeasures. a) In the case when the above condition 1 cannot be observed. When SDA becomes "L" at power on. Control SCL and SDA as shown below, to make SCL and SDA, "H" and "H".
Vcc
tLOW
SCL
SDA After Vcc becomes stable tDH tSU:DAT After Vcc becomes stable tSU:DAT
Fig.61 When SCL = "H" and SDA = "L"
Fig.62 When SCL = "H" and SDA = "L"
b) In the case when the above condition 2 cannot be observed. After power source becomes stable, execute software reset (P10). c) In the case when the above conditions 1 and 2 cannot be observed. Carry out a), and then carry out b).
Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. = 1.2V) or below, it prevent data rewrite.
Vcc noise countermeasures
Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC Vcc and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
Cautions on use
(1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5) Thermal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
15/16
Selection of order type
BR
24
L
Operating temperature
01
F
-W
E2
Package specifications E2 : reel shape emboss taping TR : reel shape emboss taping (MSOP8 package only)
ROHM type BUS type name 24 : I2C
Capacity Package
Double cell
01 = 1K L : -4085 02 = 2K H : -40125 04 = 4K 08 = 8K 16 =16K 32 =32K 64 =64K
F : SOP8 FJ : SOP-J8 FV : SSOP-B8 FVT : TSSOP-B8 FVM : MSOP8 FVJ : TSSOP-B8J
Package specifications
SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J

* SOP8
5.00.2 8 6.20.3 4.40.2 5
* SOP-J8
4.90.2 8765 0.45Min. 6.00.3 3.90.2
* SSOP-B8
3.00.2 8 6.40.3 4.40.2 5 0.3Min.
* TSSOP-B8
0.50.15 1.00.2 3.00.1 85 6.40.2 4.40.1
* TSSOP-B8J
4.90.2 3.00.1 0.450.15 0.950.2 3.00.1 85
Package type Package quantity Package direction
Emboss taping 2500pcs E2 (When the reel is gripped by the left hand, and the tape is pulled out by the right hand, No.1 pin of the product is at the left top.)
0.3Min.
1.150.1
1.50.1
0.1
0.11
1.27 0.420.1
0.1
1.27 0.420.1
0.1
0.08 S 0.245 -0.04 0.65
+0.05
0.850.05
0.10.05
0.1 0.220.1 0.65
0.10.05
0.17
+0.1 -0.05
1.3750.1 0.175
1
4
1234
1 0.20.1
4
0.150.1 1.00.1
1
4
1 0.145 -0.03
+0.05
4
0.145 -0.03
1234 1234 1234 1234 1234 1234 1234 1234
+0.05
0.08 S 0.32 0.65
+0.05 -0.04
(0.52)
Pin No.1 Reel
Pulling side
(Unit : mm)
* For ordering, specify a number of multiples of the package quantity.
MSOP8

2.9 0.1 4.0 0.2 8 2.8 0.1 5
0.9Max. 0.75 0.05 0.08 0.05
0.475
1
4
0.22+0.05 -0.04 0.65 0.08 S
0.29 0.15 0.6 0.2
Package type Package quantity Package direction
Emboss taping 3000pcs TR (When the reel is gripped by the left hand, and the tape is pulled out by the right hand, No.1 pin of the product is at the right top.)
0.145+0.05 -0.03 0.08 M
Pin No.1 Reel
Pulling side
(Unit : mm)
* For ordering, specify a number of multiples of the package quantity.
The contents described herein are correct as of October, 2005 The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD. Any part of this application note must not be duplicated or copied without our permission. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. The products described herein utilize silicon as the main material. The products described herein are not designed to be X ray proof.
Published by Application Engineering Group
Catalog No. 05T822Ae '05.102000 TSU (c) ROHM
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the NOTES specified in this catalog.
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