 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| NCP3101 Product Preview Wide Input Voltage Synchronous Buck Converter The NCP3101 is a high efficiency, wide input, high output current, synchronous PWM buck converter designed to operate from a 4.5 V to 13.2 V supply. The device is capable of producing an output voltage as low as 0.8 V. The NCP3101 can continuously output 6 A through MOSFET switches driven by an internally set 275 kHz oscillator. The 40-pin device provides an optimal level of integration to reduce size and cost of the power supply. The NCP3101 also incorporates an externally compensated transconductance error amplifier and a capacitor programmable soft-start function. Protection features include programmable short circuit protection and under voltage lockout (UVLO). The NCP3101 is available in a 40-pin QFN package. Features http://onsemi.com MARKING DIAGRAM 1 40 QFN40, 6x6 CASE 485AK NCP3101 AWLYYWWG * * * * * * * * * * * * Input Voltage Range from 4.5 V to 13.2 V 275 kHz Internal Oscillator Greater than 90% Maximum Efficiency Boost Pin Operates to 25 V Voltage Mode PWM Control 0.8 V $1% Internal Reference Voltage Adjustable Output Voltage by Resistor Divider Capacitor Programmable Soft-Start 80% Maximum Duty Cycle Input Undervoltage Lockout Resistor Programmable Current Limit This is a Pb-Free Device A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package PIN CONNECTIONS Applications * Servers/Networking * DSP and FPGA Power Supply * DC-DC Regulator Modules Vin Vout PWRVCC CPHS VCC BST PWRPHS NCP3101 COMP/DIS FB AGND TGOUT TGIN BG PWRGND ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. GND GND Figure 1. Typical Application Diagram This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. (c) Semiconductor Components Industries, LLC, 2007 1 November, 2007 - Rev. P0 Publication Order Number: NCP3101/D NCP3101 VCC 13 POR UVLO FB 16 FAULT BST 24 TGOUT 21 TGIN 25 PWRVCC 26-37 + R PWM OUT S Q PWRPHS 1-4 36-40 2V CPHS 22 + Vref 0.8V CLOCK + - COMP DIS RAMP 17 OSC FAULT OSC LATCH VOCTH SET VCC + 0.4V FAULT 50mV-550mV VOCTH + 2V + 14,15,19,20,23 AGND 10mA CPHS 35 BG 5-12 PWRGND Figure 2. Detailed Block Diagram PIN FUNCTION DESCRIPTION Pin No 1-4 , 36-40 5-12 13 14,15,19,20,23 16 17 Symbol PWRPHS PWRGND VCC AGND FB COMP/DIS Description Power phase node. Drain of the low side power MOSFET and source of the high side MOSFET. Power ground. Source of the low side power MOSFET. Connected with large copper area. High current return for the low side MOSFET. Supply for the internal driver. Decouple with a 0.1 mF - 1 mF capacitor to AGND as close to the IC as possible. Internal driver ground. Reference ground for FB, COMP and other driver circuits. The input pin to the error amplifier.(inverted input error amplifier) Connect this pin to the output resistor divider (if used) or directly to the output voltage near the load connection. Compensation or disable pin. (output error amplifier) Use this pin to compensate the voltage control feedback loop. The compensation capacitor also acts as a soft-start capacitor. Pulling the pin below 400 mV will disable the controller. No connect. This pin can be connected to AGND or not connected. Output high side MOSFET driver. Connect to pin 25 with compensation circuit if used. The controller phase sensing. Supply rail for the floating top gate driver. Gate high side MOSFET Input supply pins for the high side MOSFET. (Drain) The current limit set pin. 18 21 22 24 25 26-34 35 NC TGOUT CPHS BST TGIN PWRVCC BG http://onsemi.com 2 NCP3101 ABSOLUTE MAXIMUM RATINGS Pin Name Control Circuitry Input Voltage Main Supply Voltage Input Bootstrap Supply Voltage Input Phase Node Phase Node (Bootstrap Supply Return) Current Limit Set Feedback COMP/DISABLE Symbol VCC PWRVCC BST PWRPHS CPHS BG FB COMP/DIS VMAX 15 V 30 V 30 V wrt/GND 15 V wrt/PHASE 25 V 25 V 15 V 5.5 V 5.5 V VMIN -0.3 V -0.3 V -0.3 V -0.7 V -5 V for < 50 nsec -0.7 V -5 V for < 50 nsec -0.3 V -2.0 V for < 200 nsec -0.3 V -0.3 V MAXIMUM RATINGS Pin Name Thermal Resistance Junction-to-Ambient Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range Thermal Characteristics 6X6 QFN Plastic Package Maximum Power Dissipation @ TA = 25C Lead Temperature Soldering (10 sec): Reflow (SMD Styles Only) Pb_Free (Note 1) Moisture Sensitivity Level MSL Symbol RqJA TJ TA Tstg PD Value 35 -40 to 150 -40 to 85 -55 to 150 3000 Unit C/W C C C mW 260 peak 3 C - Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: These devices have limited built-in ESD protection. The devices should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the device. 1. 60-180 seconds minimum above 237C http://onsemi.com 3 NCP3101 ELECTRICAL CHARACTERISTICS (0C < TJ < 70C for NCP3101, -40C < TJ < 125C for NCP3101B, 4.5 V < VCC < 13.2 V, BST = VCC * 2) Characteristic Input Voltage Range Boost Voltage Range Quiescent Supply Current Quiescent Supply Current VCC Supply Current VCC Supply Current Boost Quiescent Current UVLO Threshold UVLO Hysteresis VFB Feedback Voltage VFB Feedback Voltage Oscillator Frequency Oscillator Frequency Minimum Duty Cycle Maximum Duty Cycle Blanking Time Transconductance Open Loop DC Gain Output Source Current Output Sink Current Input Bias Current Unity Gain Bandwidth Soft-Start Source Current Transient Response* OVERCURRENT PROTECTION OC Threshold Fixed OC Threshold OCSET Current Source OC Switch-Over Threshold OUTPUT POWER MOSFETS RDS(on) Low-Side RDS(on) High-Side V = 13.2 V ID = 6 A V = 13.2 V ID = 6 A 18 18 mW mW Sourced from BG Pin before Soft-Start RBG = 5 kW 25 50 -375 10 700 75 mV mV mA mV VFB = 0.8 V Undershot VOUT Recovery Time Guaranteed by Design VFB = 100 mV VFB = 100 mV 55 80 80 70 TJ = 0C to 70C TJ = -40C to 125C TJ = 0C to 70C TJ = -40C to 125C 0.792 0.788 250 233 Conditions VFB = 1.0 V , No Switching, VCC = 13.2 V VFB = 1.0 V , No Switching, VCC = 5 V VFB = 1.0 V , Switching, VCC = 13.2 V VFB = 1.0 V , Switching, VCC = 5 V VFB = 1.0 V , No Switching, VBST = 25 V VCC Rising Edge 3.6 Min 4.5 4.5 2.3 1.8 10.3 5.6 600 4.0 0.4 0.8 0.8 275 275 4 75 50 4.0 70 120 120 0.1 4.0 10 112 118 1.0 80 0.808 0.812 300 317 Typ Max 13.2 30 Unit V V mA mA mA mA mA V V V V kHz kHz % % ns mS dB mA mA mA MHz mA mV ms *Transient response with 2.5 A/ms load step 50% - 100% defined at output parts: COUT= 2x100 uF MLCC + 0.82 mF OS-CON. http://onsemi.com 4 NCP3101 TYPICAL OPERATING CHARACTERISTICS 284 282 FSW, FREQUENCY (kHz) ICC, SUPPLY CURRENT SWITCHING (mA) 280 278 Vin = 13.2 V 276 274 272 270 -40 Vin = 4.5 V 11 10 9 8 7 6 5 4 3 -20 0 20 40 60 80 100 120 2 -40 -20 0 20 40 60 80 100 120 Vin = 4.5 V Vin = 13.2 V TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 3. Oscillator Frequency (FSW) vs. Temperature 800.6 Vref, REFERENCE VOLTAGE (mV) UVLO RISING/FALLING (V) 800.4 800.2 800 799.8 799.6 Vin = 4.5 V 799.4 799.2 -40 Vin = 13.2 V 4.1 4 3.9 3.8 3.7 Figure 4. ICC vs. Temperature RISING FALLING 3.6 3.5 -40 -20 0 20 40 60 80 100 120 -20 0 20 40 60 80 100 120 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 5. Reference Voltage (Vref) vs. Temperature Figure 6. UVLO vs. Temperature SOFT-START SOURCING CURRENT (mA) 15 14.5 HIGH-SIDE RDS(on) (mW) 14 13.5 13 12.5 12 11.5 11 10.5 10 -40 -20 0 20 40 60 80 100 120 40 35 VGS = 4.5 V 30 25 VGS = 12 V 20 15 -40 -20 0 20 40 60 80 100 120 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 7. Soft-Start Sourcing Current vs. Temperature Figure 8. High-Side RDS(on) vs. Temperature http://onsemi.com 5 NCP3101 DETAILED OPERATING DESCRIPTION General 11 10 OUTPUT VOLTAGE (V) 9 8 7 6 5 4 3 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 INPUT VOLTAGE (V) DMAX = 0.7 DMAX = 0.8 NCP3101 is a high efficiency integrated wide input voltage 6 A synchronous PWM buck converter designed to operate from a 4.5 V to 13.2 V supply. The output voltage of the converter can be precisely regulated down to 800 mV $1.0% when the VFB pin is tied to VOUT. The switching frequency is internally set to 275 kHz. A high gain Operational Transconductance Error Amplifier (OTA) is used for feedback and stabilizing the loop. Duty Cycle and Maximum Pulse Width Limits In steady state DC operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. The NCP3101 can achieve an 80% duty cycle. There is a built in off-time which ensures that the bootstrap supply is charged every cycle. The NCP3101, which is capable of a 100 nsec pulse width (minimum), can allow a 12 V to 0.8 V conversion at 275 kHz. The duty cycle limit and the corresponding output voltage are shown below in graphical format in Figure 9 and 11. The light gray area represents the safe operating area for the lowest maximum operational duty cycle and the dark grey area represents the absolute maximum duty cycle and corresponding output voltage. 0.8 0.7 Min-Maximum 0.6 DUTY CYCLE 0.5 0.4 0.3 0.2 0.1 0 0.8 2.8 4.8 6.8 OUTPUT VOLTAGE (V) 8.8 10.8 Minimum 13.2 V 4.5 V Max-Maximum Figure 10. Maximum Input to Output Voltage External Enable/Disable When the Comp Pin voltage falls or is pulled externally below the 400 mV threshold as shown in Figure 11, it disables the PWM Logic and the gate drive outputs. In this disabled mode, the operational transconductance amplifier's (EOTA) output source current is reduced and limited to the Soft-Start mode of 10 mA. FB 16 + VREF 0.8 V COMP/DIS 17 Figure 11. Disable Circuit Figure 9. Duty Cycle to Output Voltage Normal Shutdown Behavior Input Voltage Range (VCC and BST) The input voltage range for both VCC and BST is 4.5 V to 13.2 V with reference to GND and PHS, respectively. Although BST is rated at 13.2 V with reference to PHS, it can also tolerate 25 V with respect to GND. Normal shutdown occurs when the IC stops switching because the input supply reaches UVLO threshold. In this case, switching stops, the internal soft-start, SS, is discharged, and all GATE pins go low. The switch node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. http://onsemi.com 6 NCP3101 External Soft-Start The NCP3101 features an external soft-start function, which reduces inrush current and overshoot of the output voltage. Soft-Start is achieved by using the internal current source of 10 mA (typ) which charges the external integrator capacitor of the transconductance amplifier. Figure 12 is a typical soft-start sequence. This sequence begins once VCC surpasses its UVLO threshold. During soft-start, as the Comp Pin rises through 400 mV, the PWM Logic and gate drives are enabled. When the feedback voltage crosses 800 mV, the EOTA will be given control to switch to its higher regulation mode output current of 120 mA. In the event of an over current during the soft-start, the overcurrent logic will override the soft-start sequence and will shut down the PWM logic and both the high side and low side gates of the switching MOSFETS. 1.1 V 0.4 V Vcomp Enable 0.4 V condition has been removed. The minimum turn-on time of the LS-FET is set to 500 ns. The trip thresholds have a -95 mV, +45 mV process and temperature variation when set to -375 mV. The operation of key nodes is displayed in Figure 13 for both normal operation and during over current conditions. LS Gate Drive 2V BO Comparator 2V HS Gate Drive Switch Node Comparator 2V Switch Node SCP Trip Voltage C Phase SCP Comparated Latch Output Figure 13. Switching and Current Limit Timing Vfb SS 10 mA Isource/ Sink -10 mA Startup Normal 120 mA 10 mA Overcurrent Protection Setting Figure 12. Soft-Start Implementation UVLO Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VCC is too low to support the internal rails and power the converter. For the NCP3101, the UVLO is set to ensure that the IC will startup when VCC reaches 4.0 V and shutdown when VCC drops below 3.6 V. This permits smooth operation from a varying 5.0 V input source. Current Limit Protection NCP3101 allows the setting of Overcurrent Threshold ranging from 50 mV to 550 mV, simply by adding a resistor (ROCSET) between BG and GND. During a short period of time following VCC rising over UVLO threshold, an internal 10 mA current (IOCSET) is sourced from BG Pin, determining a voltage drop across ROCSET. This voltage drop will be sampled and internally held by the device as Overcurrent Threshold. The OC setting procedure overall time length is approximately 6 ms. When a ROCSET resistor is connected between BG and GND, the programmed threshold is set with an RSET values range from 5 kW to 45 kW. IOCth + IOCSET * ROCSET R DS(on) (eq. 1) In case of a short circuit or overload, the low side LS-FET will conduct large currents. The controller will shut down the regulator in this situation for protection against overcurrent. The low side RDS(on) sense is implemented by comparing the voltage at the phase node when BG starts going low to an internally generated fixed voltage. If the phase voltage is lower than OC trip voltage, an overcurrent condition occurs and a counter is initiated. When the counter completes, the PWM logic and both HS-FET and LS-FET are turned off. The converter will reinitialize through the soft-start cycle to determine if the short circuit or overload In case ROCSET is not connected, the device switches the OCP threshold to a fixed 375 mV value: an internal safety clamp on BG is triggered as soon as BG voltage reaches 700 mV, enabling the 375 mV fixed threshold and ending OC setting phase. Drivers The NCP3101 drives the internal High and Low side Switching MOSFETS with 1 A gate drivers. The gate drivers also include adaptive nonoverlap circuitry. The nonoverlap circuitry increase efficiency, which minimizes power dissipation, by minimizing the body diode conduction time. A detailed block diagram of the nonoverlap and gate drive circuitry used in the chip is shown in Figure 14. http://onsemi.com 7 NCP3101 BST UVLO FAULT TG + - PHASE 2V where Iinrush is the input current during startup, COUT is the total output capacitance, VOUT is the desired output voltage, and tSS is the soft-start interval. If the inrush current is higher than the steady state input current during maximum load, then the input fuse should be rated accordingly, if one is used. Calculating Soft-Start Time + - 2V VCC BG To calculate the soft-start time, the following equation can be used. t SS + C p ) C c * DV I SS (eq. 5) PWM OUT UVLO FAULT GND Figure 14. Block Diagram Where CC is the compensation as well as the soft-start capacitor. CP is the additional capacitor that forms the second pole. ISS is the soft-start current DV is the comp voltage from zero to until it reaches regulation. DV 1.1 V Careful selection and layout of external components is required, to realize the full benefit of the onboard drivers. The capacitors between VCC and GND and between BST and PHASE must be placed as close as possible to the IC. A ground plane should be placed on the closest layer for return currents to GND in order to reduce loop area and inductance in the gate drive circuit. APPLICATION SECTION Input Capacitor Selection Vcomp Vout Figure 15. Soft-Start The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of this ripple is: Iin RMS + I OUT D (1 * D ) (eq. 2) The above calculation includes the delay from comp rising to when output voltage becomes valid. To calculate the time of output voltage rising to when it reaches regulation; DV is the difference between the comp voltage reaching regulation and 1.1 V. Output Capacitor Selection Where D is the duty cycle, IinRMS is the input RMS current, and IOUT is the load current. The equation reaches its maximum value with D = 0.5. Losses in the input capacitors can be calculated with the following equation: P CIN + ESR CIN Iin RMS 2 (eq. 3) Where PCIN is the power loss in the input capacitors and ESRCIN is the effective series resistance of the input capacitance. Due to large di/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum capacitor must be used, it must be surge protected. Otherwise, capacitor failure could occur. Calculating Input Startup current To calculate the input startup current, the following equation can be used: I inrush + C OUT t SS V OUT (eq. 4) Selection of the right value of input and output capacitors determines the behavior of the buck converter. In most high power density applications the capacitor size is most important. Ceramic capacitor is necessary to reduce the high frequency ripple voltage at the input of converter. This capacitor should be located as near the IC as possible. Added electrolytic capacitor improved response of relative slow load change. The required output capacitor will be determined by planned transient deviation requirements. Usually a combination of two types of capacitors is recommended to meet the requirements. First, a ceramic output capacitor is needed for bypassing high frequency noise. Second, an electrolytic output capacitor is needed to achieve good transient response. In fact, during load transient, for the first few microseconds the bulk capacitance supplies current to the http://onsemi.com 8 NCP3101 load. The controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. During a load step transient the output voltage initially drops due to the current variation inside the capacitor and the ESR. (neglecting the effect of the effective series inductance (ESL)): DV OUT-ESR + DI out ESR COUT (eq. 6) A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to the output capacitor discharge is given by the following equation: DV OUT-DISCHARGE + DI OUT 2 C OUT 2 L OUT (eq. 7) V IN D * V OUT where VOUT-ESR is the voltage deviation of VOUT due to the effects of ESR and the ESRCOUT is the total effective series resistance of the output capacitors. Table 1 shows values of voltage drop and recovery time of the NCP3101 demo board with the configuration shown in Figure 19. The transient response was measured for the load current step from 3 A to 6 A (50% to 100% load). Input capacitors are 2x47 mF ceramic and 1x270 mF OS-CON, output capacitors are 2x100 mF ceramic and OS-CON as mentioned in Table 1. Typical transient response waveforms are shown in Figure 16. More information about OS-CON capacitors is available at http://www.edc.sanyo.com. Table 1. TRANSIENT RESPONSE VERSUS OUTPUT CAPACITANCE (50% to 100% Load Step) COUT (mF) OS-CON 0 100 150 220 270 560 820 1000 Drop (mV) 384 224 192 164 156 128 112 112 Recovery Time (ms) 336 298 278 238 212 198 118 116 where VOUT-DISCHARGE is the voltage deviation of VOUT due to the effects of discharge, LOUT is the output inductor value and VIN is the input voltage. Inductor Selection Both mechanical and electrical considerations influence the selection of an output inductor. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space-constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by: SlewRate LOUT + V IN * V OUT L OUT (eq. 8) This equation implies that larger inductor values limit the regulator's ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. This results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator's maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak-to-peak ripple current is given by the following equation: Ipk-pk LOUT + V OUT(1 * D) L OUT 275 kHz (eq. 9) where Ipk-pkLOUT is the peak to peak current of the output. From this equation it is clear that the ripple current increases as LOUT decreases, emphasizing the trade-off between dynamic response and ripple current. In order to achieve high efficiency, coils with a low value of Direct Current Resistance (DCR) have to be used. Feedback and Compensation Figure 16. Typical Waveform of Transient Response The output voltage is adjustable from 0.8 V to 5 V as shown in Table 1. The adjustment method requires an external resistor divider with its center tap tied to the FB pin. It is recommended to have a resistance between 1.5 kW and 5 kW. The selection of low value resistors reduces efficiency, alternatively high value resistance of R2 causes decrease in output voltage accuracy due to the bias current in the error amplifier. The output voltage error of this bias current can be estimated by using the following equation: http://onsemi.com 9 NCP3101 Error(%) + R2 * I bias V REF * 100 (eq. 10) Error = R2 * 1.25 * 10-5 (%) Once R2 is calculated above R3 can be calculated to select the desired output voltage as shown in the following equation: R3 + V REF V OUT * V REF * R2 (eq. 11) component variations when determining phase margin. Loop stability is defined by the compensation network around the OTA, the output capacitor, output inductor and the output divider. Figure 18 shows the open loop and closed loop gain plots. Open Loop, Unloaded Gain GAIN (dB) A Table 1 shows R3 values for frequently used output voltages. Vout VCC 13 POR UVLO FB 16 R3 VREF COMP DIS 17 0.8V Closed Loop, Unloaded Gain FZ Gain = GMR1 FP B Error Amplifier Compensation Network R2 + 100 1000 10 k 100 k FREQUENCY (Hz) 1000 k Figure 18. Gain Plot for the Error Amplifier Thermal Considerations CSOFT-START Rcomp + FAULT Ccomp Figure 17. FB circuit Table 1. OUTPUT VOLTAGES AND DIVIDER RESISTORS VOUT (V) 0.8 1.0 1.2 1.5 1.8 2.5 3.3 5.0 R2 (kW) 1.8 0.51 0.75 1.3 1.6 1.6 1.6 2.7 R3 (kW) E24 None 2.0 1.5 1.5 1.3 0.75 0.51 0.51 R3 (kW) Calculated None 2.040 1.500 1.486 1.280 0.753 0.512 0.514 The package thermal resistance can be obtained from the specifications section of this data sheet and a calculation can be made to determine the NCP3101 junction temperature. However, it should be noted that the physical layout of the board, the proximity of other heat sources such as MOSFETs and inductors, and the amount of metal connected to the NCP3101, impact the temperature of the device. The PCB is used also as the heatsink. Double or multi layer PCBs with thermal vias between places with the same electrical potential increase cooling area. A 70 mm thick copper plating is a good solution to eliminate the need for an external heatsink. Layout Considerations Figure 17 shows a typical Type II operational transconductance error amplifier (OTA). The compensation network consists of the internal error amplifier and the impedance networks ZIN (R1, R2) and external ZFB (Rcomp, Ccomp and Csoft-start). The compensation network has to provide a closed loop transfer function with the highest 0 dB crossing frequency to have fast response (but always lower than fSW/8) and the highest gain in DC conditions to minimize the load regulation. A stable control loop has a gain crossing with -20 dB/decade slope and a phase margin greater than 45. Include worst-case When designing a high frequency switching converter, layout is very important. Using a good layout can solve many problems associated with these types of power supplies as transient occur. External compensation components (R1, C9) are needed for converter stability. They should be placed close to the NCP3101. The feedback trace is recommended to be kept as far from the inductor and noisy power traces as possible. The resistor divider and feedback acceleration circuit (R2, R3, R6, C13) is recommended to be placed near to input FB (Pin 16, NCP3101). Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located together as close as possible using ground plane construction or single point grounding. The inductor and output capacitors should be located together as close as possible to the NCP3101. http://onsemi.com 10 Q1 RLO1 RLO7 1 2 3 Q2 RLO2 CLO1 1 RLO6 2 3 CLO2 RLO3 RLO4 CLO3 2xMBRS140T3 L1 PHASE D2 R6 D1 BAT54T1 R8 200 R2 1 30 PWRVCC 28 27 26 25 24 23 22 21 R7 OR RBOOST 3R3 C8 220n CBOOST 2n2 11 12 13 14 15 16 17 18 19 20 R3 510 OUT PWRVCC 29 22n 100m 100m 0.82m + OUT BG 2 PWRPHS 3 4 5 6 TGIN BST AGND CPHS NC TGOUT AGND COMP AGND AGND VCC 7 8 9 10 FB NCP3101 PWRPHS 1.6k C13 C3 C4 + C6 OCPSET 1 D3 RSN CSN 470 3 2 10R R8 20R 6.8 mH RLO8 3 X1 Q3 RLO5 1 2 3 2 1 + C5 47m 47m C1 C2 40 39 38 37 36 35 34 33 32 31 NCP3101 Figure 19. Schematic Diagram of NCP3101 Evaluation Board http://onsemi.com PWRGND PWRGND PWRGND C7 220n C10 120 C9 33n R1 732 270m 11 IN + R5 IN 2R2 NCP3101 Schematic diagram of the NCP3101 demoboard is shown in Figure 19 and the actual PCB layout is shown in Figure 20. The corresponding bill of material is summarized in Table 2. Parameters of the board were tested with Input voltage Vin = 4.5 V to 13.2 V and with various output loads between 0 A and 6 A. The board includes a few components used for transient measurements. The load current range can be selected by switches 1 to 3 to give a range of 0 A - 6 A with 2 A steps. A square wave signal with a 10% duty cycle and a 10 V amplitude has to be connected to the X1 connector to enable the load testing. http://onsemi.com 12 NCP3101 Table 2. BILL OF MATERIAL Position R1 R2 R3 R4 R5 R6 R7 R8* RSN RBOOST RLO1* RLO2* RLO3* RLO4* RLO5* RLO6* RLO7* RLO8* C1-C2 C3-C4 C5 C6 C7 C8 C9 C10 C13 CSN CS CBOOST CLO1-3* D1 D2-3 L1 Q1-3* IC1 Value 732 W 1.6 kW 510 W 200 W 2.2 W OCP set. 0W 20 W 10 W 3.3 W 2.2 W 2.2 W 2.2 W 2.2 W 1 kW 1 kW 1 kW 75 W 47 mF 100 mF 0.27 mF 0.82 mF 220 nF 220 nF 33 nF 120 pF 22 nF 470 pF 470 pF 2.2 nF 4.7 nF BAT51T1 MBRS140T3 6.8 mH NTD4810 NCP3101 Description Resist. SMD Resist. SMD Resist. SMD Resist. SMD Resist. SMD Resist. SMD Resist. SMD Resist. SMD Resist. SMD Resist. SMD Resistor 1W Resistor 1W Resistor 1W Resistor 1W Resist. SMD Resist. SMD Resist. SMD Resist. SMD Capac. Ceram Capac. Ceram Cap.OS-CON Cap.OS-CON Capac. Ceram Capac. Ceram Capac. Ceram Capac. Ceram Capac. Ceram Capac. Ceram Capac. Ceram Capac. Ceram Capac. Ceram Diode Diode Coil MOSFET I.C. TL2BR010FTE 232272462208 232271161109 232273463308 MCF 1W 2R2 MCF 1W 2R2 MCF 1W 2R2 MCF 1W 2R2 232272461002 232272461002 232272461002 RMC1/8W 1206 1% 75R C1210C476M9PAC7800 CS1210C107M9PAC7800 16SP270M 4SP820M 12065G224ZAT2A 12065G224ZAT2A B37872K5333K-MR 2250 001 11537 2238 581 15641 12067A471JAT1A 12067A471JAT1A 12067C222KAT2A 12065C472KAT2A BAT51T1G MBRS140T3G 74457068 NTD4810NH NCP3101MNTXG Part No: RMC1/8W 1206 1% 732R RMC1/8W 1206 1% 1K6 RMC1/8W 1206 1% 510R WCR 1206 200R 2%. 232272462208 Footprint 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 Special Special Special Special 1206 1206 1206 1206 1210 1210 Special Special 1206 1206 1206 1206 1206 1206 1206 1206 1206 SOD123 SMB WE-PD4 DPAK QFN40 Quantity 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 3 1 2 1 3 1 TYCO ELECT. PHYCOMP PHYCOMP PHYCOMP MULTICOMP MULTICOMP MULTICOMP MULTICOMP PHYCOMP PHYCOMP PHYCOMP MULTICOMP KEMET KEMET SANYO SANYO AVX AVX TYCO ELECT. PHYCOMP PHYCOMP AVX AVX AVX AVX ON Semiconductor ON Semiconductor Wurth Electronik ON Semiconductor ON Semiconductor Manufacturer MULTICOMP MULTICOMP MULTICOMP WELWYN PHYCOMP *Parts marked with "*" and highlighted in grey are only necessary for transient response and PHASE-GAIN feedback measuring. http://onsemi.com 13 NCP3101 Figure 20. PCB Layout Evaluation Board (55mm x 90mm) http://onsemi.com 14 NCP3101 Measured Performance of NCP3101 Demoboard is Shown in Figures 21 Through 24. 10.5 9.5 90 EFFICIENCY (%) 8.5 7.5 Iocp (A) 6.5 5.5 4.5 3.5 2.5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Rocp RESISTANCE (kW) 50 0 1 TJ = 25C 60 TJ = 70C TJ = 0C 5V 80 6V 7V 8V 9V 10 V 11 V 12 V 13.2 V 2 3 4 OUTPUT CURRENT (A) 5 6 100 4.5 V 70 Figure 21. Overcurrent Protection Figure 22. Efficiency (Vout = 3.3 V) 50 40 30 GAIN (dB) 20 10 0 -10 -20 -30 -40 100 1000 10000 FREQUENCY (Hz) Phase Gain -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 100000 PHASE (deg) Figure 23. Transient Response (Vin = 13.2 V, Vout = 3.3 V, Iout = 3 A to 6 A Step) Output Capacitors: 2x MLCC 100 mF and 820 mF OS-CON Figure 24. Feedback Frequency Response (Vin = 13.2 V, Vout = 3.3 V) http://onsemi.com 15 NCP3101 Figure 25. Temperature Conditions (Vin = 13.2 V, Vout = 3.3 V, Iout = 6 A) Steady State, No Additional Cooling, Ambient Temperature 255C ORDERING INFORMATION Device NCP3101MNTXG NCP3101BMNTXG Package QFN40 (Pb-Free) QFN40 (Pb-Free) Temperature Grade For 0C to +70C For -40C to +85C Shipping 2500 / Tape & Reel 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 16 NCP3101 PACKAGE DIMENSIONS QFN40 6x6, 0.5P CASE 485AK-01 ISSUE A D AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 --0.05 0.20 REF 0.18 0.30 6.00 BSC 2.45 2.65 3.10 3.30 1.70 1.90 0.85 1.05 6.00 BSC 1.80 2.00 1.43 1.63 2.15 2.35 0.50 BSC 2.10 2.30 2.30 2.50 0.20 --0.30 0.50 2X 0.15 C 2X 0.15 C 0.10 C 0.08 C NOTE 4 40X L 11 10 E4 E2 E3 EEE EEE EEE TOP VIEW (A3) SIDE VIEW A1 D3 G2 21 1 40 31 30 PIN ONE LOCATION E A C SEATING PLANE DIM A A1 A3 b D D2 D3 D4 D5 E E2 E3 E4 e G2 G3 K L G3 D5 G2 10 11 21 G3 1 30 40 31 G2 K e e/2 BOTTOM VIEW 40X b 0.10 C A B 0.05 C NOTE 3 D2 AUXILIARY BOTTOM VIEW D4 G3 SOLDERING FOOTPRINT 6.30 0.72 2.62 1.86 0.72 0.72 1.96 0.50 PITCH 40X 0.92 1 1.58 6.30 2.31 0.30 0.92 1.01 3.26 40X 0.58 0.92 DIMENSIONS: MILLIMETERS http://onsemi.com 17 NCP3101 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 18 NCP3101/D |
Price & Availability of NCP3101
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |