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FEBRUARY 2001
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
FEATURES * 10-Bit Resolution * 8-Channel Mux * Sampling Rate - < 1kHz - 2MHz * Low Power CMOS - 24 mW (typ) * Power Down; Lower Consumption - 0.1 mW (typ) * Input Range between GND and VDD * No S/H Required for Analog Signals less than 100kHz * No S/H Required for CCD Signals less than 2MHz * Single Power Supply (2.7 to 3.6V) * Latch-Up Free * ESD Protection: 2000 Volts Minimum
APPLICATIONS * P/DSP Interface and Control Application * High Resolution Imaging - Scanners & Copiers * Wireless Digital Communications * Multiplexed Data Acquisition BENEFITS * Reduced Board Space (Small Package) * Reduced External Parts, No Sample/Hold Needed * Suitable for Battery & Power Critical Applications * Designer can Adapt Input Range & Scaling
GENERAL DESCRIPTION
The XRD87L99 is a flexible, easy to use, precision 10-bit analog-to-digital converter with 8-channel mux that operates over a wide range of input and sampling conditions. The XRD87L99 can operate with pulsed "on demand" conversion operation or continuous "pipeline" operation for sampling rates up to 2MHz. The elimination of the S/H requirements, very low power, and small package size offer the designer a low cost solution. No sample and hold is required for CCD applications up to 2MHz, or multiplexed input applications when the signal source bandwidth is limited to 100kHz. The input architecture of the XRD87L99 allows direct interface to any analog input range between AGND and AVDD. The user simply sets VREF(+) and VREF(-) to encompass the desired input range. Scaled reference resistor taps @ 1/4 R, 1/2 R and 3/4 R allow for customizing the transfer curve as well as providing a 1/2 span reference voltage. Digital outputs are CMOS and TTL compatible. The XRD87L99 uses a two-step flash technique. The first segment converts the 5 MSBs and consists of autobalanced comparators, latches, an encoder, and buffer storage registers. The second segment converts the remaining 5 LSBs. When the power down input is "high", the data outputs DB9 to DB0 hold the current values and VREF(-) is disconnected from VREF1(-). The power consumption during the power down mode is 0.1mW.
ORDERING INFORMATION
PART NUMBER XRD87L99AIQ PACKAGE PQFP OPERATING TEMPERATURE RANGE -40C to +85C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRD87L99
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LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM AND TIMING
AVDD
AVDD
DVDD
Coarse Comparators
B
5
Adder
6 OFW CLK
S
B
N N-1 N-1 N N
VREF(+) R3 R2 R1 VREF(-) Ladder PD VREF1(-)
Fine Resolution Comparators
DFF 5
DB9-DB0 10 OE
DB9-DB0 OFW
CLK AIN1
S
CLR 1 or 8 MUX AIN8 8 3 to 8 Decoder WR Latch A2 A1 A0
AGND
DGND
FIGURE 2. PIN OUT OF THE XRD87L99
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
34
33
23
22
Index 44 12
1
11
44-Pin PQFP (10mm x 10mm)
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PIN DESCRIPTIONS
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NAME DB6 DB7 DGND DGND DVDD CLR WR A2 A1 A0 CLK OE N/C DB8 DB9 OFW VREF(+) VREF(-) VREF1(-) R1 R2 AIN8 DESCRIPTION Data Output Bit 6 Data Output Bit 7 Digital Ground Digital Ground Digital VDD Clear (Active Low) Write (Active Low) Address 2 Address 1 Address 0 32 Clock Input Output Enable (Active Low) No Connect Data Output Bit 8 Data Output Bit 9 (MSB) Overflow Output Upper Reference Voltage Lower Reference Voltage Lower Reference Voltage 41 Reference Ladder Tap Reference Ladder Tap Analog Signal Input 8 42 43 44 DB4 DB5 N/C N/C Data Output Bit 4 Data Output Bit 5 No Connect No Connect 33 34 35 36 37 38 39 40 AIN6 AGND PD AIN7 DB0 DB1 DB2 DB3 PIN # 23 24 25 26 27 28 29 30 31 NAME R3 N/C AIN1 AIN2 AIN3 AIN4 AIN5 AGND AVDD AVDD DESCRIPTION
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
Reference Ladder Tap No Connect Analog Signal Input 1 Analog Signal Input 2 Analog Signal Input 3 Analog Signal Input 4 Analog Signal Input 5 Analog Ground Analog VDD Analog VDD Analog Signal Input 6 Analog Ground Power Down Analog Signal Input 7 Data Output Bit 0 (LSB) Data Output Bit 1 Data Output Bit 2 Data Output Bit 3
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XRD87L99
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LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
TABLE 1: TRUTH TABLE FOR INPUT CHANNEL SELECTION
CLR L H H H H H H H H H WR X L L L L L L L L H A2 X L L L L H H H H X A1 X L L H H L L H H X A0 X L H L H L H L H X Selected Analog Input AIN1 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 Previous Selection
NOTE: CLR, WR, A2, A1, A0 are internally connected to ground through 500k resistance.
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LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS AVDD = DVDD = 3 V, FS = 2 MHZ (50% DUTY CYCLE), VREF(+) = 2.6, VREF(-) = AGND, TA = 25C, UNLESS OTHERWISE SPECIFIED
PARAMETER KEY FEATURES Resolution Sampling Rate ACCURACY (A GRADE)2 Differential Non-Linearity Integral Non-Linearity Zero Scale Error Full Scale Error REFERENCE VOLTAGES Positive Ref. Voltage5 Negative Ref. Voltage5 Differential Ref. Voltage5 Ladder Resistance ANALOG INPUT1 Input Bandwidth (-1dB) Input Bandwidth (-1dB) Input Voltage Range7 Input Capacitance3 Aperture Delay1 DIGITAL INPUTS Logical "1" Voltage Logical "0" Voltage Leakage Currents CLK CLR, WR, A2, A1, A0, PD, OE VIH VIL IIN -1 -5 1 30 A A These input pins have 500k internal resistors to GND 2.0 0.8 V V VIN = DGND to DVDD VIN CIN tAP 1.0 0.125 VREF(-) 20 8 4.0 0.5 VREF(+) MHz MHz V pF ns 1-Channel 8-Channel VREF(+) VREF(-) VREF RL 1.0 AGND 1.0 500 3.0 1.0 2.0 1200 AVDD AVDD -1 AVDD 2000 V V V W DNL INL EZS EFS 0 0 -1 +0.3 1 50 30 1 2 100 60 LSB LSB mV mV Best Fit Line (Max INL - Min INL)/2 FS .001 10 2.0 Bits MHz For Rated Performance SYMBOL MIN TYP MAX UNITS TEST CONDITIONS/COMMENTS
Input Capacitance
5
pF
5
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XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
ELECTRICAL CHARACTERISTICS AVDD = DVDD = 3 V, FS = 2 MHZ (50% DUTY CYCLE), VREF(+) = 2.6, VREF(-) = AGND, TA = 25C, UNLESS OTHERWISE SPECIFIED
PARAMETER Clock Timing Clock Period Rise & Fall Time4 "High" Time "Low" Time DIGITAL OUTPUTS Logical "1" Voltage Logical "0" Voltage Tristate Leakage Data Hold Time1 Data Valid Delay1 Write Pulse Width1 Multiplexer Address Setup Time1 Multiplexer Address Hold Time1 Delay from WR to Multiplexer1 Enable Clock to PD Setup Time Clock to UR Setup Time Clock to PD Hold Time tMUXEN1 tCLKS1 tCLKS2 tCLKH1 0 600 80 400 ns ns ns ns VOH VOL IOZ tHLD tDL tWR tAS tAH 40 80 -1 12 30 35 DVDD-0.5 0.5 1 V V A ns ns ns ns TS tR, tF tB tS 125 125 250 250 500 1,000,000 10 500,000 500,000 ns ns ns ns COUT=15 PF ILOAD = 2 mA ILOAD = 2 mA VOUT = 0 to DVDD SYMBOL MIN TYP MAX UNITS TEST CONDITIONS/COMMENTS
0
ns
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XRD87L99
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LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
ELECTRICAL CHARACTERISTICS AVDD = DVDD = 3 V, FS = 2 MHZ (50% DUTY CYCLE), VREF(+) = 2.6, VREF(-) = AGND, TA = 25C, UNLESS OTHERWISE SPECIFIED
PARAMETER Clock to WR Hold Time Power Down Time1 Power Up Time1 Data Enable Delay Data High Z Delay Pipeline Delay (Latency) POWER SUPPLIES 8 Power Down (IDD) Operating Voltage (AVDD, DVDD) Current (AVDD + DVDD) IPD-DD VDD IDD 2.7 0.01 3.0 7 0.10 3.6 10 mA V mA PD=Low (Normal Mode) VDD =3 V PD=High, CLK High or Low SYMBOL tCLKH2 tPD tPU tDEN tDHZ 14 4 1.5 MIN 0 300 200 16 6 TYP MAX UNITS ns ns ns ns ns cycles TEST CONDITIONS/COMMENTS
NOTES: 1 Guaranteed. Not tested. 2 Tester measures code transition voltages by dithering the voltage of the analog input (VIN). The difference between the measured code width and the ideal value (VREF/1024) is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage. 3 See VIN input equivalent circuit. 4 Clock specification to meet aperture specification (tAP). Actual rise/fall time can be less stringent with no loss of accuracy. 5 Specified values guarantee functional device. Refer to other parameters for accuracy. 6 System can clock the XRD87L99 with any duty cycle as long as all timing conditions are met. 7 Input range where input is converted correctly into binary code. Input voltage outside specified range converts to zero or full scale output. 8 DVDD and AVDD are connected through the silicon substrate. Connect together at the package.
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE
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XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
ABSOLUTE MAXIMUM RATINGS: (TA = +25C UNLESS OTHERWISE NOTED)1, 2, 3
VDD (to GND) VREF(+), VREF(-), VREF(-) All AINs All Inputs All Outputs Storage Temperature Lead Temperature (Soldering 10 seconds) Package Power Dissipation Rating to 75C PQFP Derates above 75C 450mW 14mW/C +7 V GND -0.5 to VDD +0.5 V GND -0.5 to VDD +0.5 V GND -0.5 to VDD +0.5 V GND -0.5 to VDD +0.5 V -65 to +150C +300C
NOTE: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s. 3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND.
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XRD87L99
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disconnects the latches from the comparators. This delay is called aperture delay (tAP). The coarse comparators make the first pass conversion and selects a ladder range for the fine comparators. The fine comparators are connected to the selected range during the next B phase.
tF VIH VIL
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
FIGURE 3. XRD87L99 TIMING DIAGRAM
tAP
tS
tR
tB
FIGURE 4. XRD87L99 COMPARATORS
CLOCK Sample N-1 Auto Balance Sample N Auto Balance TS Analog Input VOH Data VOL tDL tHLD N-1
Sample N+1
S
VIN
B
S
Latch
VTAP Ref Ladder
B S
COARSE COMPARATOR
S
B
Latch
VIN VTAP
THEORY OF OPERATION
1.0 ANALOG-TO-DIGITAL CONVERSION The XRD87L99 converts analog voltages into 1024 digital codes by encoding the outputs of coarse and fine comparators. Digital logic is used to generate the overflow bit. The conversion is synchronous with the clock and it is accomplished in 2 clock periods. The reference resistance ladder is a series of resistors. The fine comparators use a patented interpolation circuit to generate the equivalent of 1024 evenly spaced reference voltages between VREF(-) and VREF(+). The clock signal generates the two internal phases, B (CLK high) and S (CLK low = sample) (See Figure 1). The rising edge of the CLK input marks the end of the sampling phase (S). Internal delay of the clock circuitry will delay the actual instant when S
Selected Range
B
FINE COMPARATOR
AIN Sampling, Ladder Sampling, and Conversion Timing Figure 3 shows this relationship as a timing chart. AIN sampling, ladder sampling and output data relationships are shown for the general case where the levels which drive the ladder need to change for each sampled AIN time point. The ladder is referenced for both last AIN sample and next AIN sample at the same time. If the ladder's levels change by more than 1 LSB, one of the samples must be discarded. Also note that the clock low period for the discarded AIN can be reduced to the minimum tS time.
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FIGURE 5. XRD87L99 COMPARATORS WITH CHANGING REFERENCE VOLTAGE
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
Short Cycle Sample will be discarded tS
Hold Reference Value Past Clock Change for tAP Time
External Update References Clock Internal AIN Sample Window Ladder Sample Window (MSB Bank) Ladder Compare (LSB Bank) External DATA
AINX0
Settle by Clock Update Time Reference Stable Time - For Sample A IN2 Reference Stable Time - For Sample A IN1
Sample AIN1
AINX1
Sample AIN2
B
S
Sample A IN1
B
Not Used
S
AINX1
B
S
Sample A IN2
Sample Ladder for AIN1
Sample Ladder for AINX1
Sample Ladder for AIN2
Sample Ladder for AINX2
Compare Ladder V/S A INX0
Compare Ladder V/S A IN1
Compare Ladder V/S A INX1
Compare Ladder V/S A IN2
DATA A IN0
DATA A INX0 Not Used
DATA A IN1
DATA A INX1 Not Used
1.1 ACCURACY OF CONVERSION: DNL AND INL The transfer function for an ideal A/D converter is shown in Figure 6. FIGURE 6. IDEAL A/D TRANSFER FUNCTION
The overflow transition (VOFW) takes place at: VIN = VOFW = VREF(+) The first and the last transitions for the data bits take place at: VIN = V001 = VREF(-) + 1.0 * LSB VIN = V3FF = VREF(-) - 1.0 * LSB VREF = VREF(+) - VREF(-)
DIGITAL CODES
LSB = VREF / 1024 = (V3FF - V001) / 1022
NOTE: The overflow transition is a flag and has no impact on the data bits.
OFW=0 1 LSB 3FE 002 001 3FD 3FF OFW=1
In a "real" converter the code-to-code transitions don't fall exactly every VREF/1024 volts. A positive DNL (Differential Non-Linearity) error means that the real width of a particular code is larger than 1 LSB. This error is measured in fractions of LSBs. A Max DNL specification guarantees that ALL code widths (DNL errors) are within the stated value. A specification of Max DNL = + 0.5 LSB means that all code widths are within 0.5 and 1.5 LSB. If VREF = 2.56 V then 1 LSB = 2.5 mV and every code width is within 1.25 and 3.75 mV.
000
LSB V
VREF(-)
V001
V002
V3FE
V3FF
V0FW = VREF(+)
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XRD87L99
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Figure 8 shows the zero scale and full scale error terms. Figure 9 gives a visual definition of the INL error. The chart shows a 3-bit converter transfer curve with greatly exaggerated DNL errors to show the deviation of the real transfer curve from the ideal one. After a tester has measured all the transition voltages, the computer draws a line parallel to the ideal transfer line. By definition the best fit line makes equal the positive and the negative INL errors. For example, an INL error of -1 to +2 LSB's relative to the Ideal Line would be +1.5 LSB's relative to the best fit line. FIGURE 9. INL ERROR CALCULATION
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
FIGURE 7. DNL MEASUREMENT ON PRODUCTION TESTER
DNL Analog Input
LSB V(N+1)
V(N)
N+1 Output Codes (N) Code Width = V(N+1) - V(N) LSB = [ VREF(+) - VREF(-) ] / 1024 DNL(N) = [ V(N+1) - V(N) ] - LSB N N-1
The formulas for Differential Non-Linearity (DNL), Integral Non-Linearity (INL) and zero and full scale errors (EZS, EFS) are: DNL (001) = V002 - V001 - LSB ::: DNL (3FE) = V3FF - V3FE - LSB EFS (full scale error) = V3FF - [VREF(+) -1.5 * LSB] EZS (zero scale error) = V001 - [VREF(-) + 0.5 * LSB] FIGURE 8. REAL A/D TRANSFER CURVE
Output Codes 7 Real Transfer Line 6 5 INL 4 3 2 1 LSB
Best Fit Line
EFS
Ideal Transfer Line
DIGITAL CODES 0.5 LSB 1.5 LSB
EZS
Analog Input (Volt)
EZS 3FE 002 001 000
EFS 3FF
V VREF(-) V001 V002 V3FE V3FF VREF(+)
1.2 CLOCK AND CONVERSION TIMING A system will clock the XRD87L99 continuously or it will give clock pulses intermittently when a conversion is desired. The timing of Figure 10a shows normal operation, while the timing of Figure 10b keeps the XRD87L99 in balance and ready to sample the analog input.
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FIGURE 10. RELATIONSHIP OF DATA TO CLOCK
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
CLOCK
N
N+1
DATA
N a. Continuous sampling
N+1
1.3 ANALOG INPUT The XRD87L99 has very flexible input range characteristics. The user may set VREF(+) and VREF(-) to two fixed voltages and then vary the input DC and AC levels to match the VREF range. Another method is to first design the analog input circuitry and then adjust the reference voltages for the analog input range. One advantage is that this approach may eliminate the need for external gain and offset adjust circuitry which may be required by fixed input range A/Ds. The XRD87L99's performance is optimized by using analog input circuitry that is capable of driving the AIN input. Figure 11 shows the equivalent circuit for AIN.
CLOCK
N
BALANCE
DATA b. Single sampling
N
FIGURE 11. ANALOG INPUT EQUIVALENT CIRCUIT
80 AVDD R Series 200 AIN 10 pF 4 1 pF 8 50 Control Channel Selection 10 pF R MUX 200
10 pF
S
160
S
B
+ 1 pF
1/2 [ V REF(+) + VREF(-) ]
1.4 ANALOG INPUT MULTIPLEXER The XRD87L99 includes a 8-Channel analog input multiplexer. The relationship between the clock, the multiplexer address, the WR and the output data is shown in Figure 12. FIGURE 12. MUX ADDRESS TIMING
FIGURE 13. ANALOG MUX TIMING
tAS A2, A1, A0 WR tWR tMUXEN1
tAH
Clock
Sample N Old Address Sample M New Address Sample M+1
MUXEN (Internal Signal)
tCLKS2 WR tAS
tWR
tCLKH2
tAH
1.5 REFERENCE VOLTAGES The input/output relationship is a function of VREF: AIN = VIN - VREF(-) VREF = VREF(+) - VREF(-)
Address
DB0-DB9
N-2 Valid
N-1 Valid Old Address
N Valid Old Address
M Valid New Address
DATA = 1024 * (AIN/VREF) A system can increase total gain by reducing VREF.
Note: tCLKS2 = tCLKH2 = 0
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XRD87L99
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FIGURE 14. XRD87L99 FUNCTIONAL EQUIVALENT CIRCUIT AND INTERFACE TIMING
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
1.6 DIGITAL INTERFACES The logic encodes the outputs of the comparators into a binary code and latches the data in a D-type flipflop for output. The functional equivalent of the XRD87L99 (Figure 14) is composed of:
S
VIN
A/D
D
Q
D
Q
DB9-DB0
1. Delay stage (tAP) from the clock to the sampling phase (fS). 2. An ideal analog switch which samples VIN. 3. An ideal A/D which tracks and converts VIN with no delay. 4. A series of two DFF's with specified hold (tHLD) and delay (tDL) times. tAP, tHLD and tDL are specified in the Electrical Characteristics table. 1.7 POWER DOWN Figure 15 shows the relationship between the clock, sampled VIN to output data relationship and the effect of power down.
XRD8799
tAP
CLK
CLK
N
N+1
VIN tDL DB9-DB0
tHLD
N-1
N
FIGURE 15. POWER DOWN TIMING DIAGRAM
CLK
SAMPLE N SAMPLE M SAMPLE M+1
VIN DB0-DB9
N-2 Valid
N-1 Valid tCLKS1
N Valid tCLKH1
M Valid
PD IDD, IVREF(+)
tPD
tPU
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2.0 APPLICATION NOTES FIGURE 16. TYPICAL CIRCUIT CONNECTIONS
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
C1 = 4.7 or 10F Tantalum C2 = 0.1F Chip Cap or low inductance cap RT = Clock Transmission Line Termination
+5 V
1 of 8
C1A, C2A AVDD Z < 100 AIN1 (Substrate) Buffer Resistive Isolation of 50 to 100 AIN8
C1D, C2D DVDD OFW
AIN
DB9 - DB0
XRD87L99
WR CLK
OE
+ Reference Voltage Source C1 C2 C1 C2
C1 C2
VREF(+) 3/4 R 1/4 R VREF(-) VREF1(-) AGND
CLK RT
A2 A1 DGND A0
The following information will be useful in maximizing the performance of the XRD87L99. 1. All signals should not exceed AVDD +0.5 V or AGND -0.5 V or DVDD +0.5 V or DGND -0.5 V. 2. Any input pin which can see a value outside the absolute maximum ratings (AVDD or DVDD+0.5 V or AGND -0.5 V) should be protected by diode clamps (HP5082-2835) from input pin to the supplies. All XRD87L99 inputs have input protection diodes which will protect the device from short transients outside the supply ranges. 3. The design of a PC board will affect the accuracy of XRD87L99. Use of wire wrap is not recommended. 4. The analog input signal (VIN) is quite sensitive and should be properly routed and terminated. It should be shielded from the clock and digital outputs so as to minimize cross coupling and noise pickup. 5. The analog input should be driven by a low impedance (less than 50). 6. Analog and digital ground planes should be substantial and common at one point only. The
ground plane should act as a shield for parasitics and not a return path for signals. To reduce noise levels, use separate low impedance ground paths. DGND should not be shared with other digital circuitry. If separate low impedance paths cannot be provided, DGND should be connected to AGND next to the XRD87L99. 7. DVDD should not be shared with other digital circuitry to avoid conversion errors caused by digital supply transients. DVDD for the XRD87L99 should be connected to AVDD next to the XRD87L99. 8. DVDD and AVDD are connected inside the XRD87L99. DGND and AGND are connected internally. 9. Each power supply and reference voltage pin should be decoupled with a ceramic (0.1F) and a tantalum (10F) capacitor as close to the device as possible. 10. The digital output should not drive long wires. The capacitive coupling and reflection will contribute noise to the conversion. When driving distant loads, buffers should be used. 100 resistors in series with the digital outputs in some applications reduces the digital output disruption of AIN.
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LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
FIGURE 17. EXAMPLE OF A REFERENCE VOLTAGE SOURCE
+3V
5k
0.1F
100k
MP5010
+ -
+
-
FIGURE 18.
3V ANALOG INPUT
+3V
+3V
1 of 8
+3V + VIN -
R
R VREF(+) AVDD
AIN1 AIN8
DB0
VREF(-)
AGND
For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent.
NOTE: High R values affect the input BW of ADC due to the (R * CIN of ADC) time constant. Therefore, for different applications the R value needs to be selected as a trade-off between AIN settling time and power dissipation.
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FIGURE 19.
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
6V ANALOG INPUT
+3V
+3V
1 of 8
+6V + VIN -
2R
R VREF(+) AVDD
AIN1 2R AIN8
DB0
VREF(-)
AGND
For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent.
NOTE: High R values affect the input BW of ADC due to the (R * CIN of ADC) time constant. Therefore, for different applications the R value needs to be selected as a trade-off between AIN settling time and power dissipation.
FIGURE 20. A/D LADDER AND AIN WITH PROGRAMMED CONTROL (OF VREF(+), VREF(-), 1/4 AND 3/4 TAP.)
MP7641 VIN AIN1
XRD87L99
-
+
DAC0
-
VIN
+
DAC7
AIN8
MP7226
DAC4
VREF(+) 3/4 1/4 VREF(+)
DAC3
DAC2
DAC1
VREF1(-)
@ Power Down write values to DAC 3, 2, 1 = DAC 4 to minimize power consumption. Only AIN and Ladder detail shown.
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LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
FIGURE 21. DNL VS. SAMPLING FREQUENCY
2.0
V DD = 3V V REF (+) = 2.6V V REF (-) = 0V
1.5
1.0 POS. DNL
0.5 DNL (LSB)
0.0
-0.5
NEG. DNL
-1.0
-1.5
-2.0 0.1 1.0 FS (MHz) 10.0
FIGURE 22. INL VS. SAMPLING FREQUENCY
4
VD D = 3V VR E F ( +) = 2.6V VR E F ( - ) = 0V
2 INL (LSB)
POS. INL
0 NEG. INL -2
-4 0.1 1.0 FS (MHz) 10.0
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FIGURE 23. SUPPLY CURRENT VS. SAMPLING FREQUENCY
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
8.0
VD D = 3V VR E F ( +) = 2.6V VR E F ( - ) = 0V
7.5
7.0 IDD (mA)
6.5
6.0
5.5
5.0 0.0 1.0 2.0 3.0 FS (MHz) 4.0 5.0 6.0
FIGURE 24. BEST FIT INL VS. REFERENCE VOLTAGE
2.5
VD D = 2.7V F S = 2MHz
2.0
INL (LSB)
1.5
1.0
0.5
0.0 0.0 0.5 1.0 1.5 V REF (V) 2.0 2.5 3.0
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LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
FIGURE 25. DNL VS. REFERENCE VOLTAGE
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0
VD D = 2.7V F S = 2MHz
POS. DNL
NEG. DNL
0.0
0.5
1.0
1.5 V REF (V)
2.0
2.5
3.0
FIGURE 26. SUPPLY CURRENT VS. TEMPERATURE
10
V DD = 3V V REF(+) = 2.6V V REF(-) = 0V FS = 2MHz
8
6 IDD (mA) 4 2 0 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
19
xr
FIGURE 27. DNL VS. TEMPERATURE
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
1 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -60 -40 -20 0 20 Temperature (C) 40 60 80 100 NEG. DNL V DD = 3V V REF(+) = 2.6V V REF(-) = 0V FS = 2MHz
POS. DNL
FIGURE 28. REFERENCE RESISTANCE VS.TEMPERATURE
2.00
V DD = 3V V REF(+) = 2.6V V REF(-) = 0V FS = 2MHz
1.75
1.50 Ref. Resistance (Kohm)
1.25
1.00
0.75
0.50
0.25
0.00 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
20
XRD87L99
xr
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
FIGURE 29. IDD VS. VDD
14.0 12.0 10.0 I DD (mA) 8.0 6.0 4.0 2.0 0.0 2.0
V REF(+) = 2.6V V REF(-) = 0V FS = 2MHz
2.5
3.0 VDD (V)
3.5
4.0
FIGURE 30. INL @ 2MSPS
2.0
V DD = 2.7V V REF(+) = 2.3V V REF(-) = 0V
1.0
LSB
0.0
-1.0
-2.0 0 128 256 384 512 Code 640 768 896 1024
21
xr
44 LEAD PLASTIC QUAD FLAT PACK
(10 mm x 10 mm QFP, 1.60 mm Form)
REV. 2.00
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
D D1 33 23
34
22
D1
D
44
12
1 B e A2
11
A Seating Plane A1 L
C
Note: The control dimension is the millimeter column
INCHES SYMBOL A A1 A2 B C D D1 e L MIN 0.072 0.001 0.071 0.011 0.004 0.510 0.390 MAX 0.093 0.010 0.087 0.018 0.009 0.530 0.398 MILLIMETERS MIN 1.82 0.02 1.80 0.29 0.11 12.95 9.90 MAX 2.45 0.25 2.20 0.45 0.23 13.45 10.10 0.80 BSC 0.73 0 1.03 7
0.0315 BSC 0.029 0 0.040 7
22
XRD87L99
xr
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2001 EXAR Corporation Datasheet February 2001 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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