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WM2130 10-bit 30MSPS Analogue-To-Digital Converter
Production Data, April 2001, Rev 1.2
DESCRIPTION
The WM2130 is a high speed 10-bit analogue-to-digital converter and operates with independent analogue and digital supplies of 3V to 5.5V. This device includes a high bandwidth sample and hold and internal voltage references. Conversion is controlled by a single clock input. The differential-input sample and hold input gives excellent common-mode noise immunity and low distortion. The device can also be driven in a single ended fashion. The device provides internal reference voltages for setting the ADC full-scale range without the requirement for external circuitry. The WM2130 can also accept external reference levels for applications where higher precision references are required. The WM2130 has also been designed to offer a speed upgrade to users of the AD876 and a replacement for the AD9200 and AD9202 devices. The WM2130 operates as an AD876 in those design slots but at speeds of up to 50% faster.
FEATURES
* * * * * * * * * 10-bit resolution ADC 30MSPS conversion rate Wide input bandwidth (150 MHz full-power bandwidth) sample and hold input amplifier Independent analogue and digital supplies Adjustable internal voltage references Out of range indicator Low power: 87mW typical at 3V supplies Powerdown mode to 3mW typical 28-pin TSSOP package
APPLICATIONS
* * * * Set Top Box (STB) IF and Baseband Digitisation Medical Imaging High speed data acquisition
BLOCK DIAGRAM
REFBF REFTF
REFSENSE MODE PRECISION REFERENCE CIRCUITS
DVDD
WM2130
DGND
M876B OEB AIN
+ SHA -
D[9:0]
REFTS
ADC
OUTPUT BUFFERS OVR
REFBS CLK TIMING CONTROL POWER-DOWN CONTROL STBY
AVDD
AGND
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Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk www.wolfsonmicro.com
Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions.
2001 Wolfson Microelectronics Ltd.
WM2130 PIN CONFIGURATION
AGND DVDD DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 DIO8 DIO9 OVR DGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AIN VREF REFBS REFBF MODE REFTF REFTS M876B AGND REFSENSE STBY OEB CLK
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ORDERING INFORMATION
DEVICE WM2130CDT/V WM2130IDT/V TEMP. RANGE 0 to +70oC -40 to +85oC PACKAGE 28-pin TSSOP 28-pin TSSOP
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME AGND DVDD DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 OVR DGND CLK STBY OEB REFSENSE AGND M876B REFTS REFTF MODE REFBF REFBS VREF AIN AVDD TYPE Ground Supply Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Ground Digital Input Digital Input Digital Input Analogue Input/Output Ground Digital Input Analogue Input Analogue Input/Output Digital Input Analogue Input/Output Analogue Input Analogue Input/Output Analogue Input Supply DESCRIPTION Analogue Ground Positive Digital Supply Digital output bit 0 (lsb) Digital output bit 1 Digital output bit 2 Digital output bit 3 Digital output bit 4 Digital output bit 5 Digital output bit 6 Digital output bit 7 Digital output bit 8 Digital output bit 9 (msb) Over-range output (tri-statable) Digital Ground Clock input Powerdown control Output enable bar - low to enable DO[9:0] and OVR VREF mode control Negative Analogue Supply AD876 mode select Top reference sense Top reference force Input mode select Bottom reference force Bottom reference sense Internal reference output Analog Input Positive Analogue Supply
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WM2130
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per specifications IPC/JEDEC J-STD-020A and JEDEC A113-B, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. CONDITION Digital supply voltage, DVDD to DGND Analogue supply voltage, AVDD to AGND Supply voltage difference, AVDD to DVDD Ground difference, AGND to DGND Digital inputs voltage range (DO[9:0], STBY, OEB, M876B) Voltage range analogue inputs (REFTS, REFBS, REFTF, REFBF, AIN, VREF, REFSENSE, CLK, MODE) Storage temperature Soldering lead temperature, 1.6mm (1/16 inch) from package body for 10 seconds MIN -0.3V -0.3V -6.5V -0.3V DGND - 0.3V AGND - 0.3V -65C MAX +6.5V +6.5V +6.5V +0.3V DVDD + 0.3V AVDD + 0.3V +150C +300C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Clock frequency Clock duty cycle Operating Free Air Minimum Temperature Operating Free Air Maximum Temperature TMIN TMAX WM2130C WM2130I WM2130C WM2130I SYMBOL DVDD AVDD fCLK TEST CONDITIONS MIN 3.0 3.0 5 45 0 -40 70 85 50 NOM 3.3 3.3 MAX 5.5 5.5 30 55 UNIT V V MHz % C C C C
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WM2130 ELECTRICAL CHARACTERISTICS
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Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% Duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, TA = TMIN to TMAX, unless otherwise stated. PARAMETER DC Accuracy Integral nonlinearity Differential nonlinearity Offset error Gain error Missing codes Analogue Input Signal to AIN pin MODE = AGND Input signal range MODE = AVDD / 2, VCMCS fixed MODE = AVDD AIN voltage limits Switched input capacitance Analogue input bandwidth DC leakage current Aperture delay Aperture jitter Conversion Characteristics Conversion frequency Pipeline delay Aperture delay Aperture jitter Dynamic Performance fIN = 3.5MHz Effective number of bits ENOB fIN=3.5MHz, AVDD 5V fIN = 15MHz fIN=15MHz, AVDD 5V fIN = 3.5MHz Spurious free dynamic range SFDR fIN=3.5MHz, AVDD 5V fIN = 15MHz fIN=15MHz, AVDD 5V fIN = 3.5MHz Total Harmonic Distortion THD fIN=3.5MHz, AVDD 5V fIN = 15MHz fIN=15MHz, AVDD 5V fIN = 3.5MHz Signal to noise ratio SNR fIN=3.5MHz, AVDD 5V fIN = 15MHz fIN=15MHz, AVDD 5V fIN = 3.5MHz Signal to noise and distortion ratio SINAD fIN=3.5MHz, AVDD 5V fIN = 15MHz fIN=15MHz, AVDD 5V 52.5 53 56 8.4 9 9 7.8 7.7 60.6 64.6 48.5 53 -60 -66.9 -47.5 -53.1 57 56 53.1 49.4 56 56 48.6 48.1 dB dB -56 dB dB dB tA fCLK 5 3 4 2 30 MHz CLK cycles ns ps rms tA Full-scale input REFBS VCMCS - VREF/2 REFBS AGND 1.2 150 60 4 2 REFTS VCMCS + VREF/2 REFTS AVDD V V V V pF MHz A ns ps rms INL DNL 1.0 0.3 0.4 1.4 2.0 1.0 2.0 3.5 LSB LSB % of FS % of FS SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
No missing codes guaranteed
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WM2130
Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% Duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, TA = TMIN to TMAX, unless otherwise stated. PARAMETER Bottom reference voltage applied to REFBS Top reference voltage applied to REFTS Differential reference input (REFTS - REFBS) Switched input capacitance on REFBS Switched input capacitance on REFTS REFBF output voltage REFTF output voltage Analogue Reference Inputs / Outputs in Centre-Span Mode (MODE=AVDD/2) Reference voltage derived or applied to VREF REFBF output voltage REFTF output voltage 1 (AVDD VREF)/2 (AVDD + VREF)/2 2 V V V VTB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Analogue Reference Inputs / Outputs in Top/Bottom Mode (MODE=AVDD) 0 1 1 0.6 0.6 (AVDD VTB)/2 (AVDD + VTB)/2 AVDD - 1 AVDD 2 V V V pF pF V V
Analogue Reference Inputs / Outputs in Full External Reference Mode (MODE=AGND) (Note 1) Differential reference voltage applied (REFTF - REFBF) Reference input common mode (REFTF + REFBF) / 2 Reference input resistance VREF Input / Output specifications Internal 1V reference to VREF Internal 2V reference to VREF External reference applied to VREF pin in centre-span mode Input impedance in centre-span mode Power Supplies AVDD = DVDD = 3V, MODE = AGND AVDD = DVDD = 5V Standby Power Digital Logic Levels (CMOS Levels) Input LOW level Input HIGH level Notes 1. In full external reference mode the REFTF and REFTS pins should be shorted together, and the REFBF and REFBS pins should be shorted together. Please refer to device operation examples in the device description section of the datasheet. Digital input and output levels refer to the supply used for the input/output buffer on the relevant pin. MODE refers to the AVDD supply, all other digital input/output refers to the DVDD supply. VIL VIH (Note 2) (Note 2) 0.8 x VDD 0.2 x VDD V V PSTBY AVDD = DVDD = 3V, MODE = AGND 29 50 3 5 mW 40 mA REFSENSE = VREF REFSENSE = AGND REFSENSE = AVDD, MODE = AVDD / 2 REFSENSE = AVDD, MODE = AVDD / 2 0.95 1.9 1 18 1.0 2.0 1.05 2.1 2 V V V k AVDD = 3.0V AVDD = 5.0V 1 1.3 2.0 1.5 2.5 680 2 1.7 3.0 V V V
Operating supply current
IAVDD + IDVDD
2.
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WM2130
Sample 2 Sample 1 Analogue Input at AIN
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tCLK tCL tCH
Sample 3 Sample 4
Sample 5
CLK
tD
Pipeline Delay Digital Output Sample 1 Sample 2
Note: All timing measurements are based on 50% of edge transition
Figure 1 Output Timing Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, TA = TMIN to TMAX, unless otherwise stated. PARAMETER Clock Clock period Clock high time Clock low time Timing Pipeline delay Clock to data valid Output disable to hi-Z output Output enable to data valid tD tDZ tDEN 0 0 3 25 20 20 CLK cycles ns ns ns tCLK tCH tCL 33 15 15 16.5 16.5 ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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TYPICAL SYSTEM PERFORMANCE
1 AVDD = DVDD = 3V, fS = 30 MSPS Differential Non-Linearity (LSBs) 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1 0 128 256 384 512 DIGITAL CODE 640 768 896 1024
Figure 2 Differential Non-Linearity
3 AVDD = DVDD = 3V, fS = 30MSPS Integral Non-Linearity (LSBs) 2 1 0 -1 -2 -3 0 128 256 384 512 DIGITAL CODE 640 768 896 1024
Figure 3 Integral Non-Linearity
0
AVDD = DVDD = 3V, fIN = 3.58MHz, -1dB FS
-20 -40
FFT (dB)
-60 -80 -100 -120 -140 0 3 6 9 12 15
Frequency (MHz)
Figure 4 Fast Fourier Transform (FFT)
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WM2130 DEVICE DESCRIPTION
INTRODUCTION
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The WM2130 is a high speed analogue-to-digital converter (ADC) with on-chip sample and hold and reference generation, designed for applications such as composite video digitisation, digital copiers and and high speed data acquisition. The chip architecture consists of: * * * * High bandwidth sample and hold input, which can operate in differential or singleended mode 10-bit, 30MSPS pipeline analogue-to-digital converter (ADC) core On-chip reference generator and reference buffer (external references can also be used for applications where common or high precision references are required) 10-bit parallel interface to read ADC conversion data. An out-of-range output pin indicates when the input signal is outside the converter's range (this is disabled in AD876 compatible mode).
ANALOGUE SIGNAL PATH
The WM2130 analogue signal path consists of a DC clamp with a 10-bit clamp level DAC (discussed under `DC Clamp', below), a high-bandwidth sample and hold unit and a fast 10-bit pipelined analogue to digital converter (ADC core). REFTF VQ+ ADC CORE VQREFBF Figure 5 Analogue Input Signal Flow Figure 5 shows the signal flow through the sample and hold unit to the ADC core, where the process of analogue to digital conversion is performed against the ADC reference voltages, REFTF and REFBF (their generation from internal or external reference sources is described later).
AIN REFTS REFBS
+1
SAMPLE -1/2 AND HOLD -1/2
SAMPLE AND HOLD
The analogue input voltage VIN is applied to the AIN pin, either DC coupled or AC coupled. The differential sample and hold processes VIN with respect to the voltages applied to the REFTS and REFBS pins, and produces a differential output VQ = VQ+ - VQ- given by:
VQ = V IN - VM
where
VM =
REFTS + REFBS 2
For single-ended input signals, VM is a constant voltage; usually the AIN mid-scale input voltage. However, in differential mode (see `ADC Reference Modes', below), REFTS and REFBS can be connected together to operate with AIN as a complementary pair of differential inputs.
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WM2130
ANALOGUE-TO-DIGITAL CONVERTER
Regardless of the reference configuration, VQ is digitised against ADC Reference Voltages REFTF and REFBF, full scale values of VQ being given by:
VQFS + =
REFTF - REFBF 2
and
REFTF - REFBF VQFS - = - 2
Attempts to convert VQ voltages outside the range of VQFS- to VQFS+ are signalled to the application by driving the OVR output pin high. If VQ is less than VQFS-, the ADC output code is 0. If VQ is greater than VQFS+, the output code is 1023.
SIGNAL CHAIN SUMMARY
Combining the above equations and referring back to the input, the positive and negative full-scale voltages at the AIN pin are:
VINFS + = VM +
REFTF - REFBF 2
and
VINFS - = VM -
REFTF - REFBF 2
Therefore the input signal span is given by:
VINFS + - VINFS - = REFTF - REFBF
In order to match the ADC input range to the input signal amplitude, REFTF and REFBF should be set such that:
REFTF - REFBF = (VINFS + - VINFS - )
ADC REFERENCE MODES
The WM2130 supports three basic modes of reference generation, selected by the voltage applied to the MODE pin. These are summarised and explained in Table 1. In differential, Centre Span and Top/Bottom modes, the internally generated ADC references are intened solely for WM2130 internal use and REFTF and REFBF must not be used as voltage references for any other device in the application.
MODE PIN AGND
MODE Full external
FUNCTION
COMMENTS On-chip reference generator and reference buffer are not used. VREF can be internally or externally generated. REFTS and REFBS are joined together and connected either to the negative end of the input signal (true differential mode) or to the AIN mid-scale voltage (centre-span mode). On-chip reference generator is not used. Reference buffer centers external reference voltages around AVDD/2.
REFTF = REFTS REFBF = REFBS
AVDD/2
Differential
REFTF = REFTF =
AVDD + VREF 2 AVDD - VREF 2
AVDD
Top/Bottom
REFTF = REFBF =
AVDD + (REFTS - REFBS ) 2 AVDD - (REFTS - REFBS ) 2
Table 1 WM2130 Reference Generation Modes
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WM2130
FULL EXTERNAL REFERENCE MODE (MODE = AGND)
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When MODE is connected to AGND, the WM2130 operates in full external reference mode. The internal reference buffer is powered down and bypassed, so that the ADC core takes the usersupplied reference voltages at pins REFTS and REFBS (REFTS and REFBS are internally connected to REFTF and REFBF). The mean of REFTF and REFBF must be equal to AVDD/2. Only single-ended input is possible in this mode.
REFTF
AIN REFTS REFBS
+1 -1/2 -1/2
SAMPLE AND HOLD
ADC CORE
REFBF INTERNAL REFERENCE BUFFER
Figure 6 ADC Reference Generation in Full External Mode The full external mode of operation is useful when the application requires more accurate or lower drift reference voltages than the WM2130 can provide, or when devices need to share common reference voltages for best ADC matching. It also offers the possibility of using REFTS and REFBS as sense lines to drive the REFTF and REFBF lines (Kelvin mode) to eliminate any voltage drops from remote references within the system (see Figure 7). In Kelvin configurations, take care when choosing the external op-amps to ensure that they can drive large capacitive loads without oscillating. Although the on-chip reference generator is not used by the WM2130 in full external mode, its output is available on the VREF pin and can be used by other parts of the system. Note that in addition to the internal connections from REFTS to REFTF and REFBS to REFBF, external wire connections must also be made as shown in Figure 8 to minimise resistance (except in Kelvin mode).
AVDD
+FS AVDD/2 -FS
AIN REFTS
REFSENSE
DC SOURCE = AVDD/2 + [(+FS) - (-FS)] * GAIN/2
REFBS
DC SOURCE = AVDD/2 - [(+FS) - (-FS)] * GAIN/2
0.1F
REFTF 10F 0.1F
0.1F REFBF
MODE
Figure 7 Full External Reference Mode (Reference Generator Disabled)
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AVDD
+FS AVDD/2 -FS
WM2130
AIN REFTS 0.1F +
REFT = AVDD/2 + [(+FS) - (-FS)] * GAIN/2
REFSENSE
REFBS REFTF 0.1F 0.1F
0.1F +
REFB = AVDD/2 - [(+FS) - (-FS)] * GAIN/2
10F MODE 0.1F REFBF
Figure 8 Full External Mode with Kelvin connections (Reference Generator Disabled)
DIFFERENTIAL MODE (MODE = AVDD/2)
The WM2130 operates in differential mode when the voltage at the MODE pin is AVDD/2 (midsupply). The ADC reference voltages REFTF and REFBF are generated by the internal reference buffer from VREF. Depending on the connection of the REFSENSE pin, VREF may be supplied by the on-chip reference generator or driven by an external source, as discussed under `On-chip Reference Voltage Generation', below. REFTF and REFBF are centred around AVDD/2 by the internal reference buffer and the voltage difference between them equals VREF.
REFTF = AVDD + VREF 2 AIN REFTS REFBS +1 -1/2 -1/2 REFBF = AVDD - VREF 2
SAMPLE AND HOLD
ADC CORE
VREF AGND
INTERNAL REFERENCE BUFFER
Figure 9 ADC Reference Generation in Differential Mode This mode is suitable for handling differentially presented inputs, which are applied to the AIN and REFTS/REFBS pins. A special case of differential mode is centre span mode, in which the user applies a single-ended signal to AIN and applies the mid-scale input voltage (VM) to the REFTS and REFBS pins.
AVDD/2
+FS
AIN
-FS
MODE
REFTS
REFBS 0.1F
REFSENSE
REFTF VREF
0.1F
10F
0.1F REFBF
Figure 10 Differential Mode, 1V Reference Span WOLFSON MICROELECTRONICS LTD
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WM2130
AVDD/2
+FS VM -FS
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AIN REFTS
MODE
DC SOURCE =VM VM + -
REFBS
0.1F
REFTF
0.1F
10F 0.1F REFBF
REFSENSE
Figure 11 Centre Span Mode, 2V Reference Span
TOP/BOTTOM MODE (MODE = AVDD)
Top/Bottom mode is enabled by connecting the MODE pin to AVDD. In this mode, the ADC Reference voltages REFTF and REFBF are generated by the internal reference buffer from the externally supplied voltages REFTS and REFBS. Only single-ended input is possible in TOP/BOTTOM Mode.
REFTF = AVDD + (REFTS - REFBS) AIN REFTS REFBS +1 -1/2 -1/2
SAMPLE AND HOLD
ADC CORE
INTERNAL REFERENCE BUFFER
REFBF = AVDD - (REFTS - REFBS)
Figure 12 ADC Reference Generation in Top/Bottom Mode The voltage difference between REFTS and REFBS should equal the peak-to-peak input signal amplitude. A smaller voltage difference would give rise to out-of-range conditions, whereas a larger one would not fully utilise the ADC resolution. The average of REFTS and REFBS must be the AIN mid-scale voltage, VM. Typically, REFSENSE is tied to AVDD to disable the on-chip reference generator, but the user can also choose to use its output to drive either REFTS or REFBS.
AVDD
+FS
AIN
-FS
MODE REFSENSE
REFTS
DC SOURCE = VM + [(FS+) - (FS-)]* GAIN/2
DC SOURCE = VM - [(FS+) - (FS-)]* GAIN/2
REFBS
0.1F
REFTF 10F 0.1F
0.1F REFBF
Figure 13 Top/Bottom Mode (Reference Generator Disabled)
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WM2130
ON-CHIP REFERENCE VOLTAGE GENERATOR
The On-chip Reference Generator (ORG) can provide a reference voltage on the VREF pin that is independent of temperature and supply voltage. External connections to the REFSENSE pin control the ORG's output to VREF, as shown in Figure 14. REFSENSE CONNECTION VREF pin AGND External divider junction AVDD ORG OUTPUT TO VREF 1 Volt 2 Volts (1 + RA/RB) Volts - see Figure 14 None (VREF becomes input pin)
Table 2 Controlling the On-chip Reference Generator Connecting REFSENSE to AVDD powers the ORG down, saving power when the ORG function is not required. In differential mode (MODE = AVDD/2), the voltage on VREF determines the ADC reference voltages as follows:
REFTF = REFBF =
AVDD + VREF 2 AVDD - V REF 2
REFTF - REFBF = V REF
When the ORG is enabled, the VREF pin should be decoupled to the circuit board's analogue ground plane close to the WM2130 AGND pin via a 1F tantalum capacitor and a 0.1F ceramic capacitor. The ORG can source currents up to 1mA into external grounded loads when it is not used by the WM2130. Typical buffer load regulation is about 0.5.
INTERNAL REFERENCE BUFFER MODE = AVDD/2 + - + - RA REFSENSE RB AGND VREF = 1 + (RA/RB) 1F 0.1F tantalum
VBG
Figure 14 ORG Operating with External Divider (for Intermediate Reference Voltages)
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WM2130
POWER MANAGEMENT
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In power-sensitive applications (such as battery-powered systems) where the WM2130 ADC is not required to convert continuously, power can be saved between conversion intervals by placing the WM2130 into Power Down mode. This is achieved by pulling the Standby Mode Pin (STBY, pin 16) HIGH. In Power Down mode, the device typically consumes less than 3mW of power. Power down mode is exited by resetting control register bit 3 to 0. On power up from long periods of power down, the WM2130 typically requires 5ms of wake up time before valid conversion results are available. When REFSENSE is tied to AVDD, the reference generator is disabled and supply current reduced by approximately 1.2mA.
DIGITAL OUTPUT FORMAT
While the OEB pin is held low, ADC conversion results are output at the data output pins DO0 (LSB) to DO9 (MSB). The output data format is unsigned binary (output codes 0 to 1023).
AD876 COMPATIBILITY MODE
Pulling M876B (pin 20) low puts the WM2130 into AD876 compatibility mode. In this mode the device latency increases to 3.5 clock cycles and the OVR pin is tri-stated to avoid conflict with the DRGND connection present at pin 13 in AD876 slots. For best dynamic performance, use a 3 cycle latency operating mode if possible.
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WM2130
APPLICATIONS INFORMATION
DRIVING THE CLOCK INPUT
Obtaining good performance from the WM2130 requires care when driving the clock input. Different sections of the Sample-and-Hold and ADC operate while the clock is low or high. The user should ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as possible in which to operate. The CLK pin should also be driven from a low jitter source for best dynamic performance. To maintain low jitter at the CLK input, any clock buffers external to the WM2130 should have fast rising edges. Use a fast logic family such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter. As the CLK input threshold is nominally around AVDD/2, any clock buffers need to have an appropriate supply voltage to drive above and below this level.
DRIVING THE SAMPLE AND HOLD INPUTS
DRIVING THE AIN PIN
Figure 15 shows an equivalent circuit for the WM2130 AIN pin. The load presented to the system at the AIN pin comprises the switched input sampling capacitor, CSample, and various stray capacitances, CP1 and CP2.
AVDD CLK 8pF AIN CP1 CLK AGND + VLAST CP2 = 1.2pF CSample 1.2pF
Figure 15 Equivalent Circuit for Analogue Input Pin AIN The input current pulses required to charge CSample can be time averaged and the switched capacitor circuit modelled as an equivalent resistor
RIN 2 =
1 C S x f CLK
where CS is the sum of CSample and CP2 (see Figure 16). This model can be used to estimate the input loading versus source resistance for high impedance sources.
AVDD CP1 = 8pF AIN IIN + AGND VM = (REFTS + REFBS) /2 RIN2 = 1 / CS fCLK
Figure 16 Equivalent Circuit for the AIN Switched Capacitor Input
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WM2130
AIN INPUT DAMPING
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The charging current pulses into AIN can make the signal source jump or ring, especially if the source is slightly inductive at high frequencies. Inserting a small series resistor of 20 or less in the input path can damp source ringing (see Figure 17). The resistor can be made larger than 20 if reduced input bandwidth or distortion performance is acceptable.
< 20R AIN VS
Figure 17 Damping Source Ringing Using a Small Resistor
DRIVING THE SAMPLE & HOLD REFERENCE INPUTS
The sample and hold reference inputs (connected to pins REFTS and REFBS) present switchedcapacitor loads similar to the AIN pin, but with smaller capacitors (see Figure 18 below). Note that in Top/Bottom mode, the internal reference buffer is also driven from REFTS and REFBS and the total load on these pins is therefore the parallel combination of the sample and hold circuit and the reference buffer.
AVDD REFTS or REFBS 7pF CP1 CLK AGND Mode = AVDD + VLAST CLK CP2 = 0.6pF 0.6pF
CSample
Internal Reference Buffer
Figure 18 Equivalent Circuit of REFTS and REFBS Sample & Hold Inputs
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WM2130
DRIVING THE INTERNAL REFERENCE BUFFER
DRIVING THE VREF PIN (DIFFERENTIAL MODE)
Figure 19 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin (MODE = AVDD/2 and REFSENSE = AVDD).
AVDD RIN VREF 14K REFSENSE=AVDD, Mode = AVDD/2
AGND
+ -
(AVDD+VREF) / 4
Figure 19 Equivalent Circuit of VREF The input current IREF is given by
I REF =
3V REF - AVDD 4 x R IN
Tolerance on this current is 30 % or greater. The user should ensure that VREF is driven from a low noise, low drift source, well-decoupled to analogue ground and capable of driving IREF.
DRIVING THE INTERNAL REFERENCE BUFFER (TOP/BOTTOM MODE)
Figure 20 shows the loading on the REFTS and REFBS pins in Top/Bottom mode due to the internal reference buffer. Note that the sample and hold circuit must also be driven via these pins, which adds additional load (see Driving the Sample & Hold Reference Inputs, above).
AVDD REFTS or REFBS RIN 14K Mode = AVDD
AGND AVDD + (REFTS + REFBS) / 4 + -
Figure 20 Equivalent Circuit of Inputs to Internal Reference Buffer The input currents are given by:
I INTS =
and
3 REFTS - AVDD - REFBS 4 x R IN
I INBS =
3REFBS - AVDD - REFTS 4 x R IN
These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving the sample and hold.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.2 April 2001
17
WM2130
DRIVING REFTF AND REFBF (FULL EXTERNAL REFERENCE MODE)
AVDD
Production Data
REFTF
To REFBS (for Kelvin connection)
AGND AVDD 680R
REFBF
To REFTS (for Kelvin connection)
AGND
Figure 21 Equivalent Circuit of REFTF and REFBF Inputs
REFERENCE DECOUPLING
VREF PIN
When the on-chip reference generator is enabled, the VREF pin should be decoupled to the circuit board's analogue ground plane close to the WM2130 AGND pin via a 1F tantalum capacitor and a 0.1F ceramic capacitor.
REFTF AND REFBF PINS
In any mode of operation, the REFTF and REFBF pins should be decoupled as shown in Figure 22 below. Use short board traces between the WM2130 and the capacitors to minimise parasitic inductance.
0.1F REFTF
10F
0.1F REFBF
WM2331
0.1F
Figure 22 Recommended Decoupling for the ADC Reference Pins REFTF and REFBF
SUPPLY DECOUPLING
The analogue (AVDD, AGND) and digital (DVDD, DGND) power supplies to the WM2130 should be separately decoupled for best performance. Each supply needs at least a 10F electrolytic or tantalum capacitor (as a charge reservoir) and a 100nF ceramic type capacitor placed as close as possible to the respective pins (to suppress spikes and supply noise).
WOLFSON MICROELECTRONICS LTD
PD Rev 1.2 April 2001
18
Production Data
WM2130
DIGITAL OUTPUT LOADING AND CIRCUIT BOARD LAYOUT
The WM2130 outputs are capable of driving rail-to-rail with up to 20pF of load per pin at 30MHz clock and 3V digital supply. Minimising the load on the outputs will improve WM2130 signal-to-noise performance by reducing the switching noise coupling from the WM2130 output buffers to the internal analogue circuits. The output load capacitance can be minimised by buffering the WM2130 digital outputs with a low input capacitance buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks between the WM2130 and this buffer. Noise levels at the output buffers, which may affect the analogue circuits within WM2130, increase with the digital supply voltage. Where possible, consider using the lowest DVDD that the application can tolerate. Use good layout practices when designing the application PCB to ensure that any off-chip return currents from the WM2130 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any sensitive analogue circuits. The WM2130 should be soldered directly to the PCB for best performance. Socketing the device will degrade performance by adding parasitic socket inductance and capacitance to all pins.
USER TIPS FOR OBTAINING BEST PERFORMANCE FROM THE WM2130
* * * * Choose differential input mode for best distortion performance. Choose a 2V ADC input span for best noise performance. Choose a 1V ADC input span for best distortion performance. Drive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB traces.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.2 April 2001
19
WM2130 PACKAGE DIMENSIONS
DT: 28 PIN TSSOP (9.7 x 4.4 x 1.0 mm)
Production Data
DM022.A
b
28
e
15
E1
E
GAUGE PLANE 1 14
D 0.25 c A A2 A1 -C0.1 C
SEATING PLANE
L
Symbols A A1 A2 b c D e E E1 L REF: MIN ----0.05 0.80 0.19 0.09 9.60
4.30 0.45 o 0
Dimensions (mm) NOM --------1.00 --------9.70 0.65 BSC 6.4 BSC 4.40 0.60 ----JEDEC.95, MO-153
MAX 1.20 0.15 1.05 0.30 0.20 9.80
4.50 0.75 o 8
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.2 April 2001
20

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