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S4016V1C
WCFS4016V1C
256K x 16 Static RAM
Features
* High speed -- tAA = 12ns * 2.0V Data Retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE features from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the devices is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The WCFS4016V1C is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground pinout.
Functional Description
The WCFS4016V1C is high-performance CMOS Static RAMs organized as 262K words by 16 bits. Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data
Logic Block Diagram
INPUT BUFFER
Pin Configuration
SOJ TSOP II Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A0 A1 A2 A3 A4 A5 A6 A7 A8
256K x 16 ARRAY 1024 x 4096
I/O0 - I/O7 I/O8 - I/O15
COLUMN DECODER
BHE WE CE OE BLE
A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10
ROW DECODER
Selection Guide
WCFS4016V1C 12ns Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Comm'l Comm'l 12 85 10
A9 A10 A 11 A 12 A 13 A14 A15 A16 A17
SENSE AMPS
April 12, 2002
WCFS4016V1C
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V
DC Input Voltage[1] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 3.3V 0.3V
DC Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Comm'l Comm'l Test Conditions Min. VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 2.4 0.4 VCC + 0.3 0.8 +1 +1 85 40 12ns Max. Unit V V V V A A mA mA
ISB2
10
mA
Capacitance[2]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF
Note: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters.
2
WCFS4016V1C
AC Test Loads and Waveforms
R1 317 OUTPUT 5 pF INCLUDING JIG AND SCOPE (a) R2 351 Z0 =50 INCLUDING ALL COMPONENTS OF TEST EQUIPMENT 30pF
3.3V OUTPUT
50 VTH = 1.5V
(b)
1041CV33-4
ALL INPUT PULSES 3.3V 90% GND Rise time > 2V/ns 10% 90% 10% Fall time: > 2V/ns
(c)
3
WCFS4016V1C
AC Switching Characteristics[3] Over the Operating Range
WCFS4016V1C 12ns Parameter READ CYCLE tpower[4] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE CYCLE[7, 8] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High
[6]
Description VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[5, 6] CE LOW to Low Z
[6] [5, 6]
Min. 1 12
Max.
Unit s ns
12 3 12 6 0 6 3 6 0 12 6 0 6 12 8 8 0 0 8 6 0 3 6 8
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE HIGH to High Z
CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z
Z[5, 6]
Byte Enable to End of Write
Notes: 3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 4. tPOWER gives the minimum amount of time that the power supply should be at typical Vcc values until the first memory access can be performed. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5pF as in part (a) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
4
WCFS4016V1C
Switching Waveforms
Read Cycle No. 1
[9, 10]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
[10, 11]
tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE
DATA OUT
HIGH IMPEDANCE
Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW.
5
WCFS4016V1C
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)
[12, 13]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATAI/O tHD
tHA
Notes: 12. Data I/O is high-impedance if OE or BHE and/or BLE= VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
6
WCFS4016V1C
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD
Truth Table
CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0-I/O7 High Z Data Out Data Out High Z Data In Data In High Z High Z I/O8-I/O15 High Z Data Out High Z Data Out Data In High Z Data In High Z Mode Power Down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 12 Ordering Code WCFS4016V1C-JC12 WCFS4016V1C-TC12 Package Name J T Package Type 44-Lead (400-Mil) Molded SOJ 44-Pin TSOP II Operating Range Commercial
7
WCFS4016V1C
Package Diagrams
44-Lead (400-Mil) Molded SOJ J
44-Pin TSOP II T
8
WCFS4016V1C
Revision History
Document Title: WCFS4016V1C 32K x 8 3.3V Static RAM REV. ** ISSUE DATE 4/12/2002 ORIG. OF CHANGE XFL DESCRIPTION OF CHANGE New Datasheet
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