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| (R) VN750PEP HIGH SIDE DRIVER TARGET SPECIFICATION TYPE VN750PEP s RDS(on) 60 m IOUT 6A VCC 36 V CMOS COMPATIBLE INPUT s ON STATE OPEN LOAD DETECTION s OFF STATE OPEN LOAD DETECTION s SHORTED LOAD PROTECTION s UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN s PROTECTION AGAINST LOSS OF GROUND s VERY LOW STAND-BY CURRENT s PowerSSO-12 REVERSE BATTERY PROTECTION (*) ORDER CODES PACKAGE TUBE T&R PowerSSO-12 VN750PEP VN750PEP13TR DESCRIPTION The VN750PEP is a monolithic device designed in STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protect the device against overload. The device detects open load condition both is on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection. BLOCK DIAGRAM VCC VCC CLAMP OVERVOLTAGE DETECTION UNDERVOLTAGE DETECTION GND Power CLAMP INPUT LOGIC DRIVER OUTPUT CURRENT LIMITER STATUS ON STATE OPENLOAD DETECTION OVERTEMPERATURE DETECTION OFF STATE OPENLOAD AND OUTPUT SHORTED TO VCC DETECTION (*) See application schematic at page 8 October 2003 - Revision 1.2 (Working document) 1/14 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. VN750PEP ABSOLUTE MAXIMUM RATING Symbol VCC - VCC - Ignd IOUT - IOUT IIN ISTAT Parameter DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge (Human Body Model: R=1.5K; C=100pF) - INPUT VESD - STATUS - OUTPUT - VCC Ptot Tj Tc Tstg Power Dissipation TC=25C Junction Operating Temperature Case Operating Temperature Storage Temperature 4000 4000 5000 5000 74 Internally limited - 40 to 150 - 55 to 150 V V V V W C C C Value 41 -0.3 -200 Internally limited -6 +/- 10 +/- 10 Unit V V mA A A mA mA CONNECTION DIAGRAM (TOP VIEW) VCC GND INPUT N.C. STATUS VCC 1 2 3 4 5 6 12 11 10 9 8 7 OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT TAB = VCC CURRENT AND VOLTAGE CONVENTIONS IS IIN INPUT ISTAT STATUS VCC IOUT OUTPUT GND VCC VIN VSTAT IGND VOUT 2/14 VN750PEP THERMAL DATA Symbol Rthj-case Rthj-amb Parameter Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Value 1.7 70 (*) Unit C/W C/W (*) *) When mounted on a standard single-sided FR-4 board with 1 cm2 of Cu (at least 35m thick) connected to all V CC pins. ELECTRICAL CHARACTERISTICS (8V SWITCHING (VCC=13V) Symbol td(on) td(off) dVOUT/dt(on) dVOUT/dt(off) Parameter Turn-on Delay Time Turn-off Delay Time Turn-on Voltage Slope Turn-off Voltage Slope Test Conditions RL=6.5 from VIN rising edge to VOUT=1.3V RL=6.5 from VIN falling edge to VOUT=11.7V RL=6.5 from VOUT=1.3V to VOUT=10.4V RL=6.5 from VOUT=11.7V to VOUT=1.3V Min Typ 40 30 0.5 0.2 Max Unit s s V/s V/s INPUT PIN Symbol VIL IIL VIH IIH Vhyst VICL Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage Test Conditions VIN=1.25V VIN=3.25V IIN=1mA IIN=-1mA 0.5 6 6.8 -0.7 Min 1 3.25 10 8 Typ Max 1.25 Unit V A V A V V V 3/14 1 VN750PEP ELECTRICAL CHARACTERISTICS (continued) STATUS PIN Symbol VSTAT ILSTAT CSTAT VSCL Parameter Test Conditions Status Low Output Voltage ISTAT=1.6mA Status Leakage Current Normal Operation; VSTAT=5V Status Pin Input Normal Operation; VSTAT=5V Capacitance ISTAT=1mA Status Clamp Voltage ISTAT=-1mA Min Typ Max 0.5 10 100 6 6.8 -0.7 8 Unit V A pF V V PROTECTIONS Symbol TTSD TR Thyst tSDL Ilim Vdemag Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Status delay in overload condition Current limitation Turn-off Output Clamp Voltage Test Conditions Min 150 135 7 Typ 175 15 20 6 9 15 15 VCC-41 VCC-48 VCC-55 Max 200 Unit C C C s A A V Tj>Tjsh 9V Symbol IOL tDOL(on) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions VIN=5V IOUT=0A Min 50 Typ 100 Max 200 200 Unit mA s VOL tDOL(off) VIN=0V 1.5 2.5 3.5 V s 1000 OPEN LOAD STATUS TIMING (with external pull-up) IOUT< IOL VOUT > VOL VIN VIN OVERTEMP STATUS TIMING Tj > Tjsh VSTAT VSTAT tDOL(off) tDOL(on) tSDL tSDL 4/14 2 VN750PEP Switching time Waveforms VOUT 90% 80% dVOUT/dt(on) dVOUT/dt(off) 10% t VIN td(on) td(off) t TRUTH TABLE CONDITIONS Normal Operation Current Limitation Overtemperature Undervoltage Overvoltage Output Voltage > VOL Output Current < IOL INPUT L H L H H L H L H L H L H L H OUTPUT L H L X X L L L L L L H H L H STATUS H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L 5/14 VN750PEP ELECTRICAL TRANSIENT REQUIREMENTS ON VCC PIN ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I C C C C C C I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C E C C C C C E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2 IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 6/14 VN750PEP Figure 1: Waveforms NORMAL OPERATION INPUT LOAD VOLTAGE STATUS UNDERVOLTAGE VUSDhyst VUSD INPUT LOAD VOLTAGE STATUS undefined VCC OVERVOLTAGE VCC OPEN LOAD without external pull-up INPUT LOAD VOLTAGE STATUS Tj INPUT LOAD CURRENT STATUS TTSD TR OVERTEMPERATURE 7/14 1 1 VN750PEP APPLICATION SCHEMATIC +5V +5V Rprot STATUS VCC Dld C Rprot INPUT OUTPUT GND VGND RGND DGND GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / (IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. C I/Os PROTECTION: If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot ) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k. 8/14 VN750PEP OPEN LOAD DETECTION IN OFF STATE Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RL V batt. VPU VCC RPU INPUT DRIVER + LOGIC OUT + R STATUS VOL RL IL(off2) GROUND 9/14 VN750PEP Off State Output Current High Level Input Current TBD TBD Input Clamp Voltage Status Leakage Current TBD TBD Status Low Output Voltage Status Clamp Voltage TBD TBD 10/14 VN750PEP On State Resistance Vs Tcase On State Resistance Vs VCC TBD TBD Openload On State Detection Threshold Input High Level TBD TBD Input Low Level Input Hysteresis Voltage TBD TBD 11/14 VN750PEP Overvoltage Shutdown Openload Off State Voltage Detection Threshold TBD TBD Turn-on Voltage Slope Turn-off Voltage Slope TBD Ilim Vs Tcase TBD TBD 12/14 VN750PEP PSSO-12TM MECHANICAL DATA MIN. 1.250 0.000 1.100 0.230 0.190 4.800 3.800 5.800 0.250 0.400 0 1.900 3.600 TYP A A1 A2 B C D E e H h L k X Y ddd A 0.800 IN IM PR EL RY MAX. 1.620 0.100 1.650 0.410 0.250 5.000 4.000 6.200 0.500 1.270 8 2.500 4.200 0.100 13/14 DIM. mm. VN750PEP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 14/14 |
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