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AGC/UP-CONVERTER UPC8158K WITH IQ MODULATOR
FEATURES
* SUPPLY VOLTAGE: VCC = 2.7 to 4.0 V, ICC = 28 mA @ VCC = 3.0 V
23
INTERNAL BLOCK DIAGRAM
22 21 20 19 18 17 16 15 AGCcont Up-Mix 14 AGC 13 Reg 12
* BUILT-IN LPF: Suppresses spurious multipled by TX local (LO1) * AGC AMPLIFIER INSTALLED IN LOCAL PORT OF UPCONVERTER: GCR = 35 dB MIN. @ fout = 1.5 GHz * EXCELLENT PERFORMANCE: Padj = -65dBc TYP. @ f = 50 KHz, EVM = 1.2 %rms TYP. * EXTERNAL IF FILTER: Can be applied between modulator output and up converter input terminal
24 25
LPF 26 27 28 I/Q-Mix Phase Shifter 1 2 3 4 5 6 7 8 Reg 11 10 9
DESCRIPTION
The UPC8158K is a silicon microwave monolithic integrated circuit designed as a quadrature modulator for digital mobile communication systems. This MMIC consist of a 0.8 GHz to 1.5 GHz up-converter and 100 MHz to 300 MHz quadrature modulator which are equipped with AGC and power save functions. This configuration suits IF modulation systems and is packaged in a 28-pin QFN suitable for high density mounting. The chip is manufactured using NEC's 20 GHz fT silicon bipolar process NESATTM III to realize low power consumption. Consequently the UPC8158K can contribute to make RF blocks smaller size, higher performance and lower power consumption.
APLICATIONS
* Digital cellular phones (PDC800M, PDC1.5G,TDMA1900 and so on) * Wireless Communiaction Systems (MMDS, Broadband wireless access)
ELECTRICAL CHARACTERISTICS (TA = 25C, VCC1 = VCC2 = VCC3 = 3.0 V, VPS/VAGC = 2.5 V)
PART NUMBER PACKAGE OUTLINE SYMBOLS ICC (TOTAL) ICC(PS) TOTAL PRFout1 PRFout2 LOL ImR IM3(I/Q) GCR EVM Padj Pout(8fLO1) TPS(Rise) TPS(Fall) ZI/Q II/Q ZLO1 PARAMETERS AND CONDITIONS UP-CONVERTER + QUADRATURE MODULATOR TOTAL Total Circuit Current, No input signal Total Circuit Current at Power Save Mode, VPS 0.5 V(low), No input signal Total Output Power 1, VAGC = 2.5 V Total Output Power 2, VAGC = 1.0 V LO Carrier Leak, fLOL = fLO1 + fLO2 Image Rejection (Side Band Leak) I/Q 3rd Order Distortion AGC Gain Control Range, VAGC = 2 V 1 V Error Vector Magnitude, MOD Pattern PN9 Adjacent Channel Interference, f = 50KHz, MOD Pattern: PN9 Spurious Suppression, fLO1 x 8, fLO1 x 8 (image)Note Power Save Rise Time, VPS(Low) VPS(High) Power Save Fall Time, VPS(High) VPS(Low) I/Q Input Impedance, Between pin I/Ib, Q/Qb I/Q Input Bias Current, Between pin I/Ib, Q/Qb LO1 Input VSWR, fLO1 = 100 M to 300 MHz mA A dBm dBm dBc dBc dBc dB %rms dBc dBc s s k A 80 35 -15 -56.5 23.7 28 0.3 -11.5 -52 -40 -40 -50 40 1.2 -65 -70 2 2 200 5 1.5 :1 13 3.0 -60 -65 5 5 37.6 10 -8 -46.5 -30 -30 -30 UNITS MIN UPC8158K TYP MAX
Note: 1. Without external LC between Fil1 and Fil2 pin on this frequency conditions. Spectrum analyzer conditions: VBW = 300 Hz, RBW = 300 Hz.
California Eastern Laboratories
UPC8158K ABSOLUTE MAXIMUM RATINGS1 (TA = 25C)
SYMBOLS VCC VPS/VAGC PD TA TSTG PARAMETERS Supply Voltage Power Save & AGC Control Power Dissipation2 Operating Ambient Temp. Storage Temperature UNITS V V mW C C RATINGS 5.0 5.0 430 -40 to +85 -55 to +150
RECOMMENDED OPERATING CONDITIONS
PART NUMBER SYMBOLS PARAMETERS VCC Supply Voltage VPS VAGCPS TA fRFout fLO2in fI/Qin PLO1in PLO2in VI/Qin fUPCONin fMODout fLO1in Power Save Voltage AGC Control Voltage Operating Ambient Temp. Upconv. RF Output Freq. LO2 Input Frequency I/Q Input Frequency LO1 Input Level LO2 Input Level I/Q Input Amplitude Upconverter Input Freq. Modulator Output Freq. LO1 Input Frequency MHz 100 300 V V V C MHz MHz MHz dBm dBm mVP-P UPC8158K UNITS MIN TYP MAX 2.7 0 1.0 -30 800 600 DC -18 -18 -15 -15 3.0 4.0 0.3 2.5 +25 +80 1500 1750 10 -12 -12
Note: 1. Operation in excess of any one of these conditions may result in permanent damage. 2. TA = +85 C
420 500
PIN EXPLANATIONS
PIN NO. 1 SYMBOL SUPPLY VOLTAGE (V) Vcc/2 PIN VOLTAGE (V) - FUNCTION AND APPLICATION Input for I signal. This input impedance is 200 k. In the case of that I/Q input signals are single ended, amplitude of the signal 500 m VP-P max. Input for I signal. This input impedance is 200 k. In the case of that I/Q input signals are single ended,Vcc/2 biased DC signal should be input. In the case of the I/Q input signals are differential, amplitude of the signal is 500 m VP-P max. This pin is not connected to internal circuit. This pin should be opened or grounded. Input for Q signal. This input impedance is 200 K. In the case of that I/Q input signals are single ended, amplitude of the signal is 500 m VP-P max. Input for I signal. This input impedance is 200 k. In the case of that I/Q input signals are single ended,Vcc/2 biased DC signal should be input. In the case of the I/Q input signals are differential, amplitude of the signal is 500 m VP-P max. These pins is not connected to internal circuit. These pins should be opened or grounded.
4 5 1 2
EQUIVALENT CIRCUIT
lin
2
linb
Vcc/2
-
3
N.C.
-
-
4
Qinb
Vcc/2
-
5
Qin
Vcc/2
-
6 7 8 9
N.C. N.C. N.C. LO1inb
- - - -
- - - 2.98
Bypass pin of modulator's local input. This pin should be decoupled with 330 pF capacitor.
9 10
10
LO1in
-
2.98
Local signal for modulator. This pin must be coupled with DC cut capacitor 330 pF and should be terminated with 51 resistor Supply Voltage pin modulator, upconverter and AGC circuits.
11
Vcc
2.7 to 4.0
-
UPC8158K PIN EXPLANATIONS (CONT.)
PIN NO. 12 SYMBOL SUPPLY VOLTAGE (V) 0 PIN VOLTAGE (V) - FUNCTION AND APPLICATION Ground pin for modulator, up-converter and AGC circuits. This pin should be grounded with minimum inductance. Form the ground pattern as widely as possible to minimize ground impedance. Local signal input for modulator. This pin must be coupled with DC cut capacitor 33 pF and should be terminated with 51 resistor. EQUIVALENT CIRCUIT
GND
13
LO2in
-
1.8
13
14
14
LO2inb
-
1.8
Bypass pin of up-converter's local signal input. This pin should be decoupled with 33 pF capacitor. This pin is not connected to internal circuit. This pin should be opened or grounded. Ground pin for modulator, up-converter and AGC circuits. This pin should be grounded with minimum inductance. Power save control pin for modulator, upconverter and AGC circuits. This pin also assigned as gain control pin forAGC circuits. Operation status with applied voltages are as follows.
REG
15
N.C.
-
-
16
GND
0
-
17
VPS/VAGC
VPS/VAGC
-
VPS/VAGC (V) 0 to 0.4 1 to 2.5
18 N.C. - -
STATE
17
OFF (Sleep Mode) On (AGC Mode)
AGC Cont
These pins is not connected to internal circuit. These pins should be opened or grounded. Ground pin for modulator, up-converter and AGC circuits. This pin should be grounded with minimum inductance. Supply Voltage pin for modulator, upconverter and AGC circuits. Ground pin for RF output buffer. This pin should be grounded with minimum inductance. This pin is not connected to internal circuit. This pin should be opened or grounded. RF output pin. This pin is emitter follower which is low impedance output port. This pin can be easily matched to 50 impedance using external coupling and decoupling capacitors.
19
GND
0
-
20
Vcc
2.7 to 4.0
-
21
GND
0
-
22
N.C.
-
-
23
RFOUT
-
1.75
External
23
24
N.C.
-
-
These pins are not connected to internal circuit. These pins should be opened or grounded. Supply Voltage pin for RF output buffer.
25
Vcc
2.7 to 4.0
-
UPC8158K PIN EXPLANATIONS (CONT.)
PIN NO. 26 SYMBOL SUPPLY VOLTAGE (V) - PIN VOLTAGE (V) 2.76 FUNCTION AND APPLICATION External inductor and capacitor can supress harmonics spurious of LO1 frequency. LC value should be determined according to LO1 input frequency and suppression level. EQUIVALENT CIRCUIT
FIL1
External 26 27
27
FIL2
-
2.76
28
GND
0
-
Ground pin for modulator, up-converter and AGC circuits. This pin should be grounded with minimum inductance. Form the ground pattern as widely as possible to minimize ground impedance.
Note: 1. Pin Votages are measured on Vcc = 3.0 V.
TEST CIRCUIT
1 000 pF
Voltage Source
0.22 F
Vector Signal Analyzer or Spectrum Analyzer
22 21 20 19 18 17 16 15
100 pF
Voltage Source or Pulse Pattern Generator
VPSVAGC
GND
GND
1 000 pF
Vcc
GND
Signal Generator
0.22 F
100 pF
Voltage Source
2 pF
23 24 25 26 27 28
RFout Vcc Fil1 Fil2 GND
UP-CON AGCcount AGC LPF
LO2b 14 33 pF 51 51 BPF LO2in 13 33 pF
100 pF
1000 pF
REG REG
I/Q Mixer Phase Shifter
Vcc 11 LO1in 10 330 pF LO1b 9 330 pF
BPF
Signal Generator or Network Analyzer
51
Qb
1
Ib
2
3
4
Q
I
5
6
7
8
100 pF
100 pF 100 pF
100 pF
TEST CONDITIONS fLO1in = 178.05 MHz, PLO1in = -15 dBm fLO2in = 1619.05 MHz, PLO2in = -15 dBm fRFout = 1441 MHz - fI/Qin
I/Q Signal Generator
0.22 F
GND 12
Voltage Source
UPC8158K INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (Top View)
UPC8158K
22 21 20 19 18 17 16 15
MAIN ANT 1st LO
SYSTEM APPLICATION
PCS/TDMA PHONE
SUB ANT LNA SW RSSI 2nd LO 1st MIX 2nd MIX To DEMOD RSSI OUT
AGCcont 23 24 25 LPF 26 27 28 I/Q-Mix Phase Shifter 1 2 3 4 5 6 7 8 Reg 11 10 9 Up-Mix 14 AGC 13 Reg 12
SW SW LO2 AGC
PLL1
PLL2
LO1 I 0 (CR)
PA
90 Q
Filter
1. 2. 3. 4. 5. 6. 7.
lin linb N.C. Qinb Qin N.C. N.C.
8. N.C. 9. LO1inb 10. LO1in 11. VCC 12. GND 13. LO2in 14. LO2inb
15. 16. 17. 18. 19. 20. 21.
N.C. GND Vps/Vagc N.C. GND VCC GND
22. 23. 24. 25. 26. 27. 28.
N.C. RFout N.C. VCC Fil1 Fil2 GND
PACKAGE OUTLINE (Units in mm)
UPC8158K 28 PIN PLASTIC QFN
4 -0.5 2 x 0.5 = 1 5.1 0.1
4 -0.5
0.5
5.1 0.1 0.5
Pin 1
PART NUMBER UPC8158K-E1
PACKAGE 28-pin plastic QFN (5.1x0.95mm)
QUANTITY QTY. 2.5 kp/Reel.
0.22 0.5 7 x 0.5 = 3.5 5.5 0.1
Notes: 1. Embossed tape 12 mm wide. Pin 1 is in pull-out direction.
5.5 0.1 5.1
2 x 0.5 = 1
0.22
ORDERING INFORMATION
Pin 28
0.5
1.2
4.7
4.1
0.95 0.1
0.125
0.5
0.22
0.22 4.5 0.5
0.5
(Bottom View)
EXCLUSIVE NORTH AMERICAN AGENT FOR
RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS
CALIFORNIA EASTERN LABORATORIES * Headquarters * 4590 Patrick Henry Drive * Santa Clara, CA 95054-1817 * (408) 988-3500 * Telex 34-6393 * FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) * Internet: http://WWW.CEL.COM 06/05/2001 DATA SUBJECT TO CHANGE WITHOUT NOTICE
0.3

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