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(R)
TDA7310
SERIAL BUS CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER: - 4 STEREO INPUTS - ONE DIFFERENTIAL STEREO INPUT FOR REMOTE SOURCES SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTION TO DIFFERENT SOURCES INPUT AND OUTPUT FOR EXTERNAL EQUALIZER OR NOISE REDUCTION SYSTEM VOLUME CONTROL IN 1.25dB STEPS LOUDNESS FUNCTION TREBLE AND BASS CONTROL FOUR SPEAKER ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN 1.25dB STEPS FOR BALANCE AND FADER FACILITIES - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS SELECTABLE CHIP ADDRESS DEDICATED PIN
PQFP44 (10 x 10) ORDERING NUMBER: TDA7310
DESCRIPTION The TDA7310 is a volume, tone (bass and treble) and fader (front/rear) processor for high quality audio applications in car radio and Hi-Fi systems. Loudness and selectable input gain are provided. The control of all fuctions is accomplished by serial bus microprocessor interface. The AC signal setting is obtained by resistor networks andswitches combined with operationalamplifiers. Thanks to the used BIPOLAR/CMOS Tecnology, Low Distortion, Low Noise and DC stepping are obtained.
PIN CONNECTION (Top view)
November 1999
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
TDA7310
TEST CIRCUIT
THERMAL DATA
Symbol R th j-pins Description Thermal Resistance Junction-pins max Value 85 Unit C/W
ABSOLUTE MAXIMUM RATINGS
Symbol VS T amb Tstg Operating Supply Voltage Ambient Temperature Storage Temperature Range Parameter Value 10.2 -40 to 85 -55 to +150 Unit V C C
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz Volume Control 1.25dB step 2dB step 1.25dB step -78.75 -14 -38.75 0 100 Bass and Treble Control Input Gain 6.25dB step Parameter Min. 6 2 0.01 106 103 0 +14 0 18.75 Typ. 9 Max. 10 Unit V Vrms % dB dB dB dB dB dB dB
Fader and Balance Control Mute Attenuation 2/15
C14 2.2F C19 100nF BOUT(L) 31 SPKR ATT 2 MUTE L2 L3 L4 L5 INPUT SELECTOR + GAIN SERIAL BUS DECODER + LATCHES MUTE 50K VOL + LOUD BASS TREBLE SPKR ATT 42 OUT LEFT REAR OUT LEFT FRONT RB L1 10 BIN(L) TREBLE(L) C20 100nF LOUD(L) 39 32
BLOCK DIAGRAM
OUT(L) 30 38 29
IN(L)
4x 2.2F C1 L1
28
C2
L2
27
LEFT INPUTS
C3
L3
26
C4
L4
25
C5
16
L5
4.7F
LOUD SW
C16 100nF
5.6K
R2
C22 2.7nF
CD
C6
SGND
37 6 5 4
ADDR SCL SEN 3 SDA DIGGND SPKR ATT 43 MUTE SPKR ATT 41 OUT RIGHT FRONT
17
+VCC
10F R5 R4 VOL + LOUD BASS R3 R2 R1 TREBLE
R5
BUS
4.7F C7
18
C8
R4
19
RIGHT INPUTS
C9
R3
20
C10
R2
21
C11
R1
24
4x 2.2F 7 15 OUT(R) C15 C13 2.2F IN(R) 14 40 LOUD(R) 100nF CREF C12 22F 36
SUPPLY
RB MUTE 35 BOUT(R) 100nF C17 5.6K C18 R1 C21 2.7nF 13 BIN(R) 100nF TREBLE(R)
D94AU170
OUT RIGHT REAR
8
9
VCC
AGND
TDA7310
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TDA7310
ELECTRICAL CHARACTERISTICS (Tamb = 25C, VS = 9V, RL = 10K, RG = 600, GV=0dB, f = 1KHz unless otherwise specified) (refer to the test circuit)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS IS SVR Supply Voltage Supply Current Ripple Rejection 6 4 60 9 8 85 10 11 V mA dB
INPUT SELECTORS
R II V CL CMRR INS RL GINmin GINmax GSTEP eIN VDC Input Resistance Clipping Level Common Mode Rejection Differential Input Input Separation (2) Output Load resistance Min. Input Gain Max. Input Gain Step Resolution Input Noise DC Steps G = 18.75dB adjacent gain steps G = 18.75 to Mute 80 2 -1 0 18.75 6.25 2 4 4 1 Input 1, 2, 3, 4 Differential Input 2 50 10 2.5 65 100 K K Vrms dB dB K dB dB dB V mV mV
VOLUME CONTROL
R IN C RANGE AVMIN AVMAX ASTEP EA ET VDC Input Resistance Control Range Min. Attenuation Max. Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps adjacent attenuation steps From 0dB to AVmax 0.1 0.5 AV = 0 to -20dB AV = -20 to -60dB -1.25 -3 -1 33 75 0 75 1.25 0 1.25 2 2 1 k dB dB dB dB dB dB dB mV mV
SPEAKER ATTENUATORS
Control Range Step Resolution Attenuation set error Output Mute Attenuation DC Steps adjacent att. steps from 0 to mute 80 100 0 1 37.5 1.25 1.5 dB dB dB dB mV mV
BASS CONTROL (1)
Control Range Step Resolution RB VDC Internal Feedback Resistance DC Steps adjacent control steps +14 2 50 0.1 dB dB K mV
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TDA7310
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
TREBLE CONTROL (1)
Control Range Step Resolution VDC DC Steps adjacent control steps +14 2 0.1 dB dB mV
AUDIO OUTPUTS
Clipping Level Output Load Resistance Output Load Capacitance Output resistance DC Voltage Level 4.2 75 4.5 d = 0.3% 2 10 120 4.8 2.5 Vrms K nF V
GENERAL
e NO Output Noise BW = 20-20KHz, flat output muted all gains = 0dB all gains = 0dB; VO = 1Vrms VIN = 1Vrms 80 AV = 0 to -20dB -20 to -60 dB 2.5 5 106 0.01 103 0 0 1 2 V V dB % dB dB dB
15
S/N d Sc
Signal to Noise Ratio Distortion Channel Separation left/right Total Tracking error
BUS INPUTS
V IL VIH VO Input Low Voltage Input High Voltage Output Voltage SDA Acknowledge IO = 1.6mA 3 0.4 1 V V V
LOUDNESS SWITCH
V IL VIH IIN Input Low Voltage Input High Voltage Input Current DC Step ON OFF position 3 -5 0.1 +5 1 V V A mV
Loudness OFF = pin38 Open; Loudness ON = pin 38 Closed to GND ADDRESS PIN (Internal 50K pull down resistor)
V IL VIH IIN
Notes: (1) Bass and Treble response see attached diagram (fig.17). The center frequency and quality of the resonance behaviour can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network (2) The selected input is grounded thru the 2.2F capacitor.
Input Low Voltage Input High Voltage Input Current VCC -1V
1
V V A
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TDA7310
APPLICATION SUGGESTION (see to Test circuit)
Component C1 to C4, C8 to C11 C5, C7 C6 C12 C13, C14 Recc. Value 2.2F 4.7F 10F 22F 2.2F Purpose THD optimization at low frequencies CMRR optimization differential input C REF * SVR optimization < -66 dB Decoupling Input-Output if external equalizer is not used Loudness characteristic Bass Filter (standard T - type) cut freq. = 100Hz Treble Filter Higher cut frequency Lower cut frequency Smaller than Recc. Value Worse THD at very low frequencies Worse CMRR for ratio not equal to 12 Better SVR at low frequencies Worse SVR at low frequencies Larger than
C15, C16 C17, C18 R1 C!9, C20 R2 C21 C22
100nF 100nF 5.6k 100nF 5.6k 2.7nF
Figure 1: Loudness versus Volume Attenuation
Figure 2: Loudnessversus Frequency (CLOUD = 100nF)
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TDA7310
Figure 3: Loudness versus External Capacitors Figure 4: Noise vs. Volume/Gain Settings
LOUDNESS VS = 9V Volume = -40dB All other control flat Cin = 2.2F
Figure 5: Signal to Noise Ratio vs. Volume Setting
Figure 6: Distortion vs. Load Resistance
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TDA7310
Figure 7 : Channel Separation (L R) vs. Frequency Figure 8 : Input Separation (L1 L2, L3, L4) vs. Frequency
Figure 9 : Supply Voltage Rejection vs. Frequency
Figure 10: Output Clipping Level vs. Supply Voltage
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TDA7310
Figure 11: Quiescent Current vs. Supply Voltage Figure 12: Supply Current vs. Temperature
Figure 13: Bass Resistance vs. Temperature
Figure 14: Typical Tone Response (with the ext. components indicated in the test circuit)
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TDA7310
APPLICATION INFORMATION (continued) SERIAL BUS INTERFACE S-BUS Interface and I2CBUS Compability Data transmission from microprocessor to the TDA7310 and viceversa takes place thru the 3wire S-BUS interface, consisting of the three lines SDA, SCL, SEN. If SDA and SEN inputs are short-circuited together, then the TDA7310 appears as a standard I 2CBUS slave. According to I2CBUS specification the S-BUS lines are connected to a positive supply voltage via pull-up resistors. Data Validity As shown in fig. 15, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions I2CBUS: as shown in fig. 16 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. S-bus: the start/stop conditions (points 1 and 6) are detected exclusively by a transition of the SEN line (1 0 / 0 1)wile the SCL line is at the HIGH level. The SDA line is only allowed to change during the time the SCL line is low (points 2, 3, 4, 5). after the start information (point 1) the SEN line returns to the HIGH level and remains uncharged for all the time the transmission is performed. Byte Fornat Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on Figure 17: Acknowledge on the I2CBUS Figure 15: Data Validity on the I2CBUS
Figure 16: Timing Diagram of S-BUS and I2CBUS
the SDA line during the acknowledge clock pulse (see fig. 17). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock.
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TDA7310
APPLICATION INFORMATION (continued) The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7310 address (the 8th bit of the byte must be 0). The TDA7310 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
TDA7310 ADDRESS MSB S 1 0 first byte 0 0 1 0 A LSB 0 ACK MSB DATA LSB
ACK
MSB DATA
LSB
ACK P
Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATION Chip address
1 MSB 0 0 0 1 0 A 0 LSB
A = LOGIC LEVEL ON PIN ADDR
DATA BYTES
MSB 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 B2 0 1 0 1 0 1 1 B1 B1 B1 B1 B1 G1 0 1 B0 B0 B0 B0 B0 G0 C3 C3 A2 A2 A2 A2 A2 S2 C2 C2 A1 A1 A1 A1 A1 S1 C1 C1 LSB A0 A0 A0 A0 A0 S0 C0 C0 FUNCTION Volume control Speaker ATT LR Speaker ATT RR Speaker ATT LF Speaker ATT RF Audio switch Bass control Treble control
Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 6.25dB steps
STATUS AFTER POWER ON RESET
Volume speaker audio Switch bass treble gain -77.5dB -37.5dB Stereo 5 +2dB +2dB 0dB 11/15
TDA7310
SOFTWARE SPECIFICATION (continued) DATA BYTES (detailed description) Volume
MSB 0 0 B2 B1 B0 A2 0 0 0 0 1 1 1 1 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 A2 A1 0 0 1 1 0 0 1 1 A1 LSB A0 0 1 0 1 0 1 0 1 A0 FUNCTION Volume 1.25dB steps 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 Volume 10dB steps 0 -10 -20 -30 -40 -50 -60 -70
For example a volume of -45dB is given by: 00100100
Speaker Attenuators
MSB 1 1 1 1 0 0 1 1 0 1 0 1 B1 B1 B1 B1 B0 B0 B0 B0 A2 A2 A2 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 A1 A1 A1 A1 0 0 1 1 0 0 1 1 LSB A0 A0 A0 A0 0 1 0 1 0 1 0 1 FUNCTION Speaker LF Speaker RF Speaker LR Speaker RR 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 -10 -20 -30 Mute
For example attenuation of 25dB on speaker RF is given by: 10110100
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TDA7310
Audio Switch
MSB 0 1 0 G1 G0 S2 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 S1 0 0 1 1 0 0 1 1 LSB S0 0 1 0 1 0 1 0 1 FUNCTION Audio Switch Stereo 1 Stereo 2 Stereo 3 Stereo 4 Stereo 5 Not allowed Not allowed Not allowed +18.75dB +12.5dB +6.25dB 0dB
For example to select the stereo 2 input with a gain of +12.5dB the 8bit string is: 01001001 Bass and Treble
0 0 1 1 1 1 0 1 C3 C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 C1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 C0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Bass Treble -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
C3 = Sign For example Bass at -10dB is obtained by the following 8 bit string: 01100010
Purchase of I2C Components from STMicroelectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I 2C Standard Specifications as defined by Philips.
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TDA7310
mm MIN. A A1 A2 B c D D1 D3 e E E1 E3 L L1 K 0.65 12.95 9.90 0.25 1.95 0.30 0.13 12.95 9.90 13.20 10.00 8.00 0.80 13.20 10.00 8.00 0.80 1.60 0(min.), 7(max.) 0.95 0.026 13.45 10.10 0.510 0.390 2.00 2.10 0.45 0.23 13.45 10.10 TYP. MAX. 2.45 0.010 0.077 0.012 0.005 0.51 0.390 0.52 0.394 0.315 0.031 0.520 0.394 0.315 0.031 0.063 0.037 0.530 0.398 0.079 0.083 0.018 0.009 0.53 0.398 MIN. inch TYP. MAX. 0.096
DIM.
OUTLINE AND MECHANICAL DATA
PQFP44 (10 x 10)
D D1 D3 A1
33 34 23 22
0.10mm .004 Seating Plane
A A2
E3
E1
B
44 1 11
12
E
B
e
L1 L
C
K
PQFP44
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TDA7310
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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