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| EVALUATION KIT AVAILABLE 1 TC1044S CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER FEATURES s s s s s s s s s s s Converts +5V Logic Supply to 5V System Wide Input Voltage Range .................... 1.5V to 12V Efficient Voltage Conversion ......................... 99.9% Excellent Power Efficiency ............................... 98% Low Power Consumption ............ 80A @ VIN = 5V Low Cost and Easy to Use -- Only Two External Capacitors Required RS-232 Negative Power Supply Available in 8-Pin Small Outline (SOIC) and 8-Pin Plastic DIP Packages Improved ESD Protection ..................... Up to 10kV No External Diode Required for High Voltage Operation Frequency Boost Raises FOSC to 45kHz GENERAL DESCRIPTION The TC1044S is a pin-compatible upgrade to the Industry standard TC7660 charge pump voltage converter. It converts a +1.5V to +12V input to a corresponding -1.5V to -12V output using only two low cost capacitors, eliminating inductors and their associated cost, size and EMI. Added features include an extended supply range to 12V, and a frequency boost pin for higher operating frequency, allowing the use of smaller external capacitors. The on-board oscillator operates at a nominal frequency of 10kHz. Frequency is increased to 45kHz when pin 1 is connected to V+. Operation below 10kHz (for lower supply current applications) is possible by connecting an external capacitor from OSC to ground (with pin 1 open). The TC1044S is available in both 8-pin DIP and 8-pin small outline (SOIC) packages in commercial and extended temperature ranges. 2 3 4 5 6 PIN CONFIGURATION (DIP and SOIC) ORDERING INFORMATION Part No. Package 8-Pin SOIC 8-Pin Plastic DIP 8-Pin SOIC 8-Pin Plastic DIP 8-Pin CerDIP 8-Pin CerDIP Temp. Range 0C to +70C 0C to +70C - 40C to +85C - 40C to +85C - 25C to +85C - 55C to +125C BOOST 1 CAP + 2 8 V+ BOOST 1 CAP + 2 8 V+ 7 OSC TC1044SCOA TC1044SCPA TC1044SEOA TC1044SEPA TC1044SIJA TC1044SMJA 7 OSC TC1044SCPA GND 3 TC1044SEPA 6 LOW VOLTAGE (LV) TC1044SIJA CAP - 4 TC1044SMJA 5 VOUT GND 3 TC1044SCOA 6 LOW VOLTAGE (LV) TC1044SEOA 5 VOUT CAP - 4 TC7660EV Charge Pump Family Evaluation Kit FUNCTIONAL BLOCK DIAGRAM V+ 8 BOOST 1 CAP + 2 OSC 7 RC OSCILLATOR 2 VOLTAGE- LEVEL TRANSLATOR 4 CAP - LV 6 5 INTERNAL VOLTAGE REGULATOR LOGIC NETWORK 3 GND TC1044S-12 9/16/96 VOUT 7 TC1044S 8 4-43 TELCOM SEMICONDUCTOR, INC. CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER TC1044S ABSOLUTE MAXIMUM RATINGS* Supply Voltage ......................................................... +13V LV, Boost and OSC Inputs Voltage (Note 1) ......................... - 0.3V to (V++ 0.3V) for V+ < 5.5V + - 5.5V) to (V++ 0.3V) (V for V+ > 5.5V Current Into LV (Note 1) ...................... 20A for V+ > 3.5V Output Short Duration (VSUPPLY 5.5V) ......... Continuous Lead Temperature (Soldering, 10 sec) ................. +300C Package Power Dissipation (TA 70C) (Note 2) 8-Pin CerDIP ..................................................800mW 8-Pin Plastic DIP ............................................. 730mW 8-Pin SOIC .....................................................470mW Operating Temperature Range C Suffix .................................................. 0C to +70C I Suffix ............................................... - 25C to +85C E Suffix ............................................. - 40C to +85C M Suffix ........................................... - 55C to +125C Storage Temperature Range ................ - 65C to +150C *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS: TA = +25C, V+ = 5V, COSC = 0, Test Circuit (Figure 1), unless otherwise indicated. Symbol I+ Parameter Supply Current Test Conditions RL = 0C < TA < +70C - 40C < TA < +85C - 55C < TA < +125C 0C < TA < +70C - 40C < TA < +85C - 55C < TA < +125C Min TA Max, RL = 10 k, LV Open Min TA Max, RL = 10 k, LV to GND IOUT = 20mA IOUT = 20mA, 0C TA +70C IOUT = 20mA, -40C TA +85C IOUT = 20mA, -55C TA +125C V+ = 2V, IOUT = 3 mA, LV to GND 0C TA +70C - 55C TA +125C Pin 7 open; Pin 1 open or GND Boost Pin = V+ RL = 5 k; Boost Pin Open TMIN < TA < TMAX; Boost Pin Open Boost Pin = V+ RL = V+ = 2V V+ = 5V Min -- -- -- -- -- -- -- 3 1.5 -- -- -- -- -- -- -- -- 96 95 -- 99 -- -- Typ 80 -- -- -- -- -- -- -- -- 60 70 70 105 -- -- 10 45 98 97 88 99.9 1 100 Max 160 180 180 200 300 350 400 12 3.5 100 120 120 150 250 400 -- -- -- -- -- -- -- -- Unit A I+ Supply Current (Boost Pin = V+) Supply Voltage Range, High Supply Voltage Range, Low Output Source Resistance A + VH2 + VL2 V V ROUT kHz % FOSC PEFF Oscillator Frequency Power Efficiency VOUT EFF ZOSC Voltage Conversion Efficiency Oscillator Impedance % M k NOTES: 1. Connecting any input terminal to voltages greater than V+ or less than GND may cause destructive latch-up. It is recommended that no inputs from sources operating from external supplies be applied prior to "power up" of the TC1044S. 2. Derate linearly above 50C by 5.5mW/C. 4-44 TELCOM SEMICONDUCTOR, INC. CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER TC1044S Circuit Description The TC1044S contains all the necessary circuitry to implement a voltage inverter, with the exception of two external capacitors, which may be inexpensive 10 F polarized electrolytic capacitors. Operation is best understood by considering Figure 2, which shows an idealized voltage inverter. Capacitor C1 is charged to a voltage, V+, for the half cycle when switches S1 and S3 are closed. (Note: Switches S2 and S4 are open during this half cycle.) During the second half cycle of operation, switches S2 and S4 are closed, with S1 and S3 open, thereby shifting capacitor C1 negatively by V+ volts. Charge is then transferred from C1 to C2, such that the voltage on C2 is exactly V+, assuming ideal switches and no load on C2. The four switches in Figure 2 are MOS power switches; S1 is a P-channel device, and S2, S3 and S4 are N-channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S3 and S4 must always remain reverse-biased with respect to their sources, but not so much as to degrade their ON resistances. In addition, at circuit start-up, and under output short circuit conditions (VOUT = V+), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this will result in high power losses and probable device latch-up. This problem is eliminated in the TC1044S by a logic network which senses the output voltage (VOUT) together with the level translators, and switches the substrates of S3 and S4 to the correct level to maintain necessary reverse bias. V+ S1 S2 1 2 C2 VOUT = - VIN C1 GND S3 S4 3 4 5 6 7 Figure 2. Idealized Charge Pump Inverter The voltage regulator portion of the TC1044S is an integral part of the anti-latch-up circuitry. Its inherent voltage drop can, however, degrade operation at low voltages. To improve low-voltage operation, the "LV" pin should be connected to GND, disabling the regulator. For supply voltages greater than 3.5V, the LV terminal must be left open to ensure latch-up-proof operation and prevent device damage. Theoretical Power Efficiency Considerations In theory, a capacitive charge pump can approach 100% efficiency if certain conditions are met: (1) The drive circuitry consumes minimal power. (2) The output switches have extremely low ON resistance and virtually no offset. V+ 1 2 C1 1F + 3 4 TC1044S 8 7 6 5 COSC* IS V+ (+5V) (3) The impedances of the pump and reservoir capacitors are negligible at the pump frequency. The TC1044S approaches these conditions for negative voltage multiplication if large values of C1 and C2 are used. Energy is lost only in the transfer of charge between capacitors if a change in voltage occurs. The energy lost is defined by: E = 1/2 C1 (V12 - V22) V1 and V2 are the voltages on C1 during the pump and transfer cycles. If the impedances of C1 and C2 are relatively high at the pump frequency (refer to Figure 2) compared to the value of RL, there will be a substantial difference in voltages V1 and V2. Therefore, it is desirable not only to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C1 in order to achieve maximum efficiency of operation. 4-45 IL RL VOUT C2 10F + NOTE: For large values of COSC (>1000pF), the values of C1 and C2 should be increased to 100F. Figure 1. TC1044S Test Circuit 8 TELCOM SEMICONDUCTOR, INC. CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER TC1044S Dos and Don'ts * Do not exceed maximum supply voltages. * Do not connect the LV terminal to GND for supply voltages greater than 3.5V. * Do not short circuit the output to V+ supply for voltages above 5.5V for extended periods; however, transient conditions including start-up are okay. * When using polarized capacitors in the inverting mode, the + terminal of C1 must be connected to pin 2 of the TC1044S and the + terminal of C2 must be connected to GND. The output characteristics of the circuit in Figure 3 are those of a nearly ideal voltage source in series with 70. Thus, for a load current of -10mA and a supply voltage of +5V, the output voltage would be - 4.3V. The dynamic output impedance of the TC1044S is due, primarily, to capacitive reactance of the charge transfer capacitor (C1). Since this capacitor is connected to the output for only 1/2 of the cycle, the equation is: 2 XC = = 3.18, 2f C1 where f = 10 kHz and C1 = 10F. Paralleling Devices Simple Negative Voltage Converter Figure 3 shows typical connections to provide a negative supply where a positive supply is available. A similar scheme may be employed for supply voltages anywhere in the operating range of +1.5V to +12V, keeping in mind that pin 6 (LV) is tied to the supply negative (GND) only for supply voltages below 3.5V. V+ 1 C1 10F + 2 3 4 TC1044S 8 7 6 5 + VOUT* C2 10F Any number of TC1044S voltage converters may be paralleled to reduce output resistance (Figure 4). The reservoir capacitor, C2, serves all devices, while each device requires its own pump capacitor, C1. The resultant output resistance would be approximately: ROUT = ROUT (of TC1044S) n (number of devices) * NOTES: Figure 3. Simple Negative Converter V+ 1 2 C1 3 4 8 7 1 2 C1 3 4 8 7 RL TC1044S "1" 6 5 TC1044S "n" 6 5 + C2 Figure 4. Paralleling Devices Lowers Output Impedance 4-46 TELCOM SEMICONDUCTOR, INC. CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER TC1044S V+ 1 2 + 10F 3 4 8 7 1 2 + 10F 3 4 8 7 1 2 TC1044S "n" 6 5 + + 10F VOUT* 10F TC1044S "1" 6 5 * NOTES: 1. VOUT = -n(V+) for 1.5V V+ 12V 3 4 5 6 7 Figure 5. Increased Output Voltage by Cascading Devices Cascading Devices The TC1044S may be cascaded as shown (Figure 5) to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is 10 devices for light loads. The output voltage is defined by: VOUT = -n(VIN) where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual TC1044S ROUT values. Changing the TC1044S Oscillator Frequency It may be desirable in some applications (due to noise or other considerations) to increase the oscillator frequency. Pin 1, frequency boost pin may be connected to V+ to increase oscillator frequency to 45kHz from a nominal of 10kHz for an input supply voltage of 5.0 volts. The oscillator may also be synchronized to an external clock as shown in Figure 6. In order to prevent possible device latch-up, a 1k resistor must be used in series with the clock output. In a V+ 1 2 + 10F 3 4 8 1k 7 CMOS GATE V+ situation where the designer has generated the external clock frequency using TTL logic, the addition of a 10k pullup resistor to V+ supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be 1/2 of the clock frequency. Output transitions occur on the positive-going edge of the clock. It is also possible to increase the conversion efficiency of the TC1044S at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is achieved by connecting an additional capacitor, COSC, as shown in Figure 7. Lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C1) and the reservoir (C2) capacitors. To overcome this, increase the values of C1 and C2 by the same factor that the frequency has been reduced. For example, the addition of a 100pF capacitor between pin 7 (OSC) and pin 8 (V+) will lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and necessitate a corresponding increase in the values of C1 and C2 (from 10F to 100F). Positive Voltage Multiplication The TC1044S may be employed to achieve positive voltage multiplication using the circuit shown in Figure 8. In this application, the pump inverter switches of the TC1044S are used to charge C1 to a voltage level of V+ - VF (where V+ is the supply voltage and VF is the forward voltage drop of diode D1). On the transfer cycle, the voltage on C1 plus the supply voltage (V+) is applied through diode D2 to capacitor C2. The voltage thus created on C2 becomes (2V+) - (2VF), or twice the supply voltage minus the combined forward voltage drops of diodes D1 and D2. The source impedance of the output (VOUT) will depend on the output current, but for V+ = 5V and an output current of 10mA, it will be approximately 60. 4-47 TC1044S 6 5 + 10F VOUT Figure 6. External Clocking 8 TELCOM SEMICONDUCTOR, INC. CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER TC1044S V+ 1 2 C1 + 3 4 8 7 COSC Figure 9, could be used to start this circuit up, after which it will bypass the other (D1 and D2 in Figure 9 would never turn on), or else the diode and resistor shown dotted in Figure 10 can be used to "force" the internal regulator on. TC1044S 6 5 + C2 VOUT Voltage Splitting The same bidirectional characteristics used in Figure 10 can also be used to split a higher supply in half, as shown in Figure 11. The combined load will be evenly shared between the two sides. Once again, a high value resistor to the LV pin ensures start-up. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit, and then the circuit of Figure 5, +15V can be converted (via +7.5V and -7.5V) to a nominal -15V, though with rather high series resistance (~250). Figure 7. Lowering Oscillator Frequency Combined Negative Voltage Conversion and Positive Supply Multiplication Figure 9 combines the functions shown in Figures 3 and 8 to provide negative voltage conversion and positive voltage multiplication simultaneously. This approach would be, for example, suitable for generating +9V and -5V from an existing +5V supply. In this instance, capacitors C1 and C3 perform the pump and reservoir functions, respectively, for the generation of the negative voltage, while capacitors C2 and C4 are pump and reservoir, respectively, for the multiplied positive voltage. There is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the finite impedance of the common charge pump driver at pin 2 of the device. V+ VOUT = -V+ 1 2 3 + C1 4 + C2 8 7 + C3 TC1044S 6 5 D1 D2 VOUT = (2 V +) - (2 VF) + C4 Efficient Positive Voltage Multiplication/Conversion Since the switches that allow the charge pumping operation are bidirectional, the charge transfer can be performed backwards as easily as forwards. Figure 10 shows a TC1044S transforming -5V to +5V (or +5V to +10V, etc.). The only problem here is that the internal clock and switchdrive section will not operate until some positive voltage has been generated. An initial inefficient pump, as shown in Figure 9. Combined Negative Converter and Positive Multiplier Negative Voltage Generation for Display ADCs The TC7106 is designed to work from a 9V battery. With a fixed power supply system, the TC7106 will perform conversions with input signal referenced to power supply ground. V+ 1 2 3 4 8 7 D1 D2 + C1 + C2 VOUT = (2 V+) - (2 VF) Negative Supply Generation for 4 Digit Data Acquisition System The TC7135 is a 4 digit ADC operating from 5V supplies. The TC1044S provides an inexpensive -5V source. (See AN16 and AN17 for TC7135 interface details and software routines.) TC1044S 6 5 Figure 8. Positive Voltage Multiplier 4-48 TELCOM SEMICONDUCTOR, INC. CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER TC1044S VOUT = -V- RL1 50 F V+ + 1 2 100 k 3 100 k + V- 4 8 7 1 M 1 2 3 4 5 80 100 1 2 C1 10F + 3 4 8 7 1 M + 10F TC1044S 6 5 V- INPUT VOUT = + V + -V - 50 2 F RL2 TC1044S 6 5 50 F Figure 10. Positive Voltage Conversion Figure 11. Splitting a Supply in Half TYPICAL CHARACTERISTICS Unloaded Osc Freq vs. Temperature 12 OSCILLATOR FREQUENCY (kHz) 60 OSCILLATOR FREQUENCY (kHz) Unloaded Osc Freq vs. Temperature with Boost Pin = VIN 10 8 6 4 VIN = 12V 2 0 -40 -20 0 20 40 60 80 100 VIN = 5V 50 40 30 VIN = 12V 20 10 0 -40 -20 0 20 40 60 VIN = 5V TEMPERATURE (C) TEMPERATURE (C) 6 Without Load 1000 800 600 IDD (A) VOLTAGE CONVERSION EFFICIENCY (%) Supply Current vs. Temperature (with Boost Pin = VIN) Voltage Conversion 101.0 100.5 100.0 99.5 99.0 98.5 TA = 25C 98.0 1 2 3 4 5 6 7 8 9 10 11 12 INPUT VOLTAGE VIN (V) VIN = 12V 7 400 200 0 -40 10K Load VIN = 5V -20 0 20 40 60 80 100 TEMPERATURE (C) 8 TELCOM SEMICONDUCTOR, INC. 4-49 CHARGE PUMP DC-TO-DC VOLTAGE CONVERTER TC1044S TYPICAL CHARACTERISTICS (Cont.) Output Source Resistance vs. Supply Voltage 100 OUTPUT SOURCE RESISTANCE () Output Source Resistance vs. Temperature 100 OUTPUT SOURCE RESISTANCE () 70 50 30 80 60 40 20 0 -40 VIN = 2.5V VIN = 5.5V IOUT = 20mA TA = 25C 10 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12 SUPPLY VOLTAGE (V) -20 0 20 40 60 80 100 TEMPERATURE (C) Output Voltage vs. Output Current 0 OUTPUT VOLTAGE VOUT (V) Power Conversion Efficiency vs. Load 100 90 80 70 60 50 40 30 20 10 0 1.0 1.5 2.0 3.0 4.5 6.0 7.5 9.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 50.0 55.0 60.0 LOAD CURRENT (mA) -2 -4 -6 -8 -10 -12 0 10 20 30 40 50 60 70 80 90 100 POWER EFFICIENCY (%) Boost Pin = Open Boost Pin = V+ OUTPUT CURRENT (mA) Supply Current vs. Temperature 200 175 SUPPLY CURRENT IDD (A) 150 125 100 75 50 25 0 -40 -20 0 20 40 60 80 100 VIN = 5.5V VIN = 12.5V TEMPERATURE (C) 4-50 TELCOM SEMICONDUCTOR, INC. |
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