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| STSJ100NH3LL N-CHANNEL 30 V - 0.0032 - 25 A PowerSO-8TM STripFETTM III MOSFET FOR DC-DC CONVERSION Table 1: General Features TYPE STSJ100NH3LL Figure 1: Package RDS(on) < 0.0035 ID 25A VDSS 30V TYPICAL RDS(on) = 0.0032 @ 10V OPTIMAL RDS(on) x Qg TRADE-OFF @ 4.5V SWITCHING LOSSES REDUCED LOW THRESHOLD DEVICE IMPROVED JUNCTION-CASE THERMAL RESISTANCE PowerSO-8TM DESCRIPTION The STSJ100NH3LL utilizes the latest advanced design rules of ST's proprietary STripFETTM technology. This process coupled to unique metallization techniques realizes the most advanced low voltage MOSFET in SO-8 ever produced. The exposed slug reduces the Rthj-c improving the current capability. Figure 2: Internal Schematic Diagram APPLICATIONS SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS FOR MOBILE PCs DRAIN CONTACT ALSO ON THE BACKSIDE Table 2: Order Codes SALES TYPE STSJ100NH3LL MARKING 100H3LLPACKAGE PowerSO-8 PACKAGING TAPE & REEL Rev. 5 November 2005 1/11 STSJ100NH3LL Table 3: Absolute Maximum ratings Symbol VDS VGS ID(2) ID(1) ID IDM(3) Ptot(2) Ptot(1) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Total Dissipation at TC = 25C Parameter Drain-source Voltage (VGS = 0) Value 30 16 100 25 15.6 100 70 3 Unit V V A A A A W W Table 4: Thermal Data Rthj-c Rthj-pcb(4) Tj Tstg Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Operating Junction Temperature Storage Temperature Max Max 1.8 42 150 -55 to 150 C/W C/W C C Table 5: Avalanche Characteristics Symbol IAV EAS Parameter Not-Repetitive Avalanche Current (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAV, VDD = 24 V) Max Value 12.5 1.3 Unit A J ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 6: On /Off Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 250A, VGS = 0 VDS = Max Rating VDS =Max Rating ,TC = 125C VGS = 16V VDS = VGS, ID = 250A VGS = 10V, ID = 12.5A VGS = 4.5V, ID = 12.5A 1 0.0032 0.004 0.0035 0.005 Min. 30 1 10 100 Typ. Max. Unit V A A nA V IGSS VGS(th) RDS(on) 2/11 STSJ100NH3LL ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Dynamic Symbol gfs (5) Ciss Coss Crss RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Input Resistance Test Conditions VDS=10V, ID = 12.5A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 30 4450 655 50 1 2 3 Max. Unit S pF pF pF f=1MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain Table 8: Switching On Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 15V, ID = 12.5A RG = 4.7 , VGS = 10V (see Figure 15) VDD=15V, ID=25A VGS=4.5V (see Figure 17) Min. Typ. 18 50 30 12.5 10 40 Max. Unit ns ns nC nC nC Table 9: Switching Off Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions VDD = 15V, ID = 12.5A RG = 4.7 , VGS = 10V (see Figure 15) Min. Typ. 75 8 Max. Unit ns ns Table 10: Source Drain Diode Symbol ISD ISDM VSD(5) trr Qrr IRRM Notes 1. 2. 3. 4. 5. This value is noted according to Rthj-pcb This value is noted according to Rthj-c Pulse width limited by safe operating area When Mounted on 1 inch FR-4 board, 2 oz Cu (t 10 sec.) Pulsed: pulse duration=300s, duty cycle 1.5% Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Test Conditions Min. Typ. Max. 25 100 Unit A A V ns nC A ISD = 25A ,VGS = 0 ISD = 25A, di/dt = 100A/s VDD = 25V, Tj = 150C (see Figure 16) 32 34 2.1 1.3 3/11 STSJ100NH3LL Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/11 STSJ100NH3LL Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized BVDSS vs Temperature Figure 11: Normalized On Resistance vs Temperature Figure 14: Source-Drain Diode Forward Characteristics 5/11 STSJ100NH3LL Table 11: Allowable Iav vs. Time in Avalanche The previous curve gives the single pulse safe operating area for unclamped inductive loads, under the following conditions: PD(AVE) =0.5*(1.3*BVDSS *IAV ) EAS(AR) =PD(AVE) *tAV Where: IAV is the Allowable Current in Avalanche PD(AVE) is the Average Power Dissipation in Avalanche (Single Pulse) tAV isthe Time in Avalanche 6/11 STSJ100NH3LL Figure 15: Switching Times Test Circuit For Resistive Load Figure 17: Gate Charge Test Circuit Figure 16: Test Circuit For Diode Recovery Times 7/11 STSJ100NH3LL In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 8/11 STSJ100NH3LL PowerSO-8TM MECHANICAL DATA mm. MIN. 0.1 0.65 0.35 0.19 0.25 4.8 5.8 1.27 3.81 2.79 3.8 0.4 4.0 1.27 0.6 8 (max.) 0.14 0.015 TYP MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 5.0 6.2 0.188 0.228 0.050 0.150 0.110 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019 DIM. A a1 a2 a3 b b1 C c1 D E e e3 e4 F L M S 9/11 STSJ100NH3LL Table 12: Revision History Date 14-Sep-2004 23-May-2005 29-Jun-2005 16-Nov-2005 Revision 2 3 4 5 Preliminary Data. New values on table 5 New RG value on table 6 Complete version Description of Changes 10/11 STSJ100NH3LL Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 11/11 |
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