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SP8481 Series* Monolithic, 12-Bit Data Acquisition System
s Complete Monolithic 8-Channel, 12-Bit DAS s 100kHz Throughput s 16-Bit Microprocessor Bus Interface s Latched MUX Address s All-channel Deselect s 8/4-Bit Nibble Output s No Missing Codes to 12-Bits s 32-Pin Packages s 200mW Max Power Dissipation
* Formerly part of the SP410 Series.
DESCRIPTION... The SP8481 Series are complete monolithic data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter in 32-pin packages. Linearity errors of 0.5 and 1.0 LSB, and Differential Non-linearity to 12-bits is guaranteed, with no missing codes over temperature. Channel-to-channel crosstalk is typically -85dB. Multiplexer settling plus acquisition time is 1.9s maximum; A/D conversion time is 8.1s maximum.
MULTIPLEXER
12-BIT A/D CONVERTER
MUX DECODE ADD. LATCH
REFERENCE
CONTROL LOGIC
CLOCK
8-BIT/4-BIT NIBBLE OUTPUT
301
ABSOLUTE MAXIMUM RATINGS
VCC to Common Ground .............................................. 0V to +16.5V VLOGIC to Common Ground ............................................... 0V to +7V Analog Common to Digital Common Ground ............... -0.5V to +1V Digital Inputs to Common Ground .................... -0.5V to VLOGIC+0.5V Digital Outputs to Common Ground ................. -0.5V to V LOGIC+0.5V Multiplexer Analog Inputs ...................................... -16.5V to +31.5V Gain and Offset Adjustment ................................ -0.5V to VCC+0.5V Analog Input Maximum Current ............................................. 25mA Temperature with Bias Applied ............................. -55C to +125C Storage Temperature ............................................ -65C to +150C Lead Temperature, Soldering .................................... 300C, 10sec
SPECIFICATIONS
(TA= 25C and nominal supply voltages unless otherwise noted)
MIN. ANALOG INPUTS Input Voltage Range Multiplexer Inputs Configuration Input Impedance ON Channel OFF Channel Input Bias Current Per Channel Crosstalk OFF to ON Channel
TYP. 0 to +5
MAX.
UNIT V
CONDITIONS
8 Single-ended 109 1010 10 250 -90 -80 -70 nA nA dB dB dB Bits LSB LSB LSB LSB LSB %FSR Parallel with 30pF Parallel with 5pF 25C -55C to +125C 10kHz, 0V to +5VPk-to-pk 50kHz, 0V to +5VPk-to-pk 100kHz, 0V to +5VPk-to-pk
ACCURACY Resolution 12 Linearity Error -K, -B 0.5 -J, -A 1 Differential Non-Linearity -K, -B 1 -J, -A 2 Offset Error 2 Gain Error 0.3 No Missing Codes -K, -B Guaranteed TRANSFER CHARACTERISTICS Throughput Rate 100 MUX Settling/Acquisition 1.9 A/D Conversion 8.1 STABILITY Linearity 0.5 2.5 Offset 5 25 Gain 10 50 DIGITAL INPUTS Capacitance 5 Logic Levels VIH +2.4 +5.5 VIL -0.5 +0.8 IIH 5 IIL 5
Adjustable to zero Adjustable to zero
kHz s s ppm/C ppm/C ppm/C pF V V A A
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SPECIFICATIONS (continued)
(TA= 25C and nominal supply voltages unless otherwise noted)
MIN. DIGITAL OUTPUTS Capacitance Logic Levels VOH VOL Leakage Current Data Output POWER REQUIREMENTS VLOGIC ILOGIC VCC ICC Power Dissipation ENVIRONMENTAL Operating Temperature Commercial; -J, -K Industrial; -A, -B Storage Temperature
TYP. 5
MAX.
UNIT pF
CONDITIONS
+2.4 40 Offset Binary +4.5 0.8 +11.4 9 140 +0.4
V V A
I OH 500A I OL 1.6mA High impedance, data bits only
+5.5 2 +16.5 12 200
V mA V mA mW
0 -40 -65
+70 +85 +150
C C C
303
PIN ASSIGNMENTS...
(Refer to Page 11 for package configurations and dimensions)
DB8/DB0 (LSB)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CLOCK
REF 12-BIT ADC DECODE 8-CHANNEL MULTIPLEXER 5 6 7 8 9 10 11 12 13 14 15 16
CONTROL LOGIC 1 2 3 4
A0
VLOGIC
VCC
R/C
CE
ANA. GND.
GAIN ADJ.
ANA. IN. CH0
ANA. IN. CH1
ANA. IN. CH2
ANA. IN. CH3
ANA. IN. CH4
ANA. IN. CH5
ANA. IN. CH6
OFFSET ADJ.
PIN FUNCTION... R/C -- Read/Convert -- Initiates conversion on the Hi-to-low transition; logic low disconnects data bus; logic high initiates read CS -- Chip Select -- Logic high disconnects data bus; logic low allows conversion or reading of data CE -- Chip Enable -- Logic low disables read or convert; logic high enables read or convert A0 -- Device Address -- Logic low enables 8 MSB read; logic high enables 4 LSB read MA0, MA1, MA2 -- MUX Address 0, 1 & 2 -- Selects analog input channels CH0 through CH7 LATCH -- MUX Address Latch -- Logic high to low transition captures MUX address on MUX address lines MAEN -- MUX Enable -- Logic low allows normal MUX address; logic high deselects CHO through CH7 DB0 through DB11 -- Data Outputs -- Logic high is binary true; logic low binary false
MULTIPLEXER TRUTH TABLE
LATCH H -> L H -> L H -> L H -> L H -> L H -> L H -> L H -> L H -> L 0 1 MAEN MA MA MA
2 1 0
ANA. IN. CH7
DIG. GND.
DB11/DB3
DB10/DB2
DB9/DB1
STATUS
LATCH
MAEN
MA2
MA1
MA0
DB7
DB6
DB5
DB4
CS
OPERATION CH Selected
O
0 0 0 0 0 0 0 0 1 X X
0 0 0 0 1 1 1 1 n X X
0 0 1 1 0 0 1 1 n X X
0 1 0 1 0 1 0 1 n X X
CH Selected
1
CH Selected
2
CH Selected
3
CH Selected
4
CH Selected
5
CH Selected
6
CH Selected
7
All Deselected Prev. Ch. n Held Prev. Ch. n Held
Table 1. Multiplexer Truth Table
CONTROL TRUTH TABLE
CE 0 X L->H 1 1 1 1 CS X 1 0 H ->L 0 0 0 A
O
R/C X X X X X 0 1
OPERATION None None Start Conversion Start Conversion Start Conversion Enable 8 MSBs Enable 4 LSBs
X X 0 0 H ->L 1 1
Table 2. Control Truth Table
304
FEATURES... The SP8481 Series are complete data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V unipolar full scale inputs. Output data is formatted as an 8-bit/4-bit nibble. Linearity errors of 0.5 and 1.0 LSB, and Differential Non-linearity to 12-bits is guaranteed, with no missing codes over temperature. Channel-to-channel crosstalk is typically -85dB. Multiplexer settling plus acquisition time is 1.9s maximum; A/D conversion time is 8.1s maximum. Versions of the SP8481 Series are available in 32-pin plastic DIP or SOIC packages. Operating temperature ranges are 0C to +70C commercial and -40C to +85C industrial.
buffers until the conversion has been completed. The SAR, timed by the clock, sequences through the conversion cycle and returns an end-of- convert flag to the control section of the ADC. The clock is then disabled by the control section, which puts the STATUS output line low. The control section is enabled to allow the data to be read by external command (R/C). Multiplexer Control and Inputs On the SP8481 the multiplexer inputs are latched with LATCH. The address line latches MA0, MA1 and MA2 select the appropriate analog input channel. When low, the LATCH line retains the last MUX address data, and therefore the previously addressed MUX channel. All channels may be deselected by bringing the MAEN control line to a logic "1". When this control function is used, the analog input will be connected to pin 8 or analog ground. Since the MUX address latches are controlled by the LATCH and MAEN control lines, MUX channel select data need not be held by the bus for any minimum period after the conversion has been initiated. However it is advisable that the MUX not be changed at all during the full 10s conversion time due to capacitive coupling effects of digital edges through the silicon. The SP8481 multiplexer inputs have been designed to allow substantial overvoltage conditions to occur without any damage. The inputs are diode-clamped and further protected with a 200 series resistor. As a result, momentary (10 seconds) input voltages can be as low as -16.5V or as high as +31.5V with no change or degradation in multiplexer performance or crosstalk. This feature allows the output voltage of an externally connected op amp to swing to 15V supply levels with no multiplexer damage. Complicated power-up sequencing is not required to protect the SP8481. The multiplexer inputs may be damaged, however, if the inputs are allowed to either source or sink greater than 100mA. Initiating a Conversion The SP8481 was designed to require a minimum of control to perform a 12-bit conversion. The control input used is R/C which tri-states the
CIRCUIT OPERATION... The SP8481 is a complete 8-channel data acquisition system (DAS), with on-board multiplexer, voltage reference, sample-and-hold, clock and tri-state outputs. The digital control architecture is very similar to the industry-standard 574-type A/D, and uses identical control lines and digital states. The multiplexer for the SP8481 is identical in operation to many discrete devices available today, except that it has been integrated into the single-chip DAS. The appropriate channel is selected using the MUX address lines MA0, MA1, and MA2 per the truth table. The selected analog input is fed through to the ADC. The input impedance into any MUX channel will be on the order to 109 ohms, since it is connected to the integral sampling structure of the capacitor DAC. Crosstalk is kept to -85dB at 0V to 5Vp-p over an input frequency range of 10kHz to 50kHz. When the control section of the SP8481 initiates a conversion command the internal clock is enabled, and the successive approximation register (SAR) is reset to all zeros. Once the conversion has been started it cannot be stopped or restarted. Data is not available at the output
305
+15V
+15V
125K
100K
SP8481
GAIN ADJUST 5 0.3% Trim Range 10K
SP8481
OFFSET ADJUST 4 -1.5mV to +3mV 5K
Center pot for zero correction
19K
Figure 1. Offset Adjust
Figure 2. Gain Adjust
outputs when high and starts the conversion when low. CS and CE may also be used with R/C to initiate a conversion. The last of the three inputs to reach the correct state starts the conversion, therefore one, two or all three may be dynamically controlled. The nominal delay from all three is the same and they may change state simultaneously. In order to ensure that a particular input controls the conversion the other two should be set up at least 50ns earlier. The STATUS line indicates when a conversion is in process and when it is complete. The A0 input is used to configure the output data. The conversion cycle is started when R/C is brought low and must be held low for a minimum of 50ns. The R/C signal will also put the output latches in a tri-state mode when low. Approximately 200ns after R/C is low, STATUS will change from low to high. This output signal will stay high while the SP8481 is performing a conversion. Valid data will be latched to the output bus, through internal control, 500ns prior to the STATUS line transitioning from a high to low. Reading the Data The output data buffers will remain in a high impedance state until the following four conditions are met: R/C is HIGH, STATUS is LOW, CE is HIGH and CS is LOW. The data lines become active in response to the four conditions and will latch data according to the conditions of A0 line. Please refer to Figure 5 for the appropriate timing. All conditions must be met at least 50ns prior to reading the data to allow sufficient time for the output latches to come out of the high impedance state. A0 is used to access the data. 306
The first 8 MSBs will be on pins 26 through 19, with pin 26 being the MSB. The remaining 4 LSBs will be on pins 23 through 26 with pin 23 being the LSB. When A0 is switched from one state to the next, there is a 50ns output latch propagation delay between the MSBs and LSBs being present on the output pins. CALIBRATION The calibration procedure for the SP8481 consists of adjusting the most negative input voltage (0V) to the ideal output code for offset adjustment, and then adjusting the most positive input voltage (5.0V) to its ideal output code for gain adjustment. Offset Adjustment The offset adjustment must be completed first. Please refer to Figure 1. Apply an input voltage of 0.5LSB or 610V to any multiplexer input. Adjust the offset potentiometer so that the output code fluctuates evenly between 000...000 and 000...001. It is only necessary to observe the lower eight LSB's during this procedure. Gain Adjustment With the offset adjusted, the gain error can now be trimmed to zero. The ideal input voltage corresponding to 1.5 LSB's below the nominal full scale input value, or +4.988V, is applied to any multiplexer input. The gain potentiometer is adjusted so that the output code alternates evenly between 111...111 and 111...110. Again, only the lower eight LSB's need be observed during this procedure. With the above adjustment made, the converter is now calibrated.
LATCH
tMDS tMDH
MA0 - MA2 tHRL R/C tDS STATUS tHDR DB11 - DB0 DATA VALID tC tHS DATA VALID
LOW PULSE FOR R/C DYNAMIC CHARACTERISTICS
VCC = +15V; VLOGIC = +5V; TA = 25C
PARAMETER tHRL tDS tHDR tHS tMDS tMDH Low R/C Pulse Width Status Delay from R/C Data Valid after R/C Status Delay after Data Valid MUX Data Setup MUX Data Valid
MIN. 50
TYP.
MAX. 200
UNIT ns ns ns ns ns
CONDITIONS
25 500 50 3 10
s
Figure 3. Low Pulse for R/C Timing
307
CE tSSC CS
tHEC
tHSC tSRC R/C
tHRC A0 tSAC tHAC
STATUS tDSC DB11 - DB0
tC HIGH IMPEDANCE
CONVERT MODE DYNAMIC CHARACTERISTICS
VCC = +15V; VLOGIC = +5V; T A = 25C
PARAMETER t HEC t SSC t HSC t SRC t HRC t SAC t HAC t DSC tC CE Pulse Width CS to CE Setup CS Low During CE High R/C to CE Setup R/C Low during CE High A0 to CE Setup A0 Valid During CE High Status Delay from CE Conversion Time
MIN. 50 50 50 50 50 0 50
TYP.
MAX.
UNIT ns ns ns ns ns ns ns
CONDITIONS
200 10
ns s
Figure 4. Convert Mode Timing
308
CE tHRS CS tSRR R/C tHRR
A0 tSAR STATUS tHS DB11 - DB0 HIGH IMPEDANCE tDD tHD tHAR
DATA VALID tHL
READ MODE DYNAMIC CHARACTERISTICS
VCC = +15V; VLOGIC = +5V; TA = 25C
PARAMETER tHRS tSRR tHRR tSAR tHAR tDD tHL CS Valid After CE Low R/C to CE Setup R/C High After CE Low A0 to CE Setup A0 Valid After CE Low Access Time from CE Output Float Delay
MIN. 0 50 0 50 50 20
TYP. 0 0 50
MAX.
UNIT ns ns ns ns ns ns
CONDITIONS
Data Valid After CE Low
150 150
ns ns
Figure 5. Read Mode Timing
309
Figure 6. FFT; 6kHz, 5V (0dB) Full Scale Input; FS=100kHz
Figure 7. FFT; 12kHz, 5V (0dB) Full Scale Input; FS=100kHz
Figure 8. FFT; 24kHz, 5V (0dB) Full Scale Input; FS=100kHz
Figure 9. FFT; 48kHz, 5V (0dB) Full Scale Input; FS=100kHz
Figure 10. FFT; 48kHz, 1V (-14dB) Input; FS=100kHz
310
ORDERING INFORMATION
12-Bit Data Acquisition System, Latched Multiplexer Address, 8-Bit/4-Bit Data Output: Commercial (0C to +70C): Integral Non-Linearity Package SP8481JP ............................................................................ 1.0LSB INL ....................................................................... 32-pin, 0.6" Plastic DIP SP8481KP ........................................................................... 0.5LSB INL ....................................................................... 32-pin, 0.6" Plastic DIP SP8481JS ............................................................................ 1.0LSB INL ................................................................................ 32-pin, 0.3" SOIC SP8481KS ........................................................................... 0.5LSB INL ................................................................................ 32-pin, 0.3" SOIC Industrial (-40C to +85C): Integral Non-Linearity Package SP8481AP ........................................................................... 1.0LSB INL ....................................................................... 32-pin, 0.6" Plastic DIP SP8481BP ........................................................................... 0.5LSB INL ....................................................................... 32-pin, 0.6" Plastic DIP SP8481AS ........................................................................... 1.0LSB INL ................................................................................ 32-pin, 0.3" SOIC SP8481BS ........................................................................... 0.5LSB INL ................................................................................ 32-pin, 0.3" SOIC
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