View SLD-3091FZ_1310352.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary
SLD-3091FZ
Product Description
Sirenza Microdevices' SLD-3091FZ is a robust 30 Watt high performance LDMOS transistor designed for operation from 10 to 2200MHz. It is an excellent solution for applications requiring high linearity and efficiency at a low cost. The SLD-3091FZ is typically used in power amplifiers, repeaters, and radio amplifier applications. The power transistor is fabricated using Sirenza's high performance XeMOS IITM process.
Pb
RoHS Compliant & Green Package
30 Watt Discrete LDMOS FET in Ceramic Flanged Package
Functional Schematic Diagram Product Features
ESD Protection
* * * * * *
30 Watt Output P1dB Single Polarity Supply Voltage High Gain: 18 dB at 915 MHz High Efficiency: 45% at 30W CW XeMOS II LDMOS Integrated ESD Protection, 1B
Applications
Case Flange = Ground
Key RF Specifications
Symbol Frequency Gain Efficiency IRL Linearity RTH Parameter Frequency of Operation 30 Watt CW, 915 MHz Drain Efficiency at 30 Watt CW, 915 MHz
* * * * *
Base Station PA driver Repeaters Radio Amplifier Military Communication GSM, CDMA, RFID, Point-to-Point
Units MHz dB % dB dBc Watt C/W
Min. 10
Typ. 19 45 -15 -28 35 2.4
Max. 2200
Input Return Loss, 30 Watt Output Power, 915 MHz 3rd Order IMD at 30 Watt PEP (Two Tone), 915 MHz 1dB Compression (P1dB), 915 MHz Thermal Resistance (Junction-to-Case)
Test Conditions VDS = 28.0V, IDQ = 300mA, TFlange = 25C
T
Key DC Parameters
Symbol gm VGSThreshold VDS Breakdown Ciss Crss Coss RDSon Parameter Forward Transconductance @ 425mA IDS IDS=3mA 1mA IDS current Input Capacitance (Gate to Source) VGS=0V, VDS=28V Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V Output Capacitance (Drain to Source) VGS=0V, VDS=28V Drain to Source Resistance, VGS=10V, VDS=250mV Unit mA / V Volt Volt pF pF pF Min Typ. 1650 3.3 65 66 1.4 30 0.2 Max
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC 1
http://www.sirenza.com EDS-104668 Rev C
Preliminary SLD-3091FZ 30 Watt LDMOS FET
Quality Specifications
Parameter ESD Rating Description Human Body Model Rating 1B
Pin Description
Pin # 1 2 Flange Function Gate Drain Source, Gnd Description Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant bias current over the operating temperature range. Care must be taken to protect against video transients that exceed the recommended maximum input power or voltage. Transistor RF output and drain bias voltage. Typical voltage is 28V. Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and RF performance. See mounting instructions for recommendation.
Pin Diagram
ESD Protection
Pin 1
Pin 2
Note 1: Gate voltage must be applied to the device concurrently or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages should never be applied to the transistor unless it is properly terminated on both input and output. Note 2: The required VGS corresponding to a specific IDQ will vary from device to device due to the normal die-to-die variation in threshold voltage with LDMOS transistors. Note 3: The threshold voltage (VGSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza application notes AN-067 LDMOS Bias Temperature Compensation.
Case Flange = Ground
Absolute Maximum Ratings
Parameters Drain Voltage (VDS ) Gate Voltage (VGS) RF Input Power Load Impedance for Continuous Operation Without Damage Output Device Channel Temperature Lead Temperature During Solder Reflow Operating Temperature Range Storage Temperature Range Value 35 20 +36 10:1 +200 +270 -20 to +90 -40 to +100 Unit V V dBm VSWR C C C C
Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging and testing devices must be observed.
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 2
http://www.sirenza.com EDS-104668 Rev C
Preliminary SLD-3091FZ 30 Watt LDMOS FET
Typical Performance Curves in 900 MHz Application Circuit
CW Gain, Efficiency vs Pout Vdd=28V, Idq=0.3A, Freq=912 MHz
22 21 20 19 18 Gain (dB) 17 16 15 14 13 12 11 10 0
60 55 50
45 40 35 Gain (dB), Efficiency (%) 30 25 20 15 10 5 0 0
2 Tone Gain, Efficiency, Linearity vs Pout Vdd=28V, Idq=0.3A, Freq=912 MHz, Delta F=1 MHz
-25 -30 -35 -40 -45 -50 -55 IMD (dBc)
45 40 35 30 25 Efficiency (%)
Gain Efficiency
20 15 10 5 0
Gain IM3 IM7
Efficiency IM5
-60 -65 -70
10
20 Pout (W)
30
40
50
5
10
15 Pout (W PEP)
20
25
30
CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Idq=0.3A, Pout=30W
60 50 Gain (dB), Efficiency (%) 40 30 20 10 0 885 0 -5 Input Return Loss (dB)
2 Tone Gain, Efficiency, Linearity and IRL vs Frequency Vdd=28V, Idq=0.3A, Pout=30W PEP, Delta F=1 MHz 60 50 Gain (dB), Efficiency (%) 40 30 20 10 0 885 895 905 915 925 935 Frequency (MHz) 0 -10 -20 -30 -40 -50 -60 945 IMD(dBc), IRL (dB)
Gain IM3 IM7
Efficiency IM5 IRL
Gain Efficiency IRL
-10 -15 -20 -25 -30 945
895
905
915
925
935
Frequency (MHz)
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 3
http://www.sirenza.com EDS-104668 Rev C
Preliminary SLD-3091FZ 30 Watt LDMOS FET
Typical Performance Curves in 900 MHz Application Circuit over Temperature
CW Gain vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=920 MHz 22 21 20 19
Efficiency vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=912 MHz 50
40 Efficiency (%)
Gain (dB)
18 17 16 15 14 13 0 10 20 Pout (W) 30 40 t-=85 t=25 t=-25
30 t-=85 t=25 t=-25
20
10
0 0 10 20 Pout (W) 30 40
IMD3 vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=912 MHz -20 -25 -30 -35 IMD3 (dBc) -40 -45 -50 -55 -60 -65 -70 0 5 10 Pout (W avg) 15 20 t-=-25 t=25 t=-85
2 tone Efficiency vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=912 MHz 40 35 30 Efficiency (%) 25 20 15 10 5 0 0 5 10 Pout (W avg) 15 20 t-=-25 t=25 t=-85
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 4
http://www.sirenza.com EDS-104668 Rev C
Preliminary SLD-3091FZ 30 Watt LDMOS FET
Impedance Data
Frequency (MHz) 850 895 960 Zsource 0.9 - j 0.7 0.8 - j 0.7 0.7 - j 0.9 Zload 2.6 - j 0.5 2.4 - j 0.4 2.3 - j 0.1
Impedances Referenced to Wirebond/PCB Interface.
Device under test
Input Matching Network Z source
Output Matching Network Z load
Zsource and Zload are the optimal impedances presented to the SLD-3091FZ when operating at 28V, Idq=300mA, Pout=30 W PEP
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 5
http://www.sirenza.com EDS-104668 Rev C
Preliminary SLD-3091FZ 30 Watt LDMOS FET
900 MHz Application Circuit
Pin Descriptions - 900 MHz Application Circuit
Connector Pin # Function Description
J1 J2 J3
Coax Coax 1
RF in RF out Gnd
RF input to test fixture (50 Ohm system) RF output to test fixture (50 Ohm system) DC ground for D package module. Also connected to RF ground. DC ground for D package module. Also connected to RF ground. Gate voltage for the SLD3091FZ. Nominally +4Vdc. Drain voltage for the SLD3091FZ. Nominally +28Vdc. Drain voltage for the SLD3091FZ. Nominally +28Vdc.
J3 J3 J3
2 3 4
Gnd VGS VDS VDS
J3
5
Bill of Materials - 900 MHz Application Circuit
Component Description Manufacturer
PCB J1, J2 J3 C2 C3, C11 C5, C13 C7 C1,C4,C6, C8,C19 C10,C12, C14 C15,C16 C17 C18 C2 C9 R2 R1 Mounting Screws
Rogers 4350, er=3.5 Thickness=30 mils Connector, SMA END 0.037" MTA Post Header, 5 Pin, Rectangle, Polarized, Surface Mount Capacitor, Lytic 22F, 35V Cap, 0.1mF, 100V, 10%, 1206 Cap, 1000pF, 100V, 10%, 1206 Capacitor, Lytic 220uF, 50V CAP, 68PF,250V,5%,0603 CAP, 12PF,250V,1%,0603 CAP, 10PF,250V,1%,0603 CAP, 7.5 PF, 250V,0603 CAP, 27PF,250V,5%,0603 CAP, 0.22UF, 50V, CERAMIC, X7R, 1206, CAP, 4.3 PF, 250V, 0603 RES, 560, 1/16W, 5%, 0402 RES, 0.0, 1/16W, 5%, 0402 4-40 X 0.250"
Rogers Johnson AMP Panasonic Johanson Johanson Panasonic ATC ATC ATC ATC ATC Kemet ATC Panasonic Panasonic Various
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 6
http://www.sirenza.com EDS-104668 Rev C
Preliminary SLD-3091FZ 30 Watt LDMOS FET
900 MHz Application Circuit Heatsink
To receive Gerber files, DXF drawings, and assembly recommendations for the test board with fixture, contact applications support at support@sirenza.com.
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 7
http://www.sirenza.com EDS-104668 Rev C
Preliminary SLD-3091FZ 30 Watt LDMOS FET
Package Outline
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. ADHESIVE FROM LID MAY EXTEND A MAXIMUM OF 0.020" BEYOND EDGE OF LID. 4. LID MAY BE MISALIGNED TO THE BODY OF THE PACKAGE BY A MAXIMUM OF 0.008" IN ANY DIRECTION.
DIM A B C D E F G H J
INCHES MILLIMETERS MIN MAX MIN MAX 0.225 0.235 5.72 0.149 0.178 3.78 0.077 0.087 1.96 0.355 0.365 9.02 0.210 0.220 5.33 5.97 4.52 2.21 9.27 5.59 0.004 0.006 0.102 0.152
0.795 0.805 20.19 20.45 0.697 0.703 17.70 17.86 DIA 0.130 DIA 3.30
PIN 1. DRAIN PIN 2. GATE PIN 3. SOURCE
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 8
http://www.sirenza.com EDS-104668 Rev C

▲Up To Search▲

Price & Availability of SLD-3091FZ

	To Download SLD-3091FZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .