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S6C0657
263 / 256 CHANNEL TFT-LCD GATE DRIVER
November. 1999. Ver. 0.1
Prepared by:
Jae il Byeon
kerigma@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
S6C0657
263 / 256 CHANNEL TFT-LCD GATE DRIVER
S6C0657 Specification Revision History Version 0.0 0.1 Original
The contents of page 9, 10 and 13 have been modified
Content
Date Aug.1999 Nov.1999
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263 / 256 CHANNEL TFT-LCD GATE DRIVER
S6C0657
CONTENTS
INTRODUCTION .................................................................................................... 4 FEATURES............................................................................................................. 4 BLOCK DIAGRAM ................................................................................................. 5 PIN ASSIGNMENTS ............................................................................................. 6 PIN DESCRIPTIONS.............................................................................................. 7 ABSOLUTE MAXIMUM RATINGS ........................................................................ 8 RECOMMENDED OPERATION RATINGS ........................................................... 8 DC CHARACTERISTICS ....................................................................................... 9 AC CHARACTERISTICS ..................................................................................... 10 AC TIMING DIAGRAM ......................................................................................... 11 OPERATION DESCRIPTION............................................................................... 12
OPERATION METHOD .........................................................................................................12 OUTPUT PIN.........................................................................................................................12 VOLTAGE BIASING ..............................................................................................................13 RECOMMENDED TIMING ....................................................................................................14
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S6C0657
263 / 256 CHANNEL TFT-LCD GATE DRIVER
INTRODUCTION
The S6C0657 is a TFT-LCD gate driver having 263 / 256 outputs. It can drive TFT panel gate ON voltage up to 38 V. It can operate within the logic voltage 2.7 to 5.5 V.
FEATURES
* * * * * 263 / 256 outputs Maximum TFT panel gate ON voltage = 38 V Bi - directional shift register Logic supply voltage = 2.7 to 5.5 V COF (Chip On Film) available
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263 / 256 CHANNEL TFT-LCD GATE DRIVER
S6C0657
BLOCK DIAGRAM
VDD VLO VOFF
SEL U/D CPV
DI/O
S/R 001
S/R 002
263 Shift Register
S/R 262
S/R 263
DO/I
OE
Level Shifter
VGG VOFF
263 Ouput Buffer
G001 G002
G262 G263
Figure 1. Block Diagram
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S6C0657
263 / 256 CHANNEL TFT-LCD GATE DRIVER
PIN ASSIGNMENTS
G263 G262 G261 G260 VGG VOFF DMY1 DMY2 DMY3 DMY4 DOI VDD U/D VLO CPV OE CPV VLO SEL VDD DIO DMY4 DMY3 DMY2 G004 G003 G002 G001 DMY1 VOFF VGG
Figure 2. Pin Assignments
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S6C0657 (Top View)
263 / 256 CHANNEL TFT-LCD GATE DRIVER
S6C0657
PIN DESCRIPTIONS
Symbol Pin Name I/O Description
DI/O DO/I
Start pulse input/output
When these inputs operate as the input, the start pulse data is read at the rising edge of shift clock, CPV. When these inputs operate as the output, the start pulse output is the next chip's start pulse input. The output pulse is generated I/O at the falling edge of the 263th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left shifting operation. (Input = DO/I and output = DI/O) I I When U/D = H, DI/O G001 ...... G263 DO/I When U/D = L, DO/I G263 ...... G001 DI/O The shift register operates in synchronization with the rising edge of this input This input selects the number of available outputs When SEL = H, 263 output mode When SEL = L, 256 output mode(G129 - G135 are disabled) This input controls the state of the driver outputs. When OE = H, the driver output is fixed to VOFF. When OE = L, the driver output is VGG or VOFF corresponding to the data. The output signals change in synchronization with the rising edge of shift clock input, CPV. The amplitude of the driver output is VGG - VOFF. This input is logic and driver ground. Always, has negative potential. This input operates as the reference to the level conversion of the other input. The other logic input range: VDD - VLO 6 to 33 V The TFT gate ON voltage is VGG - VOFF. 2.7 to 5.5 V
U/D CPV SEL
Shift direction control input Shift clock input
Output selection input
I
OE
Output enable input
I
G001 to G263 VOFF
Driver output
O
Negative power supply
I
VLO
Logic input low voltage
I
VGG VDD
Driver positive power supply Logic positive power supply
I I
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S6C0657
263 / 256 CHANNEL TFT-LCD GATE DRIVER
ABSOLUTE MAXIMUM RATINGS (VOFF = 0 V)
Table 1. Absolute Maximum Ratings Parameter Logic positive power supply Driver positive power supply Logic input low voltage Input voltage Operation temperature Storage temperature Symbol VDD VGG VLO VIN Top Tstg Ratings - 0.3 to 21.0 - 0.3 to 42.0 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 20 to 75 - 55 to 150 Unit V V V V C C
CAUTIONS If the absolute maximum rating is exceeded momentarily, the quality of this product may be degraded. It is desirable to use this product within the range of the absolute maximum ratings. The power supplying order is as follows. ON: VLO VDD VOFF Control Input VGG OFF: VGG Control Input VOFF VDD VLO
RECOMMENDED OPERATION RATINGS (VLO = 0 V)
Table 2. Recommended Operation Ratings Parameter Logic positive power supply Driver positive power supply Negative power supply Power supply voltage Operation frequency Output load Symbol VDD VGG VOFF VGG - VOFF fCPV CL Min. 2.7 6 - 15 21 Typ. Max. 5.5 33 -5 38 100 1000 Unit V V V V kHz pF
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263 / 256 CHANNEL TFT-LCD GATE DRIVER
S6C0657
DC CHARACTERISTICS (VLO = 0V)
Table 3. DC Characteristics (Ta = - 20 to 75 C, VGG - VOFF = 21 to 38 V, VLO - VOFF = 15 to 5 V, VDD - VLO = 2.7 to 5.5 V) Parameter High input voltage Low input voltage High output voltage Low output voltage LCD driver output ON resistance High output current Low output current Input leak current Symbol VIH VIL VOH VOL ROH ROL IGG IDD ILK VX = VDD - VLO IOH = - 40 A IOL = 40 A VOUT = VGG - 0.5 V, VGG = 38 V, VOFF = 0 V VOUT = 0.5 V, VGG = 38 V, VOFF = 0 V Without output load VDD - VOFF = 3.3 V VDD - VOFF = 19 V Condition Min. VLO + 0.9VX VOFF VDD - 0.4 VOFF -5 Max. VDD VLO + 0.1VX VDD VOFF + 0.4 500 500 400 400 1000 5 Unit V
(1)
Pin used
V V V A A A A G001 to G263 G001 to G263 VGG
(1) (3) (1) (2)
NOTES: 1. DI/O, DO/I, CPV, OE, U/D, SEL used. 2. When U/D = H, DO/I used, and when U/D = L, DI/O used. 3. Input swing voltage = VDD to VDD - 3.3 V
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S6C0657
263 / 256 CHANNEL TFT-LCD GATE DRIVER
AC CHARACTERISTICS (VLO = 0 V)
Table 4. AC Characteristics (Ta = - 20 to 75 C, VGG - VOFF = 21 to 38 V, VLO - VOFF = 15 to 5 V, VDD - VLO = 2.7 to 5.5 V) Parameter Clock period Clock pulse width Output enable input width Data setup time Data hold time Output delay time (1) Output delay time (2) Output delay time (3) Symbol tCPV tCPVH, tCPVL twOE tsDI thDI tpdDO tpdG tpdOE Condition Duty = 50 % CL = 30 pF CL = 300 pF Min. 10 4 0.8 0.8 0.8 Max. 0.8 0.8 0.8 s Unit
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tCPVH tCPV 50 % tCPVL tsDI 50 % tpdG 50 % thDI 50 % 50 % 50 %
AC TIMING DIAGRAM
CPV
50 %
263 / 256 CHANNEL TFT-LCD GATE DRIVER
DI/O (U/D=H) DO/I (U/D=L)
G1 (U/D=H) G263 (U/D=L)
50 % tpdOE twOE 50 % 50 % 50 %
OE
tpdOE 50 %
Figure 3. AC Timing Diagram
tpdDO 50 %
G2 to G262
G263 (U/D=H) G1 (U/D=L)
tpdDO
DO/I (U/D=H) DI/O (U/D=L)
50 %
S6C0657
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S6C0657
263 / 256 CHANNEL TFT-LCD GATE DRIVER
OPERATION DESCRIPTION
OPERATION METHOD
The start pulse input, DI/O (when U/D is "H") or DO/I (when U/D = "L"), is synchronized with the rising edge of CPV and stored in the first shift register. While stored pulse is transferred to the next register at the next rising edge of CPV, a new pulse is stored simultaneously. Output pin (G1 to G263) supplies VGG voltage or VOFF voltage to the TFT-LCD panel depending on the pulse of the shift register. The start pulse output, DO/I (when U/D is "H") or DI/O (when U/D = "L"), is synchronized with the falling edge of CPV and the pulse of the last register (G1 or G263) is transferred to the next IC. The voltage level of the start pulse output is VDD with "H" data, VOFF with "L" data The relationship between U/D and shift data input / out pin is as follows: Table 5. The Relationship between U/D and the Start Pulse Input / Output Mode 263 output 256 output U/D state "H" "L" "H" "L" Shift data Input DI/O DO/I DI/O DO/I Output DO/I DI/O DO/I DI/O Data transfer direction G1 G2 G3 G4 G5 ...... G263 G263 G262 G261 G260 ...... G1 G1 G2 ...... G128 G136 ...... G262 G263 G263 G262 ...... G136 G128 ...... G2 G1 Output level OE = L Normal (VGG / VOFF) OE = H Disable (VOFF)
OUTPUT PIN (G1 TO G263)
If the data of the shift register to an output drive pin is "H", the voltage level of the output is VGG and if the data is "L", the level of the output is VOFF. But, when OE is "H", the voltage level of the output is VOFF irrespective of the data of the shift register.
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263 / 256 CHANNEL TFT-LCD GATE DRIVER
S6C0657
VOLTAGE BIASING
The driver negative power supply, VOFF, can be any value between VLO - 5V and VLO - 15V.
G1 to G263 VGG (31 V)
Input signal VDD (3.0V)
Logic Output
VLO (0 V)
VOFF (-7 V)
Figure 4. Example of Voltage Biasing
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S6C0657
263 / 256 CHANNEL TFT-LCD GATE DRIVER
RECOMMENDED TIMING
- 263 Output mode (When SEL = "H") When U/D = "H" Input DI/O CPV OE G1 G2 G3 G4 G263 Output DO/I VGG VDD VOFF VOFF
When U/D = "L" Input DO/I CPV OE G263 G262 G261 G260 G1 Output DI/O VGG VDD VOFF VOFF
Figure 5. Recommended Timing
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263 / 256 CHANNEL TFT-LCD GATE DRIVER
S6C0657
- 256 Output mode (When SEL = "L") When U/D = "H" Input DI/O CPV OE G1 G2 G3 G4 G129 to G135 G263 Output DO/I VGG VDD VOFF VOFF VOFF
When U/D = "L" Input DO/I CPV OE G263 G262 G261 G260 G135 to G129 G1 Output DI/O VGG VDD VOFF VOFF VOFF
Figure 5. Recommended Timing (Continued)
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