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LOW POWER DTMF RECEIVER
S5T3170
INTRODUCTION
The S5T3170 is a complete Dual Tone Multiple Frequency (DTMF) receiver that is fabricated by low power CMOS and the SwitchedCapacitor Filter technology. This LSI consists of band split filters, which separates counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. It decodes all 16 DTMF tone pairs into a 4bits digital code. The externally required components are minimized by on chip provision of a differential input AMP, clock oscillator and latched three state interface. The on chip clock generator requires only a low cost TV crystal as an external component.
18-DIP-300A
20-SOP-375
FEATURES
* * * * * * * Detects all 16 standard tones. Low power consumption: 15mW (Typ) Single power supply: 5V Uses inexpensive 3.58MHz crystal Three state outputs for microprocessor interface Good quality and performance for using in exchange system Power down mode/input inhibit
ORDERING INFORMATION
Device S5T3170X01-D0B0 S5T3170X01-S0B0 Package 18-DIP-300A 20-SOP-375 Operating - 25C -- + 75C
APPLICATIONS
* * * * * PABX Central Office Paging Systems Remote Control Credit Card Systems * * * * * Key Phone System Answering Phone Home Automation System Mobile Radio Remote Data Entry
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S5T3170
LOW POWER DTMF RECEIVER
PIN CONFIGURATION
IN+
1 2 3 4 5 6 7 8 9 S5T3170
18 17 16 15 14 13 12 11 10
VDD
IN+
1 2 3 4 5 6 7 8 9 10
(20-SOP)
20 19 18 17 S5T3170 16 15 14 13 12 11
VDD
IN-
SI/GTO
IN-
SI/GTO
GS
ESO
GS
ESO
VREF
DSO
VREF
DSO
IIN
Q4
IIN
NC
PDN
Q3
PDN
Q4
OSC1
Q2
NC
Q3
OSC2
Q1
OSC1
Q2
GND
OE
OSC2
Q1
GND (18-DIP)
OE
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 Symbol IN + IN - GS VREF IIN PDN Description Non inverting input of the internal amp. Inverting input of the internal amp. Gain Select. The output used for gain adjustment of analog input signal with a feedback resistor. Reference Voltage output (VDD/2, Typ) can be used to bias the internal amp input of VDD/2. Input inhibit. High input states inhibits the detection of tones. This pin is pulled down internally. Control input for the stand-by power down mode. Power down occurs when the signal on this input is in high states. This pin is pulled down internally.
2
LOW POWER DTMF RECEIVER
S5T3170
PIN DESCRIPTION (Continued)
Pin No 7, 8 Symbol OSC1 OSC2 GND OE Description Clock input/output. A inexpensive 3.579545MHz crystal connected between these pins completes internal oscillator. Also, external clock can be used. Ground pin. Output Enable input. Outputs Q1-Q4 are CMOS push-pull when OE is High and open circuited (High impedance) when disabled by pulling OE low. Internal pull up resistor built in. Three state data output. When enabled by OE, these digital outputs provide the hexadecimal code corresponding to the last valid tone pair received. Delayed Steering Output. Indicates that valid frequencies have been present for the required guard time, thus constituting a valid signal. Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on SI/GTO falls below VTH. Early Steering Outputs. Indicates detection of valid tone output a logic high immediately when the digital algorithm detects a recognizable tone pair. Any momentary loss of signal condition will cause ESO to return to low. Steering Input/Guard Time Output. A voltage greater the VTS detected at SI causes the device to register the detected tone pair and update the output latch. A voltage less than VTS frees the device to accept a new tone pair. The GTO output acts to reset the external steering time constant, and its state is a function of ESO and the voltage on SI Power Supply (+5V, Typ)
9 10
11 - 14
Q1 - Q4
15
DSO
16
ESO
17
SI/GTO
18
VDD
ABSOLUTE MAXIMUM RATINGS
Characteristics Power Supply Voltage Analog Input Voltage Range Digital Input Voltage Range Output Voltage Range Current On Any Pin Operating Temperature Storage Temperature Symbol VDD VI (A) VI (D) VO II TOPR TSTG Value 6 - 0.3 -- V + 0.3 DD - 0.3 -- V + 0.3 DD - 0.3 -- V + 0.3 DD 10 - 40 -- + 85 - 60 -- + 150 Unit V V V V V mA C
3
S5T3170
LOW POWER DTMF RECEIVER
ELECTRICAL CHARACTERISTICS
(VDD = 5V, Ta = 25C, unless otherwise noted) Characteristic Operating Voltage Operating Current Power Dissipation Input Voltage Low Input Voltage High Input Leakage Current Pull Up Current On OE Pin Analog Input Impedance Steering Input Threshold Voltage Output Voltage Low Symbol VDD IDD PD VIL VIH II (LKG) IPU RI VTH VOL VOH Output Current (Sinking) Output Current (Sourcing) VREF Output Voltage VREF Output Resistance Analog Input Offset Voltage Power Supply Rejection Ratio Common Mode Rejection Ratio Open Loop Voltage Gain Open Loop Unit Gain Bandwidth Analog Output Voltage Swing Acceptable Capacitive Load Acceptable Resistive Load Analog Input Common Mode Voltage Range Valid Input Signal Range (each tone of composite signal) Dual Tone Twist Accept Acceptable Frequency Deviation Frequency Deviation Reject IO (SINK) No Load No Load VOL = 0.4V - - - Gain Setting Amp at 1KHz - 3.0V < VIN < 3.0V Gain Setting Amp at 1KHz - RL = 100K GS GS No Load - - - - Test Conditions - - - - - VIN = GND or VDD OE = GND fIN = 1KHz - Min. 4.75 - - - 3.5 - - 8 2.2 - 4.97 1 0.4 2.4 - - - - - - - - - - -29 - - 3.5% Typ. - 3.0 15 - - 0.1 7.5 10 - - - 2.5 0.8 - 10 25 60 60 65 1.5 4.5 100 50 3.0 - 10 - - Max. 5.25 9.0 45 1.5 - - 15 - 2.5 0.03 - - - 2.8 - - - - - - - - - - 1.0 - 1.5% 2Hz - Unit V mA mW V V m A M V V V mA mA V K mV dB dB dB MHz VP-P pF K VP-P dBm dB - -
IO (SOURCE) VOH = 4.6V VO (REF) RO (REF) VIO PSRR CMRR GV BW VO (P-P) CL RL VCM VI(VAL) TW f fR
4
LOW POWER DTMF RECEIVER
S5T3170
ELECTRICAL CHARACTERISTICS (Continued)
(VDD = 5V, Ta = 25C, unless otherwise noted) Characteristic Third Tone Tolerance Noise Tolerance Dial Tone Tolerance Crystal Clock Frequency Maximum Clock Input Rise Time Maximum Clock Input Fall Time Acceptable Clock Input Duty Cycle Acceptable Capacitive Load Tone Present Detect Time Tone Absent Detect Time Minimum Tone Duration Accept Minimum Tone Duration Reject Acceptable Interdigit Pause Rejectable Interdigit Pause Propagation Delay Time SI to Q Propagation Delay Time SI to DSO Output Data Setup Q to DSO Propagation Delay Time OE to Q (Enable) Propagation Delay Time OE to Q (Disable) Symbol T3rd TN DT fCK tR(MAX) tF(MAX) DCK DL tDET(P) tDET(A) tTDA(MIN) tTDR(MAX) tIDP(A) tIDP(R) tD(SI-Q) tD(SI-D) tSU tD(QE-Q)EN tD(QE-Q)DIS Test Conditions - - - - External Clock External Clock External Clock OSC2 PIN - - User Adjustable User Adjustable User Adjustable User Adjustable OE = High OE = High OE = High RL = 10K, CL = 50pF RL = 10K, CL = 50pF Min. -25 - 18 - - 40 - 5 0.5 - 20 - 20 - - - - - Typ. -16 -12 22 - - 50 - 11 4 - - - - 8 12 3.4 50 300 Max. - - - 110 110 60 30 14 8.5 40 - 40 - 11 16 - 60 - Unit dB dB dB MHz nS nS % pF mS mS mS mS mS mS S S S nS nS
3.5759 3.5795 3.5831
NOTES: 1. Digit sequence consists of all 16 DTMF tones. 2. Tone duration = 40mS, Tone pause = 40mS. 3. Nominal DTMF frequencies are used. 4. Both tones in the composite signal have an equal amplitude. 5. Tone pair is deviated by 1.5% 2Hz. 6. Bandwidth limited (3KHz) Gaussian Noise. 7. The precise dial tone frequencies are (350Hz and 440Hz) 2%. 8. For an error rate of better than 1 in 10000. 9. Referenced to lowest level frequency component in DTMF signal. 10. Minimum signal acceptance level is measured with specified maximum frequency deviation. 11. This item also applies to a third tone injected onto the power supply. 12. Referenced to Fig. 1 Input DTMF tone level at -28dBm.
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LOW POWER DTMF RECEIVER
VCC 1 1 2 100K 3 R2 16 17
300K LED
VCC VCC
VCC
18
R3 C1
18 17 16 4 R1 5 0.1F 6 7 8 100K
1 1 2 14 2 13
b c
VCC 16 f 15 R10
10 g
9
87
6
f com a b
2 3 4 5 6 12 11 10 VCC X - tal 1
X - tal 2
KT3170 S5T3170
HL74HCTLS02
15 3 14 13 5 12 6 11 7 4
3 12 4 11 5 10 6 9 7 8
LT
g
14
KS58006 S5T5820C
R8 ABI d 12 R7 c d 11 10 R5 R6
14 13
8 9
a d com c dp 9 10 8 GND 9 R4
12
3
45
VCC
1 4 7 5 8
2
3 6 9
*
0
#
Fig. 2
TEST CIRCUIT
S5T3170
Figure 1. Test Circuit
15
HL74LS47
RDO
a
13
7
LTS542R
R9
6
LOW POWER DTMF RECEIVER
S5T3170
TIMING DIAGRAM
tTDR (MAX)
tTDA (MIN)
tIDP (A)
tIDP (R)
DTMF #n DTMF INPUT
DTMF #n + 1
DTMF #n + 1
tDET (P)
tDET (A)
ESO
tPGT
tAGT
VTH
SI/GTO
tSU
DECODED TONE # (n - 1) Q1 - Q4
tD (SI-D)
DSO
tD (OE-Q) EN
OE
tD (OE-Q) DIS
Figure 2. Timing Diagram
7
S5T3170
LOW POWER DTMF RECEIVER
DIGITAL OUTPUT
Outputs Q1-Q4 are CMOS push pull when enabled (EO = High) and open circuited (high impedance) when disabled by pulling EO = Low. These digital outputs provide the hexadecimal code corresponding to the DTMF signals. The table below describes the hexadecimal. NO 1 2 3 4 5 6 7 8 9 0 * # A B C D ANY
NOTE: Z : High Impedance H : High Logic Level L : Low Logic Level
Low Frequency 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 -
High Frequency 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 -
OE H H H H H H H H H H H H H H H H L
Q4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Z
Q3 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Z
Q2 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Z
Q1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z
8
LOW POWER DTMF RECEIVER
S5T3170
APPLICATION CIRCUIT
+5V IN+ 0.1uF 100K IN100K SI/GTO 300K 10nF C1 100K R1 INGS IIN Q4 10nF C2 100K R2 R3 37.5K R2 60K R5 100K VREF IN+ VDD
GS
ESO
0.1uF
1 2 3 4
+ _
VREF
DSO
PDN 3.58MHz OSC1
Q3
S5T3170
Q2
OSC2
Q1
GND
OE
All resistors are 1% tolerance All capacitors are 5% tolerance Figure 3. Single Ended Input Configuration
R3 = R2R5/(R2+R5), VOLTAGE GAIN = R5/R1 INPUT IMPEDANCE :2 R1 + (1/wC)2 All resistors are 1% tolerance All resistors are 1% tolerance All capacitors are 5% tolerance Figure 4. Differential Ended Input Configuration
2
9
S5T3170
LOW POWER DTMF RECEIVER
VDD
C
C
SI/GTO
SI/GTO
R1 R2 ESO ESO
R1 R2
tPGT = (R1C) In (VDD/VDD-VTH) tAGT = (RPC) In (VDD/VTST) R P = R1R2/(R1 + R2) Decreasing tAGT (tPGT > tAGT)
tPGT = (RPC) In (VDD/VDD-VTH) tAGT = (R1C) In (VDD/VTH) RP = R1R2 (R1 + R2) Decreasing tPGT (tPGT< tAGT)
Figure 5. Guard Time Adjustment
S5T3170
S5T3170
30pF OSC1 3.579545MHz OSC2 OSC2 OSC1
TO OSC1 of next S5T3170
Figure 6. Oscillator Connection
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