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RLP1N06CLE
Data Sheet July 1999 File Number
2839.4
1A, 55V, 0.750 Ohm,Voltage Clamping, Current Limited, N-Channel Power MOSFET
The RLP1N06CLE is an intelligent monolithic power circuit which incorporates a lateral bipolar transistor, resistors, zener diodes, and a PowerMOS transistor. The current limiting of this device allows it to be used safely in circuits where it is anticipated that a shorted load condition may be encountered. The drain to source voltage clamping offers precision control of the circuit voltage when switching inductive loads. Logic level gates allow this device to be fully biased on with only 5V from gate to source. Input protection is provided for ESD up to 2kV. Formerly developmental type TA09880.
Features
* 1A, 55V * rDS(ON) = 0.750 * ILIMIT at 150oC = 1.1A to 1.5A Maximum * Built-in Voltage Clamp * Built-in Current Limiting * ESD Protected, 2kV Minimum * Controlled Switching Limits EMI and RFI * 175oC Rated Junction Temperature * Logic Level Gate * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RLP1N06CLE PACKAGE TO-220AB BRAND L1N06CLE
Symbol
D
NOTE: When ordering, use the entire part number.
G
S
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE)
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RLP1N06CLE
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RLP1N06CLE 55 55 2 Self Limited 5.5 36 0.24 -55 to 175 300 260 UNITS V V kV V W W/oC oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain to Gate Voltage (RGS = 20k, Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Electrostatic Voltage at TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Gate to Source Voltage (Reverse Voltage Gate Bias Not Allowed) . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Power Dissipation Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) IDS(LIM) t(ON) td(ON) tr td(OFF) tf t(OFF) RJC RJA ESD TO-220AA Human Model (100pF, 1.5k) MIL-STD-883B (Category B2) TEST CONDITIONS ID = 20mA, VGS = 0V (Figure 7) VGS = VDS, ID = 250A (Figure 8) VDS = 45V, VGS = 0V VGS = 5V ID = 1A, VGS = 5V (Figure 6) VDS = 15V, VGS = 5V (Figure 2) TC = 25oC TC = 150oC TC = 25oC TC = 150oC TC = 25oC TC = 150oC TC = 25oC TC = 150oC MIN 55 1 1.8 0.9 1 1 2000 TYP MAX 70 2.5 5 20 5 20 0.750 1.500 3 1.5 6.5 1.5 5 7.5 5 12.5 4.17 62 UNITS V V A A A A A A s s s s s s
oC/W oC/W
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
Limiting Current
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Electrostatic Voltage
VDD = 30V, ID = 1A, VGS = 5V, RGS = 25 RL = 30
V
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage (Note 2) Reverse Recovery Time NOTES: 2. Pulsed: pulse duration = 80s maximum, duty cycle = 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. SYMBOL VSD trr ISD = 1A ISD = 1A TEST CONDITIONS MIN TYP MAX 1.5 1 UNITS V ms
6-429
RLP1N06CLE Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 NORMALIZED DRAIN CURRENT
Unless Otherwise Specified
2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS = 10V, VGS = 5V 1.5
1.0
0.5
0 -50
-25
0
25 50 75 100 125 TC, CASE TEMPERATURE (oC)
150
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. NORMALIZED CURRENT LIMIT vs CASE TEMPERATURE
10 IDS, DRAIN TO SOURCE CURRENT (A) OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
IDS, DRAIN TO SOURCE CURRENT (A)
TJ = MAX RATED TC = 25oC 100s 1ms
2.5
VGS = 7V
2.0 VGS = 6V VGS = 5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 4V
1.5
1 OPERATION IN THIS AREA LIMITED BY IDS(LIM) 10ms DC
1.0
0.5
VGS = 3V
VDSS MAX = 55V 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100
0
0
1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V)
5
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. SATURATION CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
3.0 VDS >> IDS x rDS(ON) PULSE DURATION = 80s 2.5 DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 0.5 0 -25oC NORMALIZED DRAIN TO SOURCE ON RESISTANCE
3.0 VGS = 5V, ID = 0.5A PULSE DURATION = 80s 2.5 DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 0.5 0 -50
25oC
150oC
0
1
2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V)
6
-25
0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (oC)
150
175
FIGURE 5. TRANSFER CHARACTERISTICS
FIGURE 6. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
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RLP1N06CLE Typical Performance Curves
NORMALIZED GATE THRESHOLD VOLTAGE 2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS ID = 250A 1.6
Unless Otherwise Specified (Continued)
2.0 ID = 20mA
1.5
1.2
1.0
0.8
0.5
0.4
0 -50
-25
0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (oC)
150
175
0 -50
-25
0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (oC)
150
175
FIGURE 7. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
300 250 C, CAPACITANCE (pF) 200 COSS 150 100 50 CRSS 0 0 5 15 20 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 25 0V RGS DUT VGS VGS VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
RL VDS
+
CISS
FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 10. SWITCHING TEST CIRCUIT
25 VDS, DRAIN TO SOURCE VOLTAGE (V) HSTR = 0oC/W 20 1oC/W 15 2oC/W 5oC/W 10oC/W 5 25oC/W
VDS, DRAIN TO SOURCE VOLTAGE (V)
TJ = 175oC ILIM = 1.35A RJC = 4.17oC/W
80 DUTY CYCLE = 20% 60 10% 5% 2%
FREE AIR RJA = 80oC/W
40 50% 20 MAX PULSE WIDTH = 100ms TJ = 175oC, ILIM = 1.35A, RJC = 4.17oC/W 0 25 50 75 100 125 150 175 TA, AMBIENT TEMPERATURE (oC)
10
0 25
50
75
100
125
150
175
TA, AMBIENT TEMPERATURE (oC)
NOTE: Heatsink thermal resistance = 2oC/W FIGURE 11. DC OPERATION IN CURRENT LIMITING FIGURE 12. MAXIMUM VDS vs TA IN CURRENT LIMITING
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RLP1N06CLE Typical Performance Curves
80 VDS, DRAIN TO SOURCE VOLTAGE (V) TJ = 175oC ILIM = 1.35A RJC = 4.17oC/W
Unless Otherwise Specified (Continued)
80 VDS, DRAIN TO SOURCE VOLTAGE (V)
TJ = 175oC ILIM = 1.35A RJC = 4.17oC/W
60 DUTY CYCLE = 20% 40 10% 5% 2%
60
40 DUTY CYCLE = 20% 20 50% MAX PULSE WIDTH = 100ms 0 25 50 75 100 125 150 175 TA, AMBIENT TEMPERATURE (oC) 10% 5% 2%
20 50% MAX PULSE WIDTH = 100ms 0 25 50 75 100 125 150 175 TA, AMBIENT TEMPERATURE (oC)
NOTE: Heatsink thermal resistance = 5oC/W FIGURE 13. MAXIMUM VDS vs TA IN CURRENT LIMITING
80 VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Heatsink thermal resistance = 10oC/W FIGURE 14. MAXIMUM VDS vs TA IN CURRENT LIMITING
80 VDS, DRAIN TO SOURCE VOLTAGE (V)
60
MAX PULSE WIDTH = 100ms TJ = 175oC ILIM = 1.35A RJC = 4.17oC/W 5% 2% 1%
60 2% 40
MAX PULSE WIDTH = 100ms TJ = 175oC ILIM = 1.35A RJA = 80oC/W DUTY CYCLE = 1%
40 10%
5% 20 10% 50% 0 25 50 75 100 125 150 175 TA, AMBIENT TEMPERATURE (oC)
20 DUTY CYCLE = 20% 50% 0 25 50 75 100 125 150 175
TA, AMBIENT TEMPERATURE (oC)
NOTE: Heatsink thermal resistance = 25oC/W FIGURE 15. MAXIMUM VDS vs TA IN CURRENT LIMITING
10 RJC =
NOTE: No external heatsink FIGURE 16. MAXIMUM VDS vs TA IN CURRENT LIMITING
10 RJC =
4.17oC/W 8 TIME TO 175oC (s)
4.17oC/W STARTING 125oC 100oC 75oC 50oC TEMP = 25oC
8 TIME TO 175oC (s) 150oC 6 125oC 100oC 75oC STARTING 50oC TEMP = 25oC
150oC 6
4
4
2
2
0
0
5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V)
25
0
0
5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V)
25
NOTE: Heatsink thermal resistance = 2oC/W Heatsink thermal capacitance = 4j/oC FIGURE 17. TIME TO 175oC IN CURRENT LIMITING
NOTE: Heatsink thermal resistance = 5oC/W Heatsink thermal capacitance = 2j/oC FIGURE 18. TIME TO 175oC IN CURRENT LIMITING
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RLP1N06CLE Typical Performance Curves
10
Unless Otherwise Specified (Continued)
RJC = 10 RJC =
4.17oC/W 8
4.17oC/W
8 TIME TO 175oC (s) 150oC 6 125oC 4 75oC STARTING TEMP = 25oC 100oC 50oC TIME TO 175oC (s)
6
4 150oC 2
125oC
75oC 100oC
STARTING TEMP = 25oC 50oC
2
0
0
5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V)
25
0
0
5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V)
25
NOTE: Heatsink thermal resistance = 10oC/W Heatsink thermal capacitance = 1j/oC FIGURE 19. TIME TO 175oC IN CURRENT LIMITING
10
NOTE: Heatsink thermal resistance = 25oC/W Heatsink thermal capacitance = 0.5j/oC FIGURE 20. TIME TO 175oC IN CURRENT LIMITING
RJA =
80oC/W 8 TIME TO 175oC (s)
6
4
2
125oC 150oC
75oC 100oC
STARTING TEMP = 25oC 25
0
0
5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: No external heatsink FIGURE 21. TIME TO 175oC IN CURRENT LIMITING
Detailed Description
Temperature Dependence of Current Limiting and Switching Speed
The RLP1N06CLE is a monolithic power device which incorporates a logic level PowerMOS transistor with a resistor in series with the source. The base and emitter of a lateral bipolar transistor is connected across this resistor, and the collector of the bipolar transistor is connected to the gate of the PowerMOS transistor. When the voltage across the resistor reaches the value required to forward bias the emitter base junction of the bipolar transistor, the bipolar transistor "turns on". A series resistor is incorporated in series with the gate of the PowerMOS transistor allowing the bipolar transistor to drive the gate of the PowerMOS transistors to a voltage which just maintains a constant current in the PowerMOS transistor. Since both the resistance of the resistor
in series with the PowerMOS transistor source and voltage required to forward bias the base emitter junction of the bipolar transistor vary with the temperature, the current at which the device limits is a function of temperature. This dependence is shown in figure 2. The resistor in series with the gate of the PowerMOS transistor results in much slower switching than in most PowerMOS transistors. This is an advantage where fast switching can cause EMI or RFI. The switching speed is very predictable, and a minimum as well as maximum fall time is given in the device characteristics for this type.
DC Operation of the RLP1N06CLE
The limit of the drain to source voltage for operation in current limiting on a steady state (DC) basis is shown as Figure 11. The dissipation in the device is simply the applied drain to source voltage multiplied by the limiting current. This
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RLP1N06CLE
device, like most Power MOSFET devices today, is limited to 175oC. The maximum voltage allowable can, therefore be expressed as:
( 175 C - T AMBIENT ) V DS = ---------------------------------------------------------I LIM x ( R JC + R CA )
o
Limited Time Operations of the RLP1N06CLE
Protection for a limited period of time is sufficient for many applications. As stated above the heat storage in the silicon chip can usually be ignored for computations of over 10 milliseconds and the thermal equivalent circuit reduces to a simple enough circuit to allow easy computation on the limiting conditions. The variation in limiting current with temperature complicates the calculation of junction temperature, but a simple straight line approximation of the variation is accurate enough to allow meaningful computations. The curves shown as figures 17 thru 21 give an accurate indication of how long the specified voltage can be applied to the device in the current limiting mode without exceeding the maximum specified 175oC junction temperature. In practice this tells you how long you have to alleviate the condition causing the current limiting to occur.
(EQ. 1)
Duty Cycle Operation of the RLP1N06CLE
In many applications either the drain to source voltage or the gate drive is not available 100% of the time. The copper header on which the RLP1N06CLE is mounted has a very large thermal storage capability, so for pulse widths of less than 100 milliseconds, the temperature of the header can be considered a constant case temperature calculated simply as:
T C = ( V DS x I D x D x R CA ) + T AMBIENT (EQ. 2)
Generally the heat storage capability of the silicon chip in a power transistor is ignored for duty cycle calculations. Making this assumption, limiting junction temperature to 175oC and using the TC calculated above, the expression for maximum VDS under duty cycle operation is:
175 - T C V DS = -----------------------------------------I LIM x D x R JC (EQ. 3)
These values are plotted as Figures 12 thru 16.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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