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4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM
HYB 314100BJ/BJL -50/-60/-70
Advanced Information
* * * *
4 194 304 words by 1-bit organization 0 to 70 C operating temperature Fast Page Mode Operation Performance: -50 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns
tRAC tCAC tAA tRC tPC
*
RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time
50 13 25 95 35
Single + 3.3 V ( 0.3 V ) supply with a built-in Vbb generator * Low power dissipation max. 252 mW active (-50 version) max. 216 mW active (-60 version) max. 198 mW active (-70 version) * Standby power dissipation: 7.2 mW max. standby (TTL) 3.6 mW max. standby (CMOS) 720 W max. standby (CMOS) for Low Power Version Output unlatched at cycle end allows two-dimensional chip selection * Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability * All inputs and outputs TTL-compatible * 1024 refresh cycles / 16 ms
*
1024 refresh cycles / 128 ms Low Power Version * Plastic Packages: P-SOJ-26/20-5 with 300 mil width
*
Semiconductor Group
1
4.96
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
The HYB 314100BJ/BJL is the new generation dynamic RAM organized as 4 194 304 words by 1-bit. The HYB 314100BJ/BJL utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514100BJ/BJL to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 3.3 V ( 0.3 V) power supply, direct interfacing with high performance logic device families. Ordering Information Type HYB 314100BJ-50 HYB 314100BJ-60 HYB 314100BJ-70 HYB 314100BJL-50 HYB 314100BJL-60 HYB 314100BJL-70 Ordering Code Q67100-Q2035 Q67100-Q2037 Q67100-Q2039 on request on request on request Package P-SOJ-26/20-5 P-SOJ-26/20-5 P-SOJ-26/20-5 P-SOJ-26/20-5 P-SOJ-26/20-5 P-SOJ-26/20-5 Descriptions 3.3 V DRAM (access time 50 ns) 3.3 V DRAM (access time 60 ns) 3.3 V DRAM (access time 70 ns) 3.3 V Low Power DRAM (access time 50 ns) 3.3 V Low Power DRAM (access time 60 ns) 3.3 V Low Power DRAM (access time 70 ns)
Semiconductor Group
2
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Pin Configuration (top view)
P-SOJ-26/20-5
Pin Names A0-A10 RAS CAS WE DI DO Address Input Row Address Strobe Column Address Strobe Read/Write Input Data In Data Out Power Supply (+ 3.3 V) Ground (0 V) No Connection
VCC VSS
N.C.
Semiconductor Group
3
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Block Diagram
Semiconductor Group
4
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 C Storage temperature range......................................................................................- 55 to + 150 C Input/output voltage ........................................................................... - 1 to + min (VCC + 0.5, 4.6) V Power Supply voltage .................................................................................................. - 1 to + 4.6 V Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics
TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V , tT = 5 ns
Parameter Input high voltage Input low voltage TTL Output high voltage (IOUT = - 2 mA) TTL Output low voltage (IOUT = 2 mA) CMOS Output high voltage (IOUT = - 100 A) CMOS Output low voltage (IOUT = 100 A) Input leakage current, any input (0 V < Vin < VCC + 0.3 V, all other input = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < VCC) Average VCC supply current -50 version -60 version -70 version Standby VCC supply current (RAS = CAS = WE = VIH) Average VCC supply current during RAS-only refresh cycles -50 version -60 version -70 version Average VCC supply current during fast page mode operation -50 version -60 version -70 version Standby VCC supply current (RAS = CAS = WE = VCC - 0.2 V) Symbol Limit Values min. max. 0.8 - 0.4 0.2 10 10 2.0 - 1.0 2.4 - - - 10 - 10 Unit Test Condition
1) 1) 1) 1)
VIH VIL VOH VOL VOH VOL II(L) IO(L) ICC1
VCC + 0.5 V
V V V V V A A mA
VCC - 0.2 -
1)
1)
2) 3)4)
_ - -
70 60 55 2 mA mA -
2)4)
ICC2 ICC3
-
_ - -
70 60 55 mA
2) 3)4)
ICC4
- - 50 45 40 1 200
ICC5
-
mA A
1)
L-version
Semiconductor Group
5
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
DC Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V , tT = 5 ns Parameter Average VCC supply current during CAS before RAS refresh mode -50 version -60 version -70 version For Low Power Version only: Battery backup current (average power supply current in battery backup mode): (CAS = CAS before RAS cycling or 0.2 V, WE = VCC - 0.2 V or 0.2 V, A0 to A10 = VCC - 0.2 V or 0.2 V; DI = VCC - 0.2 V or 0.2 V or open, tRC = 125 s, tRAS = tRAS min = 1 s) Symbol Limit Values min. max. Unit Test Condition mA - - - 70 60 55 250 A -
2)4)
ICC6
ICC7
-
Capacitance TA = 0 to 70 C; VCC = 3.3 V 0.3 V; f = 1 MHz Parameter Input capacitance (A0 to A10, DI) Input capacitance (RAS, CAS, WE) Output capacitance (DO) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
6
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
AC Characteristics 5)6) TA = 0 to 70 C, VCC = 3.3 V 0.3 V, tT = 5 ns Parameter Symbol -50 min. Limit Values -60 -70 max. max. min. max. min. Unit Note
Common Parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period Refresh period for L-version
tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF tREF
95 35 50 13 0 8 0 10 18 13 13 50 5 3 - -
- - 10k 10k - - - - 37 25
110 40 60 15 0 10 0 15 20 15 15 60
- - 10k 10k - - - - 45 30 - - - 50 16 128
130 50 70 20 0 10 0 15 20 15 20 70 5 3 - -
- - 10k 10k - - - - 50 35 - - - 50 16 128
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7
- 50 16 128
5 3 - -
Read Cycle
Access time from RAS Access time from CAS Access time from column address Column addr. to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z
tRAC tCAC tAA tRAL tRCS tRCH tRRH tCLZ
- - - 25 0 0 0 0
50 13 25 - - - - -
- - - 30 0 0 0 0
60 15 30 - - - - -
- - - 35 0 0 0 0
70 20 35 - - - - -
ns ns ns ns ns ns ns ns
8, 9 8, 9 8,10
11 11 8
Semiconductor Group
7
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
AC Characteristics (cont'd) 5)6)
TA = 0 to 70 C, VCC = 3.3 V 0.3 V, tT = 5 ns
Parameter Symbol -50 min. Output buffer turn-off delay Limit Values -60 0 15 0 -70 max. 20 ns 12 max. min. 13 max. min. Unit Note
tOFF
0
Write Cycle
Write command hold time Write command pulse width Write command setup time
tWCH tWP tWCS
8 8 0 13 13 0 10
- - - - - - -
10 10 0 15 15 0 10
- - - - - - -
10 10 0 20 20 0 15
- - - - - - -
ns ns ns ns ns ns ns 14 14 13
Write command to RAS lead time tRWL Write command to CAS lead time tCWL Data setup time Data hold time
tDS tDH
Read-Modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time
tRWC tRWD tCWD tAWD
115 50 13 25
- - - -
130 60 15 30
- - - -
155 70 20 35
- - - -
ns ns ns ns 13 13 13
Fast Page Mode Cycle
Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay
tPC tCP tCPA tRAS tRHCP
35 10 - 50 30
- - 30
40 10 -
- - 35
45 10 -
- - 40
ns ns ns 7
200 k 60 - 35
200 k 70 - 40
200 k ns - ns
Semiconductor Group
8
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C, VCC = 3.3 V 0.3 V, tT = 5 ns Parameter Symbol -50 min. Limit Values -60 -70 max. max. min. max. min. Unit Note
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle tPRWC time CAS precharge to WE 55 30 - - 60 35 - - 70 40 - - ns ns
tCPWD
CAS-before-RAS refresh cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS
tCSR tCHR tRPC tWRP tWRH
10 10 5 10 10
- - - - -
10 10 5 10 10
- - - - -
10 10 5 10 10
- - - - -
ns ns ns ns ns
CAS-before-RAS counter test cycle
CAS precharge time
tCPT
35
-
40
-
40
-
ns
Test Mode
Write command setup time Write command hold time
tWTS tWTH
10 10
- -
10 10
- -
10 10
- -
ns ns
Semiconductor Group
9
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at VOL = 0.8 and VOH = 2.0 V. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) defines the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.), the cycle is a read-write cycle and DO will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the DO pin (at access time) is indeterminate. 14)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles.
Semiconductor Group
10
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Read Cycle
Semiconductor Group
11
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Write Cycle (Early Write)
Semiconductor Group
12
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
13
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
14
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Fast Page Mode Read Cycle
Semiconductor Group
15
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Fast Page Mode Early Write Cycle
Semiconductor Group
16
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
RAS-Only Refresh Cycle
Semiconductor Group
17
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
CAS-Before-RAS Refresh Cycle
Semiconductor Group
18
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Hidden Refresh Cycle (Read)
Semiconductor Group
19
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Hidden Refresh Cycle (Early Write)
Semiconductor Group
20
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
21
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Test Mode Entry Test Mode The HYB314100BJ/BJL is organized 4 194 304 words by 1- bit but can internally be configured as 524 288 words by 8-bits. A WE, CAS-before-RAS cycle puts the device into Test Mode. In Test Mode, data is written into 8 sectors in parallel and retrieved the same way. If, upon reading, all bits are equal, the data output pin indicates a "1". If any of the bits differ, the data output pin indicates a "0". In Test Mode the 4M DRAM can be tested as if it were a 512K DRAM. Test Mode is exited by any refresh operation which is not a WE, CAS- before-RAS cycle. Addresses A10R, A10C and A0C do not care during Test Mode.
Semiconductor Group
22
HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM
Package Outlines Plastic Package P-SOJ-26/20-5 (Plastic Small Outline J-leaded Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 23
Dimensions in mm
GPJ05627

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