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TO 19 OTHER CHANNELS
V
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836
2.5V 20-Bit Universal Bus Driver with 3-State Outputs
Product Features
* PI74AVC+16836 is designed for low voltage operation, VCC = 1.65V to 3.6V * True 24mA Balanced Drive @ 3.3V * IOFF supports partial power-down operation * 3.6V I/O Tolerant inputs and outputs * Meets PC133 SDRAM Registered DIMM Specifications * All outputs contain a patented DDC (Dynamic Drive Control) circuit that reduces noise without degrading propagation delay * Industrial operation at -40C to +85C * Available Packages: - 56-pin 240 mil wide plastic TSSOP (A) - 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor's PI74AVC+ series of logic circuits are produced using the Company's advanced 0.35 micron CMOS technology, achieving industry leading speed. The 20-bit PI74AVC+16836 universal bus driver is designed for 1.65V to 3.6V Vcc operation. Data flow from A to Y is controlled by the Output Enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is LOW. When LE is HIGH, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is HIGH, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is HIGH, the outputs are in the highimpedance state, but all the inputs are enabled and data is capable of being stored in the register. To ensure the high-impedance state during power up or power down, OE should be tied to Vcc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Logic Block Diagram
1 OE 56
CLK
LE
29
A1
55 1D C1 CLK 2 Y1
1
PS8511A
02/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs
Product Pin Description
Pin Name OE LE CLK A Y GND Vcc De s cription Output Enable Input (Active LOW) Latch Enable (Active LOW) Clock Input Data Input Data Output Ground Power
Truth Table(1)
Inputs OE H L L L L L LE X L L H H H CLK X X X L or H A X L H L H X Z L H L H Yo( 2 ) Outputs Y
Pin Configuration
OE Y1 Y2 GND Y3 Y4 VCC Y5 Y6 Y7 GND Y8 Y9 Y10 Y11 Y12 Y13 GND Y14 Y15 Y16 VCC Y17 Y18 GND Y19 Y20 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44
56-Pin 43 A, K 42
CLK A1 A2 GND A3 A4 VCC A5 A6 A7 GND A8 A9 A10 A11 A12 A13 GND A14 A15 A16 VCC A17 A18 GND A19 A20 LE
Note: 1 H = High Signal Level L = Low Signal Level Z = High Impedance = Transition LOW-to-HIGH X = Irrelevant 2. Output level before the indicated steady-state input conditions were established.
41 40 39 38 37 36 35 34 33 32 31 30 29
2
PS8511A
02/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, VCC ............................................................................................ -0.5V to +4.6V Input voltage range, VI .................................................................................................... -0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ............................................................ -0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ........................................................................................ -0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ............................................................................ -50mA Output clamp current, IOK (VO <0) ...................................................................... -50mA Continuous output current, IO ...................................................................................................... 50mA Continuous current through each VCC or GND ................................................. 100mA Package thermal impedance, JA(3): package A .................................................... 64C/W package K ................................................... 48C/W Storage Temperature range, Tstg .............................................................................. -65C to 150C
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Notes: 1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions(1)
M in. Operating VCC Supply Voltage Data retention only VCC = 1.2V VIH High- level Input Voltage VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VCC = 1.2V VIL Low- level Input Voltage VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VI VO Input Voltage Active State Output Voltage 3- State VCC = 1.65V to 1.95V IOH High- level output current VCC = 2.3V to 2.7V VCC = 3V to 3.6V VCC = 1.65V to 1.95V IOL Low- level output current VCC = 2.3V to 2.7V VCC = 3V to 3.6V tv Input transition rise or fall rate TA Operating free- air temperature VCC = 1.65V to 3.6V -40 0 0 0 1.65 1.2 VCC 0.65 x VCC 1.7 2 Gnd 0.35 x VCC 0.7 0.8 3.6 VCC 3.6 -6 - 12 - 24 6 12 24 5 85 ns/V C mA V M ax. 3.6 Units
Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation.
3
PS8511A 02/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs
DC Electrical Characteristics (Over the Operating Range, TA = -40C +85C)
Parame te rs Te s t Conditions (1) IO H = -100A IO H = -6mA VIH = 1.07V VIH = 1.7V IO H = -12mA IO H = -24mA VIH = 2V IO L = 100A VIH = 0.57V IO L = 6mA VIH = 0.7V IO L = 12mA IO L = 24mA VIH = 0.8V VI = VC C or GND VI or VO = 3.6V VI = VC C or GND VO = VC C or GND IO = 0 VCC 1.65V to 3.6V 1.65V 2.3V 3V 1.65V to 3.6V 1.65V 2.3V 3V 3.6V 0 3.6V 3.6V 2.5V 3.3V 2.5V 3.3V 2.5V 3.3V M in. VC C -0.2V 1. 2 1.75 2.0 0.2 0.45 0.55 0.8 2.5 10 10 40 4 4 6 6 8 8 M ax. Units
VO H
V
VO L
II IO F F IO Z IC C
Control Inputs
A
Control Inputs CI Data Inputs CO Outputs VO = VC C or GND VI = VC C or GND
pF
Note: Typical values are measured at TA = 25C.
4
PS8511A
02/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs
Timing Requirements (Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
Vcc = 1.2V Vcc = 1.5V 0.1V Vcc = 1.8V 0.15V M in. M ax. 180 2.0 2.0 1.4 1. 4 1.4 1. 0 1. 0 1. 2 1.2 1. 2 1.2 1. 2 0.8 0.8 Vcc = 2.5V 0.2V M in. M a x. 18 0 1.0 1.0 1. 0 1.0 1.0 0.6 0.6 ns Vcc = 3.3V 0.3V M in. M a x. 18 0 Units MHz
M in. M ax. M in. M ax. fclock tw Pulse Duration Clock Frequency LE Low CLK High or Low Data before CLK tsu Setup Time Data before CLK High LE CLK Low Data after CLK th Hold Time Data after LE CLK High or Low
Switching Characteristics over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Parame te rs From (Input) To (Output) VCC = 1.2V VCC = 1.5V 0.1V M ax. VCC = 1.8V 0.15V M in. 180 A 1. 0 1. 0 Y 1. 0 1. 5 1. 5 4.5 5.0 4.5 5.5 5.0 M ax. VCC = 2.5V 0.2V M in. 180 0.8 0.8 0.8 1.0 1.0 3.0 3.3 3.0 4.5 4.5 M a x. VCC = 3.3V 0.3V M in. 180 0.7 0.7 0.7 1.0 1.0 2.4 2.5 2.5 4.0 4.0 ns M ax. MHz Units
M in. M ax. M in.
fmax
tpd
LE CLK
ten tdis
OE OE
Operating Characteristics, TA= 25C
Parame te rs Te s t Conditions Outputs Enabled Cpd Power Dissipation Capacitance Outputs Disabled VCC = 1.8V 0.1V Typical CL = 0pF, f = 10 MHz 48 25 VCC = 2.5V 0.2V Typical 50 28 VCC = 3.3V 0.3V Typical 55 pF 32 Units
5
PS8511A
02/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 1.2V AND 1.5V 0.1V
S1 2xVCC Open GND
From Output Under Test CL = 15pF
(See Note A)
2
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
2
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.1V tPHZ VCC/2 VOH -0.1V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
6
PS8511A
02/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 1.8V 0.15V
S1 2xVCC Open GND
From Output Under Test CL = 30 15pF
(See Note A)
1 k 2
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
2 k 1
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.1V 0.15V tPHZ VCC/2 VOH -0.1V 0.15V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having these characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
7
PS8511A
02/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 2.5V 0.2V
S1 2xVCC Open GND
From Output Under Test CL =30 15pF
(See Note A)
500 2
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
500 2
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.15V tPHZ VCC/2 VOH -0.15V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 3. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having these characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
8
PS8511A
02/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16836 2.5V 20-Bit Universal Bus Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 3.3V 0.3V
S1 2xVCC Open GND
From Output Under Test CL = 30 15pF
(See Note A)
500 2
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
500 2
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.1V 0.3V tPHZ VCC/2 VOH -0.1V 0.3V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having these characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
9
PS8511A 02/06/01

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