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Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated FEATURES * Repetitive Avalanche Rated * Fast switching * Stable off-state characteristics * High thermal cycling performance * Low thermal resistance PHB11N50E, PHW11N50E SYMBOL d QUICK REFERENCE DATA VDSS = 500 V g ID = 10.9 A RDS(ON) 0.55 s GENERAL DESCRIPTION N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies, T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications. The PHW11N50E is supplied in the SOT429 (TO247) conventional leaded package. The PHB11N50E is supplied in the SOT404 surface mounting package. PINNING PIN 1 2 3 tab DESCRIPTION gate drain1 source SOT404 tab SOT429 (TO247) 2 drain 1 3 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total dissipation Operating junction and storage temperature range CONDITIONS Tj = 25 C to 150C Tj = 25 C to 150C; RGS = 20 k Tmb = 25 C; VGS = 10 V Tmb = 100 C; VGS = 10 V Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 500 500 30 10.9 6.9 44 156 150 UNIT V V V A A A W C 1 It is not possible to make connection to pin 2 of the SOT404 package. December 1998 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS EAR IAS, IAR Non-repetitive avalanche energy CONDITIONS PHB11N50E, PHW11N50E MIN. - MAX. 707 18 10.9 UNIT mJ mJ A Unclamped inductive load, IAS = 10.9 A; tp = 0.2 ms; Tj prior to avalanche = 25C; VDD 50 V; RGS = 50 ; VGS = 10 V Repetitive avalanche energy2 IAR = 10.9 A; tp = 2.5 s; Tj prior to avalanche = 25C; RGS = 50 ; VGS = 10 V Repetitive and non-repetitive avalanche current THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78 package, in free air SOT429 package, in free air SOT404 package, pcb mounted, minimum footprint TYP. MAX. UNIT 60 45 50 0.8 K/W K/W K/W K/W ELECTRICAL CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL PARAMETER Drain-source breakdown voltage V(BR)DSS / Drain-source breakdown Tj voltage temperature coefficient Drain-source on resistance RDS(ON) VGS(TO) Gate threshold voltage gfs Forward transconductance Drain-source leakage current IDSS IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ld Ls Ciss Coss Crss V(BR)DSS CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA MIN. 500 2.0 4 TYP. MAX. UNIT 0.1 0.47 3.0 6.5 1 60 10 75 7 39 11 38 92 40 3.5 4.5 7.5 1326 182 96 0.55 4.0 25 500 200 100 12 55 V %/K V S A A nA nC nC nC ns ns ns ns nH nH nH pF pF pF VGS = 10 V; ID = 5.5 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 5.5 A VDS = 500 V; VGS = 0 V VDS = 400 V; VGS = 0 V; Tj = 125 C Gate-source leakage current VGS = 30 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 11 A; VDD = 400 V; VGS = 10 V VDD = 250 V; RD = 22 ; RG = 5.6 Measured from tab to centre of die Measured from drain lead to centre of die (SOT429 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz 2 pulse width and repetition rate limited by Tj max. December 1998 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHB11N50E, PHW11N50E SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Tmb = 25C Tmb = 25C IS = 11 A; VGS = 0 V IS = 11 A; VGS = 0 V; dI/dt = 100 A/s MIN. TYP. MAX. UNIT 630 6.9 10.9 44 1.2 A A V ns C December 1998 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHB11N50E, PHW11N50E 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating Transient Thermal Impedance, Zth j-a (K/W) PHP11N50E 1 D = 0.5 0.2 0.1 0.1 0.05 0.02 P D Single pulse tp D = tp/T 0.01 T t 1E+00 1E+01 0 20 40 60 80 100 Tmb / C 120 140 0.001 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) ID% Normalised Current Derating Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 120 110 100 90 80 70 60 50 40 30 20 10 0 Drain Current, ID (A) 8 7 6 5 4 3 2 1 0 Tj = 25 C VGS = 10 V PHP11N50E 5V 4.8 V 4.6 V 4.4 V 4.2 V 4V 0 20 40 60 80 Tmb / C 100 120 140 0 1 2 3 4 Drain-Source Voltage, VDS (V) 5 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 10 V Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS Drain-Source On Resistance, RDS(on) (Ohms) 100 Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID PHP11N50E tp = 10 us 1.4 4V 1.2 4.8V 1 10 100 us 1 ms 1 d.c. 10 ms 100 ms 0.2 PHP11N50E 0.1 10 100 Drain-Source Voltage, VDS (V) 1000 0 0 1 2 3 4 5 Drain Current, ID (A) 6 7 8 0.8 0.6 0.4 VGS = 10 V 5V 4.2V 4.4V 4.6V Tj = 25 C Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS December 1998 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHB11N50E, PHW11N50E Drain current, ID (A) 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 150 C VDS > ID X RDS(ON) PHP11N50E 4 VGS(TO) / V max. 3 typ. min. 2 Tj = 25 C 1 6 7 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Gate-source voltage, VGS (V) Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS ID / A SUB-THRESHOLD CONDUCTION Transconductance, gfs (S) 12 VDS > ID X RDS(ON) 10 8 6 4 2 0 0 5 10 Drain current, ID (A) 15 PHP11N50E Tj = 25 C 1E-01 1E-02 150 C 1E-03 2% typ 98 % 1E-04 1E-05 20 1E-06 0 1 2 VGS / V 3 4 Fig.8. Typical transconductance. gfs = f(ID); parameter Tj a Normalised RDS(ON) = f(Tj) Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS 2 10000 Capacitances, Ciss, Coss, Crss (pF) PHP11N50E Ciss 1000 1 100 Coss Crss 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 10 0.1 1 10 Drain-source voltage, VDS (V) 100 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 5.5 A; VGS = 10 V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz December 1998 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHB11N50E, PHW11N50E Source-Drain Diode Current, IF (A) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Gate-source voltage, VGS (V) ID = 11A Tj = 25 C 200V 100 V VDD=400V PHP11N50E PHP11N50E 20 18 16 14 12 10 8 6 4 2 0 150 C Tj = 25 C 0 20 40 60 80 Gate charge, QG (nC) 100 120 0 0.2 0.4 0.6 0.8 1 1.2 Drain-Source Voltage, VSDS (V) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj 450 400 350 300 250 200 150 100 50 0 Switching times, td(on), tr, td(off), tf (ns) VDD = 250V RD = 22 Ohms PHP11N50E td(off) 100 Non-repetitive Avalanche current, IAS (A) Tj prior to avalanche = 25 C 10 125 C tf tr td(on) 0.1 1E-06 1E-05 1E-04 Avalanche time, tp (s) 1 VDS tp ID PHP12N50E 1E-03 1E-02 0 10 20 30 Gate resistance, RG (Ohms) 40 50 Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG) Fig.17. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load 1.15 1.1 1.05 1 0.95 0.9 Normalised Drain-source breakdown voltage V(BR)DSS @ Tj V(BR)DSS @ 25 C 100 Maximum Repetitive Avalanche Current, IAR (A) 10 Tj prior to avalanche = 25 C 1 125 C 0.1 PHP12N50E 0.01 1E-06 -50 0 50 Tj, Junction temperature (C) 100 150 0.85 -100 1E-05 1E-04 Avalanche time, tp (s) 1E-03 1E-02 Fig.15. Normalised drain-source breakdown voltage; V(BR)DSS/V(BR)DSS 25 C = f(Tj) Fig.18. Maximum permissible repetitive avalanche current (IAR) versus avalanche time (tp) December 1998 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated MECHANICAL DATA Dimensions in mm Net Mass: 1.4 g 10.3 max PHB11N50E, PHW11N50E 4.5 max 1.4 max 11 max 15.4 2.5 0.85 max (x2) 2.54 (x2) 0.5 Fig.19. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.20. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". December 1998 7 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated MECHANICAL DATA Dimensions in mm Net Mass: 5 g 5.3 3.5 21 max 15.5 max seating plane 7.3 16 max PHB11N50E, PHW11N50E 5.3 max 1.8 o 3.5 max 2.5 4.0 max 1 2.2 max 3.2 max 5.45 2 3 0.9 max 1.1 5.45 0.4 M 15.5 min Fig.21. SOT429; pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT429 envelope. 3. Epoxy meets UL94 V0 at 1/8". December 1998 8 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated DEFINITIONS Data sheet status Objective specification Product specification Limiting values PHB11N50E, PHW11N50E This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. December 1998 9 Rev 1.000 |
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