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PRELIMINARY SPECIFICATION
PE84244
Military Operating Temperature Range
Product Description
The PE84244 MOSFET RF Switch is designed to cover a broad range of applications from DC to 3.0 GHz. This switch integrates on-board CMOS control logic with a low voltage CMOS compatible control input. Using a +3-volt nominal power supply voltage, a 1 dB compression point of +27 dBm can be achieved. The PE84244 also exhibits excellent isolation of 28 dB at 2.0 GHz and is offered in a small 8-lead MSOP package. The PE4244 MOSFET RF Switch is manufactured in Peregrine's patented Ultra Thin Silicon (UTSi) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram
RFCommon
SPDT MOSFET RF Switch
Features * Single +3.0-volt Power Supply * Low Insertion loss: 0.70 dB up to 2.0 GHz * High isolation of 39 dB at 1.0 GHz, 28 dB at 2.0 GHz, typical * Typical 1 dB compression of +27 dBm * Single-pin CMOS logic control * Packaged in 8-lead MSOP
Figure 2. Package Type
RF1 CTRL
RF2
8-lead MSOP
Table 1. Electrical Specifications -55 C to +125 C, VDD = 3 V (ZS = ZL = 50 )
Parameter
Operation Frequency Insertion Loss Isolation - RFCommon to RF1/RF2 Isolation - RF1 to RF2 Return Loss `ON' Switching Time `OFF' Switching Time Video Feedthrough
2 1
Conditions
Minimum
DC
Typical
Maximum
3000
Units
MHz dB dB dB dB ns ns mVpp dBm dBm
2000 MHz 2000 MHz 2000 MHz 2000 MHz CTRL to 0.1 dB final value, 2 GHz CTRL to 25 dB isolation, 2 GHz 25 24 18
0.7 28 27 25 200 90 15
0.95
Input 1 dB Compression Input IP3
2000 MHz 2000 MHz, 14dBm
25 40
27 42
Notes: 1. Device linearity will begin to degrade below 10 MHz. 2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50 test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
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Copyright Peregrine Semiconductor Corp. 2003
Page 1 of 7
PE84244
Preliminary Specification
Figure 3. Pin Configuration
VDD CTRL 1 2 8 7 RF1 GND GND
Table 4. DC Electrical Specifications
Parameter
VDD Power Supply Voltage IDD Power Supply Current VDD = 3V, VCNTL = 3V Control Voltage High Control Voltage Low 0.7xVDD 0.3xVDD
Min
2.7
Typ
3.0 250
Max
3.3 500
Units
V nA V V
PE84244
GND RFCommon 3 4 6 5
RF2
Table 5. Control Logic Truth Table Table 2. Pin Descriptions
Pin No.
1
Control Voltage Description
CTRL = CMOS High CTRL = CMOS Low
Signal Path
RFCommon to RF1 RFCommon to RF2
Pin Name
VDD
Nominal 3 V supply connection. A bypass capacitor (100 pF) to the ground plane should be placed as close as possible to the pin CMOS logic level: High = RFCommon to RF1 signal path Low = RFCommon to RF2 signal path Ground connection. Traces should be physically short and connected to ground plane for best performance. Common RF port for switch (Note 1) RF2 port (Note 1) Ground Connection. Traces should be physically short and connected to ground plane for best performance. Ground Connection. Traces should be physically short and connected to ground plane for best performance. RF1 port (Note 1)
Electrostatic Discharge (ESD) Precautions When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up.
2
CTRL
3
GND
4 5 6
RF Common RF2 GND
7
GND
8
RF1
Note 1: All RF pins must be DC blocked with an external series capacitor or held at 0VDC.
Table 3. Absolute Maximum Ratings
Symbol
VDD VI TST TOP
Parameter/Conditions
Power supply voltage Voltage on any input Storage temperature range Operating temperature range
Min
-0.3 -0.3 -65 -55
Max
4.0 VDD+ 0.3 150 125
Units
V V C C
PIN
VESD
Input power (50)
ESD voltage (Human Body Model)
30
1500
dBm
V
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0129~00A
| UTSi CMOS RFIC SOLUTIONS
Page 2 of 7
PE84244
Preliminary Specification
Typical Performance Data -55 C to +125 C (Unless Otherwise Noted) Figure 4. Insertion Loss - RFC to RF1 Figure 5. Input 1 dB Compression Point & IIP3
0.0
60
-55C
-0.3
IIP3
50
-55C 25C
Insertion Loss (dB)
-0.6
Power (dBm)
25C
-0.9
40
125C
125C
-1.2
30
1dB Compression
-1.5 0 500 1000 1500 2000 2500 3000
20 0 500 1000 1500 2000 2500 3000
Frequency (M Hz) Frequency (MHz)
Frequency (M Hz) Frequency (MHz)
Figure 6. Insertion Loss - RFC to RF2
Figure 7. Isolation - RFC to RF1
0.0
0
-55C
-0.3 -20
Insertion Loss (dB)
-0.6
Isolation (dB)
125C
-40
-55C
-60
25C
-0.9
125C
25C
-1.2
-80
-1.5 0 500 1000 1500 2000 2500 3000
-100 0 500 1000 1500 2000 2500 3000
Frequency (M Hz) (MHz)
Frequency (M Hz) Frequency (MHz)
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Copyright Peregrine Semiconductor Corp. 2003
Page 3 of 7
PE84244
Preliminary Specification
Typical Performance Data -55 C to +125 C (Unless Otherwise Noted) Figure 8. Isolation - RFC to RF2 Figure 9. Isolation - RF1 to RF2, RF2 to RF1
0
0
-20
-20
Isolation (dB)
Isolation (dB)
125C
-40
RF2
-40
-55C
-60
RF1
-60
25C
-80
-80
-100 0 500 1000 1500 2000 2500 3000
-100 0 500 1000 1500 2000 2500 3000 Frequency (M Hz) Frequency (MHz)
Frequency (MHz) Frequency (M Hz)
Figure 10. Return Loss - RFC to RF1, RF2
Figure 11. Return Loss - RF1, RF2
0
0
-5
-10
-10
Return Loss (dB)
-15
Return Loss (dB)
-20
-20
RF1 RF2
-30
RF2
-25
RF1
-30
-35 0 500 1000 1500 2000 2500 3000
-40 0 500 1000 1500 2000 2500 3000
Frequency (M Hz)
Frequency (M Hz) Frequency (MHz)
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0129~00A
| UTSi CMOS RFIC SOLUTIONS
Page 4 of 7
PE84244
Preliminary Specification
Evaluation Kit Information Evaluation Kit The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE84244 SPDT switch. The RF common port is connected through a 50 transmission line to the top left SMA connector, J1. Port 1 and Port 2 are connected through 50 transmission lines to the top two SMA connectors on the right side of the board, J3 and J4. A through transmission line connects SMA connectors J6 and J8. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a two metal layer FR4 material with a total thickness of 0.031". The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.030", trace gaps of 0.007", dielectric thickness of 0.028", metal thickness of 0.0014" and r of 4.4. J2 provides a means for controlling DC and digital inputs to the device. Starting from the lower left pin, the second pin to the right (J2-3) is connected to the device CNTL input. The fourth pin to the right (J2-7) is connected to the device VDD input. A decoupling capacitor (100 pF) is provided on both CNTL and VDD traces. It is the responsibility of the customer to determine proper supply decoupling for their design application. Removing these components from the evaluation board has not been shown to degrade RF performance. Figure 12. Evaluation Board Layouts
Figure 13. Evaluation Board Schematic
J2-7
100 pF
Optional
VDD
RF1
J3
CNTL J2-3 100 pF
Optional
GND
GND
GND
RFC J1
RF2 J4
J6
J8
PEREGRINE SEMICONDUCTOR CORP. |
http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 5 of 7
PE84244
Preliminary Specification
Figure 14. Package Drawing
8-lead MSOP
TOP VIEW 0.65BSC 8 7 6 5 .525BSC
2.450.10 2X 3.000.10
0.510.13 -B1 2 3 4 .25 A B C
0.510.13
2.950.10
-C0.860.08 2.950.10
1.10 MAX -A0.10 A 0.33+0.07 -0.08 0.08 ABC 3.000.10 FRONT VIEW SIDE VIEW 0.100.05 3.000.10 4.900.15
Table 6. Ordering Information
Order Code
84244-01 84244-02 84244-00
Part Marking
84244 84244 PE84244-EK
Description
PE84244-08MSOP-50A PE84244-08MSOP-2000C PE84244-08MSOP-EK
Package
8-lead MSOP 8-lead MSOP Evaluation Kit
Shipping Method
50 units / Tube 2000 units / T&R 1 / Box
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0129~00A
| UTSi CMOS RFIC SOLUTIONS
Page 6 of 7

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