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FINAL
COM'L: H-25
PALCE29MA16H-25
24-Pin EE CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s High-performance semicustom logic s Register/Latch Preload permits full logic
s
s s s
replacement; Electrically Erasable (EE) technology allows reprogrammability 16 bidirectional user-programmable I/O logic macrocells for Combinatorial/Registered/ Latched operation Output Enable controlled by a pin or product terms Varied product term distribution for increased design flexibility Programmable clock selection with common pin clock/latch enable (LE) or individual product term clock/LE with LOW/HIGH clock/ LE polarity
verification
s High speed (tPD = 25 ns, fMAX = 33 MHz and fMAX
internal = 50 MHz)
s Full-function AC and DC testing at the factory
for high programming and functional yields and high reliability s 24-pin 300 mil SKINNYDIP and 28-pin plastic leaded chip carrier packages s Extensive third-party software and programmer support through FusionPLD partners
GENERAL DESCRIPTION
The PALCE29MA16 is a high-speed, EE CMOS Programmable Array Logic (PAL) device designed for general logic replacement in TTL or CMOS digital systems. It offers high speed, low power consumption, high programming yield, fast programming, and excellent reliability. PAL devices combine the flexibility of custom logic with the off-the-shelf availability of standard products, providing major advantages over other
BLOCK DIAGRAM
CLK/LE I/OF 7 I/OF 6
I/O7
I/O6
I/O 5
I/O 4
I/OF5
I/OF4
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
V
V
V
V
V
4 4
4 4
4 8
4 12
V
4 12
4 8
V
4 4
V
4 4
Programmable AND Array 58x178
4 4 4
4 4
8 4
12 4
12 4
8 4
4 4
4
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
I/O Logic Macrocell
V
V
V
V
V
V
V
4
I 0 -I 3 I/OE
I/OF0
I/OF 1
I/O0
I/O 1
I/O 2
V
I/O3
I/OF 2
I/OF3
08811G-1
Publication# 08811 Rev. G Issue Date: June 1993 Amendment /0
2-349
AMD
GENERAL DESCRIPTION (continued)
semicustom solutions such as gate arrays and standard cells, including reduced development time and low upfront development cost. The PALCE29MA16 uses the familiar sum-of-products (AND-OR) structure, allowing users to customize logic functions by programming the device for specific applications. It provides up to 29 array inputs and 16 outputs. It incorporates AMD's unique input/output logic macrocell which provides flexible input/output structure and polarity, flexible feedback selection, multiple Output Enable choices, and a programmable clocking scheme. The macrocells can be individually programmed as combinatorial, registered, or latched with active-HIGH or active-LOW polarity. The flexibility of the logic macrocells permits the system designer to tailor the device to particular application requirements. Increased logic power has been built into the PALCE29MA16 by providing a varied number of logic
product terms per output. Of the 16 outputs, 8 outputs have 4 product terms each, 4 outputs have 8 product terms each, and the other 4 outputs have 12 product terms each. This varied product-term distribution allows complex functions to be implemented in a single PAL device. Each output can be dynamically controlled by a common Output Enable pin or Output Enable product term. Each output can also be permanently enabled or disabled. System operation has been enhanced by the addition of common asynchronous-Preset and Reset product terms and a power-up Reset feature. The PALCE29MA16 also incorporates Preload and Observability functions which permit full logic verification of the design. The PALCE29MA16 is offered in the space-saving 300-mil SKINNYDIP package as well as the plastic leaded chip carrier package.
CONNECTION DIAGRAMS Top View SKINNYDIP
PLCC
CLK/LE
I/OF0 I0
I/OF0 I/OF1 I/O0 I/O1 I/O2 I/O3 I/OF2 I/OF3 I/OE GND
3 4 5 6 7 8 9 10 11 12
22 21 20 19 18 17 16 15 14 13
I/OF7 I/OF6 I/O7 I/O6 I/O5 I/O4 I/OF5 I/OF4 I2 I1
08811G-2
4 I/OF1 I/O0 I/O1 NC I/O2 I/O3 I/OF2 5 6 7 8 9 10 11
3 2 1 28 27 26 25 24 23 22 21 20 19 I/OF6 I/O7 I/O6 NC I/O5 I/O4 I/OF5
12 13 14 15 16 17 18 I/OF3 I/OE GND NC I1 I2 I/OF4
I3
I0
2
23
I3
I/OF7
08811G-3
Note: Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLK/LE GND I I/O I/OF VCC NC 2-350 = Clock or Latch Enable = Ground = Input = Input/Output = Input/Output with Dual Feedback = Supply Voltage = No Connection PALCE29MA16H-25
NC VCC
CLK/LE
1
24
VCC
AMD
ORDERING INFORMATION Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of these elements:
PAL CE 29 MA 16 H -25 P C /4 FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY CE = CMOS Electrically Erasable NUMBER OF ARRAY INPUTS OUTPUT TYPE MA = Advanced Asynchronous Macrocell NUMBER OF FLIP-FLOPS POWER H = Half Power (100 mA) SPEED -25 = 25 ns OPTIONAL PROCESSING Blank = Standard Processing PROGRAMMING REVISION /4 = First Revision (Requires current programming Algorithm)
TEMPERATURE RANGE C = Commercial (0C to +75C)
PACKAGE TYPE P = 24-Pin Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028)
Valid Combinations PALCE29MA16H-25 PC, JC /4
Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
PALCE29MA16H-25 (Com'l)
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AMD
FUNCTIONAL DESCRIPTION Inputs
The PALCE29MA16 has 29 inputs to drive each product term (up to 58 inputs with both TRUE and complement versions available to the AND array) as shown in the block diagram in Figure 1. Of these 29 inputs, 4 are dedicated inputs, 16 are from eight I/O logic macrocells with two feedbacks, 8 are from other I/O logic macrocells with single feedback and one is the I/OE input. Initially the AND-array gates are disconnected from all the inputs. This condition represents a logical TRUE for the AND array. By selectively programming the EE cells, the AND array may be connected to either the TRUE input or the complement input. When both the TRUE and complement inputs are connected, a logical FALSE results at the output of the AND gate.
device ranging from 4 to 12 wide, with an average of 7 logic product terms per output. An increased number of product terms per output allows more complex functions to be implemented in a single PAL device. This flexibility aids in implementing functions such as counters, exclusive-OR functions, or complex state machines, where different states require different numbers of product terms. Individual asynchronous-Preset and Reset product terms are connected to all Registered or Latched I/Os. When the asynchronous-Preset product term is asserted (HIGH) the register or latch will immediately be loaded with a HIGH, independent of the clock. When the asynchronous-Reset product term is asserted (HIGH) the register or latch will be immediately loaded with a LOW, independent of the clock. The actual output state will depend on the macrocell polarity selection. The latches must be in latched mode (not transparent mode) for the Reset, Preset, Preload, and power-up Reset modes to be meaningful.
Product Terms
The degree of programmability and complexity of a PAL device is determined by the number of connections that form the programmable-AND and OR gates. Each programmable-AND gate is called a product term. The PALCE29MA16 has 178 product terms; 112 of these product terms provide logic capability and others are architectural product terms. Among the control product terms, one is for Observability, and one is for Preload. The Output Enable of each macrocell can be programmed to be controlled by a common Output Enable pin or an individual product term. It may also be permanently disabled. In addition, independent product terms for each macrocell control Preset, Reset and CLK/LE. Each product term on the PALCE29MA16 consists of a 58-input AND gate. The outputs of these AND gates are connected to a fixed-OR plane. Product terms are allocated to OR gates in a varied distribution across the
Input/Output Logic Macrocells
The I/O logic macrocell allows the user the flexibility of defining the architecture of each input or output on an individual basis. It also provides the capability of using the associated pin either as an input or an output. The PALCE29MA16 has 16 macrocells, one for each I/O pin. Each I/O macrocell can be programmed for combinatorial, registered or latched operation (see Figure 2). Combinatorial output is desired when the PAL device is used to replace combinatorial glue logic. Registers and Latches are used in synchronous logic applications. Registers and Latches with product term controlled clocks can also be used in asychronous application.
VCC 0 1 1 0 S6 1 0 Preset Q D Q S0 CLK/LE Reset
V
Common I/OE (Pin) Individual OE Individual Asynchronous Preset P0 P7 or P11 Common CLK/LE (PIN) Individual CLK/LE S4 Individual Asynchronous Reset To AND Array S8 1 0 RX 1 1 0 0 1 0 1 0 S5
1 1 0 0 S7 I/O X
1 0 1 0
1 1 0 0 S1
S3
S2
08811G-4
Figure 2a. PALCE29MA16 Macrocell (Single Feedback) 2-352 PALCE29MA16H-25
AMD The output polarity for each macrocell in each of the three modes of operation is user-selectable, allowing complete flexibility of the macrocell configuration. Eight of the macrocells (I/OF0-I/OF7) have two independent feedback paths to the AND array (see Figure 2b). The first is a dedicated I/O pin feedback to the AND array for combinatorial input. The second path consists of a direct register/latch feedback to the array. If the pin is used as a dedicated input using the first feedback path, the register/latch feedback path is still available to the AND array. This path provides the capability of using the register/latch as a buried state register/latch. The other eight macrocells have a single feedback path to the AND array. This feedback is user-selectable as either an I/O pin or a register/latch feedback (see Figure 2a). Each macrocell can provide true input/output capability. The user can select each macrocell register/latch to be driven by either the signal generated by the AND-OR array or the corresponding I/O pin. When the I/O pin is selected as the input, the feedback path provides the register/latch input to the array. When used as an input, each macrocell is also user-programmable for registered, latched, or combinatorial input. The PALCE29MA16 has a dedicated CLK/LE pin and one individual CLK/LE product term or macrocell. All macrocells have a programmable switch to choose between the CLK/LE pin and the CLK/LE product term as the clock or latch enable signal. These signals are clock signals for macrocells configured as registers and latch enable signals for macrocells configured as latches. The polarity of these CLK/LE signals is also individually programmable. Thus different registers or latches can be driven by different clocks and clock phases. The Output-Enable mode of each of the macrocells can be selected by the user. The I/O pin can be configured as an output pin (permanently enabled) or as an input pin (permanently disabled). It can also be configured as
Common I/OE (Pin) Individual OE Individual Asynchronous Preset P0 P3 Common CLK/LE (PIN) Individual CLK/LE S4 Individual Asynchronous Reset To AND Array To AND Array RFX
08811G-5
a dynamic I/O controlled by the Output Enable pin or by a product term.
I/O Logic Macrocell Configuration
AMD's unique I/O macrocell offers major benefits through its versatile, programmable input/output cell structure, multiple clock choices, flexible Output Enable and feedback selection. Eight I/O macrocells with single feedback contain 9 EE cells, while the other eight macrocells contain 8 EE cells for programming the input/ output functions (see Table 1). EE cell S1 controls whether the macrocell will be combinatorial or registered/latched. S0 controls the output polarity (active-HIGH or active-LOW). S2 determines whether the storage element is a register or a latch. S3 allows the use of the macrocell as an input register/latch or as an output register/latch. It selects the direction of the data path through the register/latch. If connected to the usual AND-OR array output, the register/latch is an output connected to the I/O pin. If connected to the I/O pin, the register/latch becomes an input register/latch to the AND array using the feedback data path. Programmable EE cells S4 and S5 allow the user to select one of the four CLK/LE signals for each macrocell. S6 and S7 are used to control Output Enable as pin controlled, product-term controlled, permanently enabled or permanently disabled. S8 controls a feedback multiplexer for the macrocells with a single feedback path only. Using the programmable EE cells S0-S8 various input and output configurations can be selected. Some of the possible configuration options are shown in Figure 3. In the erased state (charged, disconnected), an architectural cell is said to have a value of "1"; in the programmed state (discharged, connected to GND), an architectural cell is said to have a value of "0."
VCC
0 1 1 0 S6
1 1 0 0 S7 I/OFX
1 0 S3 1 1 0 0 1 0 1 0 S5
Preset Q D Q S0 CLK/LE Reset
V
1 0 1 0
1 1 0 0 S1
S2
Figure 2b. PALCE29MA16 Macrocell (Dual Feedback) PALCE29MA16H-25 2-353
AMD Table 1a. PALCE29MA16 I/O Logic Macrocell Architecture Selections
S3 1 0 I/O Cell Output Cell Input Cell S2 1 0 Storage Element Register Latch
S1 1 0
Output Type Combinatorial Register/Latch
S0 1 0
Output Polarity Active LOW Active HIGH
S8 1 0
Feedback* Register/Latch I/O
*Applies to macrocells with single feedback only.
Table 1b. PALCE29MA16 I/O Logic Macrocell Clock Polarity and Output Enable Selections
S4 1 1 0 0 S5 1 0 1 0 Clock Edge/Latch Enable Level CLK/LE pin positive-going edge, active-LOW LE* CLK/LE pin negative-going edge, active-HIGH LE* CLK/LE PT positive-going edge, active-LOW LE* CLK/LE PT negative-going edge, active-HIGH LE*
S6 1 1 0 0
S7 1 0 1 0
Output Buffer Control Pin-Controlled Three-State Enable PT-Controlled Three-State Enable Permanently Enabled (Output only) Permanently Disabled (Input only)
Notes: 1 = Erased State (Charged or disconnected). 0 = Programmed State (Discharged or connected). *Active-LOW LE means that data is stored when the LE pin is HIGH, and the latch is transparent when the LE pin is LOW. Active-HIGH LE means the opposite.
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SOME POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL
(For other useful configurations, please refer to the macrocell diagrams in Figure 2. All macrocell architecture cells are independently programmable).
D V
Q Q S0 = 1 S1 = 0 S3 = 1 S2 = 1 D V Q Q S0 = 1 S1 = 1 S3 = 1
08811G-6
Output Registered/Active Low
08811G-7
Output Combinatorial/Active Low
D V
Q Q S0 = 0 S1 = 0 S3 = 1 S2 = 1
D V
Q Q
S0 = 0 S1 = 1 S3 = 1
08811G-8
08811G-9
Output Registered/Active High
Output Combinatorial/Active High
Figure 3a. Dual Feedback Macrocells
D V
Q Q S0 = 1 S1 = 0 S3 = 1 S8 = 0 S2 = 1 S0 = 1 S1 = 1 S3 = 1 S8 = 0
08811G-10
08811G-11
Output Registered/Active Low, I/O Feedback
Output Combinatorial/Active Low, I/O Feedback
D
Q S0 = 0 S1 = 0 S3 = 1 S8 = 0 S2 = 0 S0 = 0 S1 = 1 S3 = 1 S8 = 0
LE Q
08811G-12
08811G-13
Output Latched/Active High, I/O Feedback
Output Combinatorial/Active High, I/O Feedback
Figure 3b. Single Feedback Macrocells PALCE29MA16H-25 2-355
AMD
SOME POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL
D V
Q Q S0 = 1 S1 = 0 S3 = 1 S8 = 1 S2 = 1 D V Q Q S0 = 1 S1 = 1 S3 = 1 S8 = 1 S2 = 1
08811G-14
Output Registered/Active Low, Register Feedback
08811G-15
Output Combinatorial/Active Low, Latched Feedback
D
Q S0 = 1 S1 = 0 S3 = 1 S8 = 1 S2 = 0 D Q S0 = 1 S1 = 1 S3 = 1 S8 = 1 S2 = 0
LE Q
LE Q
08811G-16
Output Latched/Active Low, Latched Feedback
08811G-17
Output Combinatorial/Active Low, Latched Feedback
Figure 3b. Single Feedback Macrocells (Continued)
D Q V
S3 = 0 S8 = 1 (FOR SINGLE FEEDBACK ONLY) S2 = 1 REGISTER = 0 LATCH
08811G-18
PROGRAMMABLE-AND ARRAY
Programmable-AND Array
Figure 3c. All Macrocells
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Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. The outputs of the PALCE29MA16 depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be LOW if programmed as active LOW and HIGH if programmed as active HIGH. If combinatorial is selected, the output will be a function of the logic.
pin for each of the logic macrocells. This unique feature allows for easy debugging and tracing of the buried state machines. In addition, a capability of supervoltage observability is also provided.
Security Cell
A security cell is provided on each device to prevent unauthorized copying of the user's proprietary logic design. Once programmed, the security cell disables the programming, verification, preload, and the observability modes. The only way to erase the protection cell is by erasing the entire array and architecture cells, in which case no proprietary design can be copied. (This cell should be programmed only after the rest of the device has been completely programmed and verified.)
Preload
To simplify testing, the PALCE29MA16 is designed with preload circuitry that provides an easy method for testing logical functionality. Both product-term-controlled and supervoltage-enabled preload modes are available. The TTL-level preload product term can be useful during debugging, where supervoltages may not be available. Preload allows any arbitrary state value to be loaded into the registers/latches of the device. A typical functional-test sequence would be to verify all possible state transitions for the device being tested. This requires the ability to set the state registers into an arbitrary "present state" value and to set the device's inputs into an arbitrary "present input" value. Once this is done, the state machine is clocked into a new state, or "next state," which can be checked to validate the transition from the "present state." In this way any transition can be checked. Since preload can provide the capability to go directly to any desired arbitrary state, test sequences may be greatly shortened. Also, all possible states can be tested, thus greatly reducing test time and development costs and guaranteeing proper in-system operation.
Programming and Erasing
The PALCE29MA16 can be programmed on standard logic programmers. It may also be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming hardware. No special erasure operation is required.
Quality and Testability
The PALCE29MA16 offers a very high level of built-in quality. The erasability of the device provides a direct means of verifying performance of all the AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to yield the highest programming yield and post-programming functional yield in the industry.
Technology
The high-speed PALCE29MA16 is fabricated with AMD's advanced electrically-erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input-clamp diodes, output slew-rate control, and a grounded substrate for clean switching.
Observability
The output register/latch observability product term, when asserted, suppresses the combinatorial output data from appearing on the I/O pin and allows the observation of the contents of the register/latch on the output
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LOGIC DIAGRAM SKINNY DIP (PLCC) Pinouts
CLK/LE (2) 1
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56
(3) 2 I0 (4) 3 I/OF0
Input/ Output Macro
23 (27) I3
OBSERVE PRODUCT TERM
Input/ Output Macro
22 (26) I/OF 7
(5) 4 I/OF1
Input/ Output Macro
Input/ Output Macro
21 (25) I/OF 6
(6) 5 I/O 0
Input/ Output Macro
Input/ Output Macro
20 (24) I/O 7
(7) 6 I/O 1
Input/ Output Macro
19 (23) I/O6
Input/ Output Macro
Continued on Next Page
08811G-19
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LOGIC DIAGRAM SKINNY DIP (PLCC) Pinouts
Continued from Previous Page
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56
(9) 7 I/O 2
Input/ Output Macro
18 (21) I/O 5
Input/ Output Macro
(10) 8 I/O 3
Input/ Output Macro
Input/ Output Macro
17 (20) I/O 4
(11) 9 I/OF2
Input/ Output Macro
Input/ Output Macro
16 (19) I/OF5
(12) 10 I/OF 3
Input/ Output Macro
PRELOAD PRODUCT TERM
Input/ Output Macro
15 (18) I/OF4
(13) 11 I/OE
14 (17) I2 13 (16) I1
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56
08811G-19 (concluded)
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +75C) . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL Parameter Description Output HIGH Voltage Output LOW Voltage Test Conditions IOH = -2 mA IOL = 8 mA IOL = 4 mA IOL = 20 A VIH VIL IIH IIL IOZH IOZL ISC ICC Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.5 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.5 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 5.5 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max -30 2.0 0.8 10 -10 10 -10 -130 100 VIN = VIH or VIL VCC = Min VIN = VIH or VIL VCC = Min Min 2.4 0.5 0.33 0.1 V V A A A A mA mA V Max Unit V
Notes: 1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
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AMD
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 0 V VOUT = 0 V VCC = 5.0 V, TA = 25C, f = 1 MHz Typ 5 8 Unit pF pF
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
SWITCHING CHARACTERISTICS Registered Operation
Parameter Symbol tPD Parameter Description Input or I/O Pin to Combinatorial Output Min Max 25 Unit ns
Combinatorial Output
Output Register - Pin Clock tSOR tCOR tHOR Input or I/O Pin to Output Register Setup Output Register Clock to Output Data Hold Time for Output Register 0 15 15 ns ns ns
Output Register - Product Term Clock tSORP tCORP tHORP I/O Pin or Input to Output Register Setup Output Register Clock to Output Data Hold Time for Output Register 10 4 29 ns ns ns
Input Register - Pin Clock tSIR tCIR tHIR I/O Pin to Input Register Setup Register Feedback Clock to Combinatorial Output Data Hold time for Input Register 6 2 28 ns ns ns
Clock and Frequency tCIS tCISPP fMAX fMAXI fMAXP fMAXIPP tCWH tCWL tCWHP tCWLP Register Feedback (Pin Driven Clock) to Output Register/Latch (Pin Driven) Setup Register Feedback (PT Driven Clock) to Output Register/Latch (PT Driven) Setup Maximum Frequency (Pin Driven) 1/(tSOR + tCOR) Maximum Internal Frequency (Pin Driven) 1/tCIS Maximum Frequency (PT Driven) 1/(tSORP + tCORP) Maximum Internal Frequency (PT Driven) 1/tCISPP Pin Clock Width HIGH Pin Clock Width LOW PT Clock Width HIGH PT Clock Width LOW 20 25 33.3 50 30 40 8 8 12 12 ns ns MHz MHz MHz MHz ns ns ns ns
PALCE29MA16H-25 (Com'l)
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AMD
CLK
V
tSIR Input Register
t CIS
AND-OR Array
t CIS
V
Output Register t COR
I/O
I/O
I/O t SOR t PD
I/O t CIR t PD
08811G-20
Input/Output Register Specs (Pin CLK Reference)
CLK Input
V
Input Register
t CISPP
AND-OR Array
t CISPP
V
Output Register t CORP
I/O
I/O
I/O tSORP t PD
I/O
t PD
08811G-21
Input/Output Register Specs (PT CLK Reference)
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SWITCHING WAVEFORMS
Combinatorial Input Combinatorial Output
VT tPD VT
Combinatorial Output Combinatorial Output
08811G-22
Combinatorial Input Clock
VT tSOR tHOR VT tCOR
VT
Registered Output
VT
Output Register (Pin Clock) Output Register (Pin Clock)
08811G-23
Combinatorial Input Combinatorial Input as Clock Registered Output
VT t SORP VT t CORP
VT t HORP
VT
Output Register (PT Clock) Output Register (PT Clock)
08811G-24
Registered Input
VT t SIR t HIR VT t CIR
VT
Clock
Combinatorial Output
VT
Input Register Input Register
08811G-25
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SWITCHING WAVEFORMS
t CIS
Clock
VT tCWH
VT t CWL
VT
Pin Clock Width Pin Clock Width
08811G-26
t CISPP
Combinatorial Input as Clock
VT t CWLP
VT t CWHP
VT
08811G-27
PT Clock Width PT Clock Width
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AMD
SWITCHING CHARACTERISTICS Latched Operation
Parameter Symbol tPD tPTD Parameter Description Input or I/O Pin to Combinatorial Output Input or I/O Pin to Output via Transparent Latch Min Max 25 28 Unit ns ns
Combinatorial Output
Output Latch - Pin LE tSOL tGOL tHOL tSTL Input or I/O Pin to Output Register Setup Latch Enable to Transparent Mode Output Data Hold Time for Output Latch Input or I/O Pin to Output Latch Setup via Transparent Input Latch Input or I/O Pin to Output Latch Setup Latch Enable to Transparent Mode Output Data Hold Time for Output Latch Input or I/O Pin to Output Latch Setup via Transparent Input Latch 10 10 0 18 15 15 ns ns ns ns
Output Latch - Product Term LE tSOLP tGOLP tHOLP tSTLP 4 29 ns ns ns ns
Input Latch - Pin LE tSIL tGIL tHIL Latch Enable tGIS tGISPP tGWH tGWL tGWHP tGWLP Latch Feedback (Pin Driven) to Output Register/Latch (Pin Driven) Setup Latch Feedback (PT Driven) to Output Register/Latch (PT Driven) Setup Pin Enable Width HIGH Pin Enable Width LOW PT Enable Width HIGH PT Enable Width LOW 20 25 8 8 12 12 ns ns ns ns ns ns I/O Pin to Input Latch Setup Latch Feedback, Latch Enable Transparent Mode to Combinatorial Output Data Hold Time for Input Latch 6 2 28 ns ns ns
PALCE29MA16H-25 (Com'l)
2-365
AMD
LE
t GIS t STL t SIL tPTD I/O Input Latch
AND-OR Array
t GIS Output Latch t GOL t PTD I/O
I/O t SOL t PTD t PD
I/O t GIL t PTD t PD
08811G-28
Input/Output Latch Specs (Pin LE Reference)
LE INPUT
tGISPP t STLP tPTD I/O
AND-OR Array
tGISPP t GOLP Output Latch
Input Latch
t PTD I/O
I/O t SOLP t PTD t PD
I/O t PTD tPD
08811G-29
Input/Output Latch Specs (PT LE Reference)
2-366
PALCE29MA16H-25
AMD
SWITCHING WAVEFORMS
Latched Input
VT tPTD LE Latched VT Transparent
Combinatorial Input Combinatorial Output
VT tPD VT tPTD Transparent
Input Latch
tGIS
Latched Output Latch
VT
LE
08811G-31
VT
Latched Output
Input and Output Latch Relationship
08811G-30
Latch (Transparent Mode)
Latched Input
VT t STL
Latched Input
VT t STLP
Combinatorial Input LE
VT t SOL t HOL VT
VT
Combinatorial Input
t SOLP VT Transparent t GOL
VT t HOLP VT VT Transparent t GOLP
Combinatorial Input as LE Latched Output
t PTD
Latched Output
t PTD
VT t PTD
VT
VT
VT
Note 1
08811G-32
08811G-33
Output Latch (Pin LE)
Latched Input
Output Latch (PT LE)
VT t SIL t HIL VT
VT t GIL VT Transparent
LATCHED
TRANSPARENT VT VT t GWL
LE
VT t GWH
LE
08811G-35
Combinatorial Output
t PTD
VT
VT
Pin LE Width
08811G-34
Input Latch (Pin LE)
Combinatorial Input as LE
VT
Latched
Transparent VT VT tGWHP
t GWLP
Note:
PT LE Width
08811G-36
1. If the combinatorial input changes while LE is in the latched mode and LE goes into the transparent mode after tPTD ns has elasped, the corresponding latched output will change tGOL ns after LE goes into the transparent mode. If the combinatorial input changes while LE is in the latched mode and LE goes into the transparent mode before tPTD ns has elapsed, the corresponding latched output will change at the later of the following - tPTD ns after the combinatorial input changes or tGOL ns after LE goes into the latched mode.
PALCE29MA16H-25
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AMD
SWITCHING CHARACTERISTICS Reset/Preset, Enable
Parameter Symbol tAPO tAW tARO tARI tARPO tARPI Parameter Description Input or I/O Pin to Output Register/Latch Reset/Preset Asynchronous Reset/Preset Pulse Width Asynchronous Reset/Preset to Output Register/Latch Recovery Asynchronous Reset/Preset to Input Register/Latch Recovery Asynchronous Reset/Preset to Output Register/Latch Recovery PT Clock/LE Asynchronous Reset/Preset to Input Register/Latch Recovery PT Clock/LE I/OE Pin to Output Enable I/OE Pin to Output Disable (Note 1) Input or I/O to Output Enable via PT Input or I/O to Output Disable via PT (Note 1) 15 15 12 4 6 Min Max 30 Unit ns ns ns ns ns ns
Output Enable Operation tPZX tPXZ tEA tER 20 20 25 25 ns ns ns ns
Note: 1. Output disable times do not include test load RC time constants.
SWITCHING WAVEFORMS
t AW
Combinatorial Asynchronous Reset/Preset Registered/ Latched Output Clock
VT t APO VT t ARO VT
Pin 11 Combinatorial/ Registered/ Latched Output
t PXZ
VT t PZX VOH - 0.5 V VOL + 0.5 V VT
08811G-37
08811G-39
Output Register/Latch Reset/Preset
Pin 11 to Output Disable/Enable
t AW
Combinatorial Asynchronous Reset/Preset
VT t ARI
Combinatorial Input
VT
VT t ER VOH - 0.5 V VOL + 0.5 V t EA VT
Clock
08811G-38
Combinatorial/ Registered/ Latched Output
08811G-40
Input Register/Latch Reset/Preset
Input to Output Disable/Enable
2-368
PALCE29MA16H-25 (Com'l)
AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply
OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
S1 5V
R1
Output R2
CL
08811G-41
Specification tPD, tCO, tGOL tEA, tPZX
Switch S1 Closed ZH: open ZL: closed
CL
R1
R2
Measured Output Value 1.5 V
35 pF 470 5 pF 390
1.5 V
tER, tPXZ
HZ: open LZ: closed
HZ: VOH -0.5 V LZ: VOL +0.5 V
PALCE29MA16H-25
2-369
AMD
PRELOAD
The PALCE29MA16 has the capability for product-term Preload. When the global-preload product term is true, the PALCE29MA16 will enter the preload mode. This feature aids functional testing by allowing direct setting of register states. The procedure for Preload is as follows:
s Set the selected input pins to the user selected
s Pulse the clock pin (pin 1). s Remove the inputs to the I/O pins. s Remove the Preload condition. s Verify VOL/VOH for all output pins as per pro-
grammed pattern. Because the Preload command is a product term, any input to the array can be used to set Preload (including I/O pins and registers). Preload itself will change the values of the I/O pins and registers. This will have unpredictable results. Therefore, only dedicated input pins should be used for the Preload command.
preload condition.
s Apply the desired register value to the I/O pins.
This sets Q of the register. The value seen on the I/O pin, after Preload, will depend on whether the macrocell is active high or active low.
Parameter Symbol tD tW tI/O
Parameter Description Delay Time Pulse Width Valid Output
Min 0.5 250 100
Rec. 1.0 500
Max 5.0 700 500
Unit s ns ns
VIH
Inputs Preload Mode
VIL tD
I/O Pins Data to be Preloaded
tIO
VOH/VIH VOL/VIL
tD
CLK Pin 1 (2)
tD VIH tW VIL
08811G-42
Preload Waveform
2-370
PALCE29MA16H-25
AMD
OBSERVABILITY
The PALCE29MA16 has the capability for product-term Observability. When the global-Observe product term is true, the PALCE29MA16 will enter the Observe mode. This feature aids functional testing by allowing direct observation of register states. When the PALCE29MA16 is in the Observe mode, the output buffer is enabled and the I/O pin value will be Q of the corresponding register. This overrides any OE inputs. The procedure for Observe is:
s Remove the inputs to all the I/O pins. Parameter Symbol tD tI/O
s Set the inputs to the, user selected, Observe
configuration. s The register values will be sent to the corresponding I/O pins. s Remove the Observe configuration from the selected I/O pins. Because the Observe command is a product term, any input to the array can be used to set Observe (including I/O pins and registers). If I/O pins are used, the observe mode could cause a value change, which would cause the device to oscillate in and out of the Observe mode. Therefore, only dedicated input pins should be used for the Observe command.
Parameter Description Delay Time Valid Output
Min 0.5 100
Rec. 1.0
Max 5.0 500
Unit s ns
Input Pins
VIH
Observe Mode
VIL tD tIO VOH
I/O Pins
VOL VIH
CLK Pin 1 (2)
VIL
08811G-43
Observability Waveform
PALCE29MA16H-25
2-371
AMD
POWER-UP RESET
The registered devices in the AMD PAL Family have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to LOW. The output state will depend on the polarity of the output buffer. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the
Parameter Symbol tPR tS tW tR Parameter Description Power-Up Reset Time Input or Feedback Setup Time Clock Width VCC Rise Time
asynchronous operation of the power-up reset, and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are:
s The VCC rise must be monotonic. s Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and feedback setup times are met.
Min
Max 10
Unit s
See Switching Characteristics 500 s
Power
4V
VCC tPR
tR
Registered Active LOW Output
tS
Clock
tW
08811G-44
Power-Up Reset Waveform
2-372
PALCE29MA16H-25
AMD
TYPICAL THERMAL CHARACTERISTICS
Measured at 25C ambient. These parameters are not tested.
Parameter Symbol jc ja jma Typ Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient Thermal impedance, junction to ambient with air flow 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air SKINNYDIP 17 63 60 52 43 39 PLCC 11 51 43 38 34 30 Unit C/W C/W C/W C/W C/W C/W
Plastic jc Considerations The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment.
PALCE29MA16H-25
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