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| (Preliminary)PLL500-37 Low Phase Noise VCXO (36MHz to 130MHz) FEATURES * * * * * * * * * * * VCXO output for the 36MHz to 130MHz range Low phase noise (-148 dBc @ 10kHz offset at 77.76MHz). CMOS output with OE tri-state control. 36 to 130MHz fundamental crystal input. Integrated high linearity variable capacitors. 8mA drive capability at TTL output. +/- 150 ppm pull range, max 5% linearity. Low jitter (RMS): 2.5ps period jitter. Single 2.5V 10% or 3.3V 10 power supply. Operating temperature range from -40C to +85C Available in Die or Wafer form. PIN AND PAD CONFIGURATION 32 mil (812,986) 8 1 XIN XOUT OE^ 7 39 mil 2 OE^ VDD 6 3 VCON 4 GND CLK 5 Y X (0,0) Note: ^ denotes pull-up resistor DESCRIPTION The PLL500-37 is a low cost, high performance and low phase noise VCXO for the 36 to 130MHz range, providing less than -148dBc at 10kHz offset at 77.76MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 36 to 130MHz (fundamental resonant mode). DIE SPECIFICATIONS Name Value Size Reverse side Pad dimensions Thickness 39 x 32 mil GND 80 micron x 80 micron 12 mil BLOCK DIAGRAM XIN XOUT XTAL OSC VARICAP OE VCON 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 1 (Preliminary)PLL500-37 Low Phase Noise VCXO (36MHz to 130MHz) PAD ASSIGNMENT AND DESCRIPTION Name XIN Pad # 1 2 Die Pad Position X (m) 94.2 94.2 715.5 94.2 94.2 715.5 715.5 477.0 Y (m) 768.6 605.0 Type I Crystal input pin. Description OE 7 VCON GND CLK VDD XOUT 3 4 5 6 8 626.7 331.7 140.4 203.9 455.7 888.8 P I P O P O Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected to low. Use only one OE signal. Frequency control voltage input pin. Ground pin. Output clock pin. VDD power supply pin. Crystal output pin. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL VDD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. 4.6 VDD+0.5 VDD+0.5 150 85 125 260 2 UNITS V V V C C C C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 2 (Preliminary)PLL500-37 Low Phase Noise VCXO (36MHz to 130MHz) 2. AC Electrical Specifications PARAMETERS Input Crystal Frequency Output Clock Rise/Fall Time Output Clock Duty Cycle Short Circuit Current 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load Measured @ 1.4V 45 SYMBOL CONDITIONS MIN. 36 TYP. 1.15 3.7 50 50 MAX. 130 UNITS MHz ns 55 % mA 3. DC Specifications PARAMETERS Supply Current, Dynamic, with Loaded Outputs Allowable output load capacitance Operating Voltage Output Low Voltage at CMOS level Output High Voltage at CMOS level Output drive current Short Circuit Current VCXO Control Voltage VCON 0 SYMBOL IDD CL (Output) VDD VOLC VOHC CONDITIONS FXIN = 77.76MHz Output load of 15pF Standard drive up to 100MHz MIN. TYP. 7.2 MAX. 9 15 UNITS mA pF V V V mA 2.25 IOL = +4mA IOH = -4mA For VOL<0.4V or VOH>2.4V VDD - 0.4 8 50 3.63 0.4 mA VDD V 4. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity Power Supply Rejection VCON pin input impedance VCON modulation BW 0V VCON 3.3V, -3dB PWSRR Frequency change with VDD varied +/- 10% -1 2000 45 SYMBOL TVCXOSTB CONDITIONS From power valid FXIN = 36 - 130MHz; XTAL C0/C1 < 250 0V VCON 3.3V VCON=1.65V, 1.65V MIN. TYP. MAX. 10 UNITS ms ppm ppm 300 150 100 5 +1 ppm/V % ppm k kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 3 (Preliminary)PLL500-37 Low Phase Noise VCXO (36MHz to 130MHz) 5. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Maximum Sustainable Drive Level Operating Drive Level C0/C1 C0 2.0pF, FXIN up to 85MHz C0 2.5pF, FXIN up to 80MHz C0 3.0pF, FXIN up to 75MHz C0 2.0pF, FXIN up to 95MHz C0 2.5pF, FXIN up to 90MHz C0 3.0pF, FXIN up to 85MHz C0 2.0pF, FXIN up to 110MHz C0 2.5pF, FXIN up to 105MHz C0 3.0pF, FXIN up to 100MHz C0 2.0pF, FXIN up to 130MHz C0 2.5pF, FXIN up to 120MHz C0 3.0pF, FXIN up to 115MHz 50 250 30 25 20 15 SYMBOL FXIN CL (xtal) CONDITIONS VCON = 1.65V MIN. 36 TYP. MAX. 130 UNITS MHz pF 5.0 200 W W ESR RS Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range and oscillator gain. 6. Jitter and Phase Noise Specifications PARAMETERS RMS Period Jitter (1 sigma - 1000 samples) Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier CONDITIONS With capacitive decoupling between VDD and GND. 77.76MHz @10Hz offset 77.76MHz @100Hz offset 77.76MHz @1kHz offset 77.76MHz @10kHz offset 77.76MHz @100kHz offset 77.76MHz @1MHz offset MIN. TYP. 2.5 -80 -110 -134 -148 -150 -152 MAX. UNITS ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 4 (Preliminary)PLL500-37 Low Phase Noise VCXO (36MHz to 130MHz) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL500-37 X X PART NUMBER PACKAGE TYPE W= Wafer D= DIE TEMPERATURE C=COMMERCIAL I=INDUSTRIAL Part / Order Number PLL500-37WC PLL500-37DC Marking P500-37WC P500-37DC Package Option Wafer Die (Waffle Pack) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 5 |
Price & Availability of P500-37WC
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