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NJU6824
Preliminary
128-common x (128+2) RGB-Segment, in 4096-Color STN LCD DRIVER
s GENERAL DESCRIPTION
The NJU6824 is a STN LCD driver with 128-common x (128+2) RGB-segment in 4096-color. It consists of 384(128xRGB)-segment + 6(2xRGB)-icon segment, 128common drivers, serial and parallel MPU interface circuits, internal power supply circuits, gradation palettes and 196,608-bit for graphic display data RAM. Each segment driver outputs 16-gradation level out of 32-gradation level of gradation palette. The display rotate function makes easily rotated display without original display data change. Since the NJU6824 provides a low operating voltage of 1.7V and low operating current, it is ideally suited for battery-powered handheld applications.
s PACKAGE OUTLINE
NJU6824CJ
s FEATURES
q q q q q q q q q q q q q q q 4096-color STN LCD driver LCD drivers 128-commons, 128RGB-segments, 2RGB-icon segments Display data RAM (DDRAM) 196,608-bit for graphic display Color display mode 16 gradation level out of 32-gradation level of gradation palette Black & white display mode 128 x 384 pixels in 16-gradation level or 128 x 384 pixels in B&W 256-color driving mode 8/16bit Parallel interface directly-connective to 68/80 series MPU Programmable 8- or 16-bit data bus length for display data 3-/4-line serial interface Programmable duty and bias ratios Programmable internal voltage booster (Maximum 6-times) Bias voltage adjustment circuits Programmable contrast control using 128-step EVR Display Rotate Function / Display Mirror Inverse Function Various instructions Display data read/write, Display ON/OFF, Reverse display ON/OFF, All pixels ON/OFF, column address, row address, N-line inversion, Initial display line, Initial COM line, Read-modify-write, Gradation mode control, Increment control, Data bus length, Discharge ON/OFF, Duty cycle ratio, LCD bias ratio, Boost level, EVR control, Power save ON/OFF, etc Low operating current Low logic supply voltage 1.7V to 3.3V LCD driving supply voltage 5.0V to 18.0V C-MOS technology Rectangle out look for COG Package Bumped chip / TCP
q q q q q q
02/08/26 -1-
NJU6824
s PAD LOCATION
SEGA126 SEGB126 SEGC126 SEGA127 SEGB127 SEGC127 SEGSA1 SEGSB1 SEGSC1 COM64 COM113 DMY41 DMY42 DMY43
DMY44 DMY45 DMY46 COM114
COM127 DMY47
DMY71
1
Note1) The same name PADs are shorted mutually in the LSI. Note2) The DMY PADs are electrically open. Chip Center Chip Size Chip Thickness Bump Size :X= 0m, Y= 0m :22.07mm x 2.55mm :625m 25m :28m x 110m(COM/SEG Output, DMY10 ~ DMY71), 60m x 100m(Interface), 28m x 100m(DMY0 ~ DMY9) :43m(Min) :14.0~22.5m (Typical 18m) :Au
Bump Pitch Bump Height Bump Material
Alignment marks a: 30m b: 6m c: 120m d: 27m Alignment mark coordinates X=-10866m, Y= 1106m X= 10866m, Y=-1106m b c b a c a d
CLK CLK FR FR FLM FLM CL CL VDD VDD VDD VDD VDD VDD VDD D15 D15 D14 D14 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 VSSA VSSA D7 D7 D6 D6 D5 D5 D4/SPOL D4/SPOL D3/SMODE D3/SMODE D2 D2 D1/SDA D1/SDA D0/SCL D0/SCL VDDA VDDA RDb RDb DMY6 WRb WRb DMY5 RS RS DMY4 CSb CSb DMY3 RESb RESb VSSA VSSA P/S P/S VDDA VDDA SEL68 SEL68 VSSA VSSA DMY2 DMY1 DMY0
d
-2-
NJU6824
VOUT VOUT VOUT VOUT VSSH VSSH VSSH VSSH VSSH VSSH VSSH VBA VBA VBA VBA VBA VBA VREF VREF VREF VREF VREF VREF VREG VREG VREG VREG VREG VREG V4 V4 V4 V4 V4 V4 V3 V3 V3 V3 V3 V3 V2 V2 V2 V2 V2 V2 V1 V1 V1 V1 V1 V1 VLCD VLCD VLCD VLCD VLCD VLCD VSSA VSSA V4A2 V4A2 VDDA VDDA V4A1 V4A1 VSSA VSSA V1A2 V1A2 VDDA VDDA V1A1 V1A1 VSS VSS VSS VSS VSS VSS VSS OSC2 OSC2 OSC1 OSC1
Y
X
-3-
DMY37 DMY36 DMY35 COM50
COM63 DMY34
DMY38 DMY39 DMY40 COM49 DMY9 DMY8 DMY7 C5C5C5C5C5C5C5+ C5+ C5+ C5+ C5+ C5+ C4C4C4C4C4C4C4+ C4+ C4+ C4+ C4+ C4+ C3C3C3C3C3C3+ C3+ C3+ C3+ C3+ C3+ C2C2C2C2C2C2C2+ C2+ C2+ C2+ C2+ C2+ C1C1C1C1C1C1C1+ C1+ C1+ C1+ C1+ C1+ VEE VEE VEE VEE VEE VEE VEE VOUT VOUT VOUT
COM0 SEGSA0 SEGSB0 SEGSC0 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1
NJU6824
Y
X
DMY10
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NJU6824
s PAD COORDINATES 1
Chip Size 22070m x 2550m (Chip Center 0m x 0m )
PAD Terminal No. 1 DMY0 2 DMY1 3 DMY2 4 VSSA 5 VSSA 6 SEL68 7 SEL68 8 VDDA 9 VDDA 10 P/S 11 P/S 12 VSSA 13 VSSA 14 RESb 15 RESb 16 DMY3 17 CSb 18 CSb 19 DMY4 20 RS 21 RS 22 DMY5 23 WRb 24 WRb 25 DMY6 26 RDb 27 RDb 28 VDDA 29 VDDA 30 D0/SCL 31 D0/SCL 32 D1/SDA 33 D1/SDA 34 D2 35 D2 36 D3/SMODE 37 D3/SMODE 38 D4/SPOL 39 D4/SPOL 40 D5 41 D5 42 D6 43 D6 44 D7 45 D7 46 VSSA 47 VSSA 48 D8 49 D8 50 D9 51 D9 X(m) -10642.5 -10599.5 -10556.5 -10475.5 -10402.5 -10293.0 -10220.0 -10110.5 -10037.5 -9928.0 -9855.0 -9745.5 -9672.5 -9563.0 -9490.0 -9380.5 -9271.0 -9198.0 -9088.5 -8979.0 -8906.0 -8796.5 -8687.0 -8614.0 -8504.5 -8395.0 -8322.0 -8212.5 -8139.5 -7993.5 -7920.5 -7774.5 -7701.5 -7555.5 -7482.5 -7336.5 -7263.5 -7117.5 -7044.5 -6898.5 -6825.5 -6679.5 -6606.5 -6460.5 -6387.5 -6241.5 -6168.5 -6022.5 -5949.5 -5803.5 -5730.5 Y(m) -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 PAD No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Terminal D10 D10 D11 D11 D12 D12 D13 D13 D14 D14 D15 D15 VDD VDD VDD VDD VDD VDD VDD CL CL FLM FLM FR FR CLK CLK OSC1 OSC1 OSC2 OSC2 VSS VSS VSS VSS VSS VSS VSS V1A1 V1A1 VDDA VDDA V1A2 V1A2 VSSA VSSA V4A1 V4A1 VDDA VDDA V4 A 2 X(m) -5584.5 -5511.5 -5365.5 -5292.5 -5146.5 -5073.5 -4927.5 -4854.5 -4708.5 -4635.5 -4489.5 -4416.5 -4197.5 -4124.5 -4051.5 -3978.5 -3905.5 -3832.5 -3759.5 -3613.5 -3540.5 -3394.5 -3321.5 -3175.5 -3102.5 -2956.5 -2883.5 -2701.0 -2628.0 -2409.0 -2336.0 -2044.0 -1971.0 -1898.0 -1825.0 -1752.0 -1679.0 -1606.0 -1460.0 -1387.0 -1277.5 -1204.5 -1095.0 -1022.0 -912.5 -839.5 -730.0 -657.0 -547.5 -474.5 -365.0 Y(m) -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 PAD No. 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Terminal V 4 A2 VSSA VSSA VLCD VLCD VLCD VLCD VLCD VLCD V1 V1 V1 V1 V1 V1 V2 V2 V2 V2 V2 V2 V3 V3 V3 V3 V3 V3 V4 V4 V4 V4 V4 V4 VREG VREG VREG VREG VREG VREG VREF VREF VREF VREF VREF VREF VBA VBA VBA VBA VBA VBA X(m) -292.0 -182.5 -109.5 0.0 73.0 146.0 219.0 292.0 365.0 511.0 584.0 657.0 730.0 803.0 876.0 1022.0 1095.0 1168.0 1241.0 1314.0 1387.0 1533.0 1606.0 1679.0 1752.0 1825.0 1898.0 2044.0 2117.0 2190.0 2263.0 2336.0 2409.0 2555.0 2628.0 2701.0 2774.0 2847.0 2920.0 3029.5 3102.5 3175.5 3248.5 3321.5 3394.5 3504.0 3577.0 3650.0 3723.0 3796.0 3869.0 Y(m) -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0
-5-
NJU6824
s PAD COORDINATES 2
Chip Size 22070m x 2550m (Chip Center 0m x 0m )
PAD No. 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 Terminal VSSH VSSH VSSH VSSH VSSH VSSH VSSH VOUT VOUT VOUT VOUT VOUT VOUT VOUT VEE VEE VEE VEE VEE VEE VEE C1+ C1+ C1+ C1+ C1+ C1+ C1C1C1C1C1C1C2+ C2+ C2+ C2+ C2+ C2+ C2C2C2C2C2C2C3+ C3+ C3+ C3+ C3+ C3+ X(m) 4051.5 4124.5 4197.5 4270.5 4343.5 4416.5 4489.5 4672.0 4745.0 4818.0 4891.0 4964.0 5037.0 5110.0 5292.5 5365.5 5438.5 5511.5 5584.5 5657.5 5730.5 5840.0 5913.0 5986.0 6059.0 6132.0 6205.0 6314.5 6387.5 6460.5 6533.5 6606.5 6679.5 6789.0 6862.0 6935.0 7008.0 7081.0 7154.0 7263.5 7336.5 7409.5 7482.5 7555.5 7628.5 7738.0 7811.0 7884.0 7957.0 8030.0 8103.0 Y(m) -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 PAD No. 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 Terminal C3C3C3C3C3C3C4+ C4+ C4+ C4+ C4+ C4+ C4C4C4C4C4C4C5+ C5+ C5+ C5+ C5+ C5+ C5C5C5C5 C5 C5 DMY7 DMY8 DMY9 DMY10 DMY11 DMY12 DMY13 DMY14 DMY15 DMY16 DMY17 DMY18 DMY19 DMY20 DMY21 DMY22 DMY23 DMY24 DMY25 DMY26 DMY27 X(m) 8212.5 8285.5 8358.5 8431.5 8504.5 8577.5 8687.0 8760.0 8833.0 8906.0 8979.0 9052.0 9161.5 9234.5 9307.5 9380.5 9453.5 9526.5 9636.0 9709.0 9782.0 9855.0 9928.0 10001.0 10110.5 10183.5 10256.5 10329.5 10402.5 10475.5 10556.5 10599.5 10642.5 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 Y(m) -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -1090.0 -881.5 -838.5 -795.5 -752.5 -709.5 -666.5 -623.5 -580.5 -537.5 -494.5 -451.5 -408.5 -365.5 -322.5 -279.5 -236.5 -193.5 -150.5 PAD No. 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 Terminal DMY28 DMY29 DMY30 DMY31 DMY32 DMY33 DMY34 COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 DMY35 DMY36 DMY37 DMY38 DMY39 DMY40 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 X(m) 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10845.0 10642.5 10599.5 10556.5 10513.5 10470.5 10427.5 10384.5 10341.5 10298.5 10255.5 10212.5 10169.5 10126.5 10083.5 10040.5 9997.5 9954.5 9911.5 9868.5 9825.5 9782.5 9739.5 9696.5 9653.5 9610.5 9567.5 9524.5 Y(m) -107.5 -64.5 -21.5 21.5 64.5 107.5 150.5 193.5 236.5 279.5 322.5 365.5 408.5 451.5 494.5 537.5 580.5 623.5 666.5 709.5 752.5 795.5 838.5 881.5 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0
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NJU6824
s PAD COORDINATES 3
Chip Size 22070m x 2550m (Chip Center 0m x 0m )
PAD No. 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 Terminal COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEGSA0 SEGSB0 SEGSC0 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2 SEGA2 SEGB3 SEGC3 SEGA4 SEGB4 SEGC4 SEGA5 SEGB5 SEGC5 SEGA6 SEGB6 SEGC6 SEGA7 X(m) 9481.5 9438.5 9395.5 9352.5 9309.5 9266.5 9223.5 9180.5 9137.5 9094.5 9051.5 9008.5 8965.5 8922.5 8879.5 8836.5 8793.5 8750.5 8707.5 8664.5 8621.5 8578.5 8535.5 8492.5 8449.5 8406.5 8363.5 8320.5 8277.5 8234.5 8191.5 8148.5 8105.5 8062.5 8019.5 7976.5 7933.5 7890.5 7847.5 7804.5 7761.5 7718.5 7675.5 7632.5 7589.5 7546.5 7503.5 7460.5 7417.5 7374.5 7331.5 Y(m) 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 PAD No. 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 Terminal SEGB7 SEGC7 SEGA8 SEGB8 SEGC8 SEGA9 SEGB9 SEGC9 SEGA10 SEGB10 SEGC10 SEGA11 SEGB11 SEGC11 SEGA12 SEGB12 SEGC12 SEGA13 SEGB13 SEGC13 SEGA14 SEGB14 SEGC14 SEGA15 SEGB15 SEGC15 SEGA16 SEGB16 SEGC16 SEGA17 SEGB17 SEGC17 SEGA18 SEGB18 SEGC18 SEGA19 SEGB19 SEGC19 SEGA20 SEGB20 SEGC20 SEGA21 SEGB21 SEGC21 SEGA22 SEGB22 SEGC22 SEGA23 SEGB23 SEGC23 SEGA24 X(m) 7288.5 7245.5 7202.5 7159.5 7116.5 7073.5 7030.5 6987.5 6944.5 6901.5 6858.5 6815.5 6772.5 6729.5 6686.5 6643.5 6600.5 6557.5 6514.5 6471.5 6428.5 6385.5 6342.5 6299.5 6256.5 6213.5 6170.5 6127.5 6084.5 6041.5 5998.5 5955.5 5912.5 5869.5 5826.5 5783.5 5740.5 5697.5 5654.5 5611.5 5568.5 5525.5 5482.5 5439.5 5396.5 5353.5 5310.5 5267.5 5224.5 5181.5 5138.5 Y(m) 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 PAD No. 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 Terminal SEGB24 SEGC24 SEGA25 SEGB25 SEGC25 SEGA26 SEGB26 SEGC26 SEGA27 SEGB27 SEGC27 SEGA28 SEGB28 SEGC28 SEGA29 SEGB29 SEGC29 SEGA30 SEGB30 SEGC30 SEGA31 SEGB31 SEGC31 SEGA32 SEGB32 SEGC32 SEGA33 SEGB33 SEGC33 SEGA34 SEGB34 SEGC34 SEGA35 SEGB35 SEGC35 SEGA36 SEGB36 SEGC36 SEGA37 SEGB37 SEGC37 SEGA38 SEGB38 SEGC38 SEGA39 SEGB39 SEGC39 SEGA40 SEGB40 SEGC40 SEGA41 X(m) 5095.5 5052.5 5009.5 4966.5 4923.5 4880.5 4837.5 4794.5 4751.5 4708.5 4665.5 4622.5 4579.5 4536.5 4493.5 4450.5 4407.5 4364.5 4321.5 4278.5 4235.5 4192.5 4149.5 4106.5 4063.5 4020.5 3977.5 3934.5 3891.5 3848.5 3805.5 3762.5 3719.5 3676.5 3633.5 3590.5 3547.5 3504.5 3461.5 3418.5 3375.5 3332.5 3289.5 3246.5 3203.5 3160.5 3117.5 3074.5 3031.5 2988.5 2945.5 Y(m) 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0
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NJU6824
s PAD COORDINATES 4
Chip Size 22070m x 2550m (Chip Center 0m x 0m )
PAD No. 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 Terminal SEGB41 SEGC41 SEGA42 SEGB42 SEGC42 SEGA43 SEGB43 SEGC43 SEGA44 SEGB44 SEGC44 SEGA45 SEGB45 SEGC45 SEGA46 SEGB46 SEGC46 SEGA47 SEGB47 SEGC47 SEGA48 SEGB48 SEGC48 SEGA49 SEGB49 SEGC49 SEGA50 SEGB50 SEGC50 SEGA51 SEGB51 SEGC51 SEGA52 SEGB52 SEGC52 SEGA53 SEGB53 SEGC53 SEGA54 SEGB54 SEGC54 SEGA55 SEGB55 SEGC55 SEGA56 SEGB56 SEGC56 SEGA57 SEGB57 SEGC57 SEGA58 X(m) 2902.5 2859.5 2816.5 2773.5 2730.5 2687.5 2644.5 2601.5 2558.5 2515.5 2472.5 2429.5 2386.5 2343.5 2300.5 2257.5 2214.5 2171.5 2128.5 2085.5 2042.5 1999.5 1956.5 1913.5 1870.5 1827.5 1784.5 1741.5 1698.5 1655.5 1612.5 1569.5 1526.5 1483.5 1440.5 1397.5 1354.5 1311.5 1268.5 1225.5 1182.5 1139.5 1096.5 1053.5 1010.5 967.5 924.5 881.5 838.5 795.5 752.5 Y(m) 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 PAD No. 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 Terminal SEGB58 SEGC58 SEGA59 SEGB59 SEGC59 SEGA60 SEGB60 SEGC60 SEGA61 SEGB61 SEGC61 SEGA62 SEGB62 SEGC62 SEGA63 SEGB63 SEGC63 SEGA64 SEGB64 SEGC64 SEGA65 SEGB65 SEGC65 SEGA66 SEGB66 SEGC66 SEGA67 SEGB67 SEGC67 SEGA68 SEGB68 SEGC68 SEGA69 SEGB69 SEGC69 SEGA70 SEGB70 SEGC70 SEGA71 SEGB71 SEGC71 SEGA72 SEGB72 SEGC72 SEGA73 SEGB73 SEGC73 SEGA74 SEGB74 SEGC74 SEGA75 X(m) 709.5 666.5 623.5 580.5 537.5 494.5 451.5 408.5 365.5 322.5 279.5 236.5 193.5 150.5 107.5 64.5 21.5 -21.5 -64.5 -107.5 -150.5 -193.5 -236.5 -279.5 -322.5 -365.5 -408.5 -451.5 -494.5 -537.5 -580.5 -623.5 -666.5 -709.5 -752.5 -795.5 -838.5 -881.5 -924.5 -967.5 -1010.5 -1053.5 -1096.5 -1139.5 -1182.5 -1225.5 -1268.5 -1311.5 -1354.5 -1397.5 -1440.5 Y(m) 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 PAD No. 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 Terminal SEGB75 SEGC75 SEGA76 SEGB76 SEGC76 SEGA77 SEGB77 SEGC77 SEGA78 SEGB78 SEGC78 SEGA79 SEGB79 SEGC79 SEGA80 SEGB80 SEGC80 SEGA81 SEGB81 SEGC81 SEGA82 SEGB82 SEGC82 SEGA83 SEGB83 SEGC83 SEGA84 SEGB84 SEGC84 SEGA85 SEGB85 SEGC85 SEGA86 SEGB86 SEGC86 SEGA87 SEGB87 SEGC87 SEGA88 SEGB88 SEGC88 SEGA89 SEGB89 SEGC89 SEGA90 SEGB90 SEGC90 SEGA91 SEGB91 SEGC91 SEGA92 X(m) -1483.5 -1526.5 -1569.5 -1612.5 -1655.5 -1698.5 -1741.5 -1784.5 -1827.5 -1870.5 -1913.5 -1956.5 -1999.5 -2042.5 -2085.5 -2128.5 -2171.5 -2214.5 -2257.5 -2300.5 -2343.5 -2386.5 -2429.5 -2472.5 -2515.5 -2558.5 -2601.5 -2644.5 -2687.5 -2730.5 -2773.5 -2816.5 -2859.5 -2902.5 -2945.5 -2988.5 -3031.5 -3074.5 -3117.5 -3160.5 -3203.5 -3246.5 -3289.5 -3332.5 -3375.5 -3418.5 -3461.5 -3504.5 -3547.5 -3590.5 -3633.5 Y(m) 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0
-8-
NJU6824
s PAD COORDINATES 5
Chip Size 22070m x 2550m (Chip Center 0m x 0m )
PAD No. 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 Terminal SEGB92 SEGC92 SEGA93 SEGB93 SEGC93 SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 SEGA96 SEGB96 SEGC96 SEGA97 SEGB97 SEGC97 SEGA98 SEGB98 SEGC98 SEGA99 SEGB99 SEGC99 SEGA100 SEGB100 SEGC100 SEGA101 SEGB101 SEGC101 SEGA102 SEGB102 SEGC102 SEGA103 SEGB103 SEGC103 SEGA104 SEGB104 SEGC104 SEGA105 SEGB105 SEGC105 SEGA106 SEGB106 SEGC106 SEGA107 SEGB107 SEGC107 SEGA108 SEGB108 SEGC108 SEGA109 X(m) -3676.5 -3719.5 -3762.5 -3805.5 -3848.5 -3891.5 -3934.5 -3977.5 -4020.5 -4063.5 -4106.5 -4149.5 -4192.5 -4235.5 -4278.5 -4321.5 -4364.5 -4407.5 -4450.5 -4493.5 -4536.5 -4579.5 -4622.5 -4665.5 -4708.5 -4751.5 -4794.5 -4837.5 -4880.5 -4923.5 -4966.5 -5009.5 -5052.5 -5095.5 -5138.5 -5181.5 -5224.5 -5267.5 -5310.5 -5353.5 -5396.5 -5439.5 -5482.5 -5525.5 -5568.5 -5611.5 -5654.5 -5697.5 -5740.5 -5783.5 -5826.5 Y(m) 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 PAD No. 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 Terminal SEGB109 SEGC109 SEGA110 SEGB110 SEGC110 SEGA111 SEGB111 SEGC111 SEGA112 SEGB112 SEGC112 SEGA113 SEGB113 SEGC113 SEGA114 SEGB114 SEGC114 SEGA115 SEGB115 SEGC115 SEGA116 SEGB116 SEGC116 SEGA117 SEGB117 SEGC117 SEGA118 SEGB118 SEGC118 SEGA119 SEGB119 SEGC119 SEGA120 SEGB120 SEGC120 SEGA121 SEGB121 SEGC121 SEGA122 SEGB122 SEGC122 SEGA123 SEGB123 SEGC123 SEGA124 SEGB124 SEGC124 SEGA125 SEGB125 SEGC125 SEGA126 X(m) -5869.5 -5912.5 -5955.5 -5998.5 -6041.5 -6084.5 -6127.5 -6170.5 -6213.5 -6256.5 -6299.5 -6342.5 -6385.5 -6428.5 -6471.5 -6514.5 -6557.5 -6600.5 -6643.5 -6686.5 -6729.5 -6772.5 -6815.5 -6858.5 -6901.5 -6944.5 -6987.5 -7030.5 -7073.5 -7116.5 -7159.5 -7202.5 -7245.5 -7288.5 -7331.5 -7374.5 -7417.5 -7460.5 -7503.5 -7546.5 -7589.5 -7632.5 -7675.5 -7718.5 -7761.5 -7804.5 -7847.5 -7890.5 -7933.5 -7976.5 -8019.5 Y(m) 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 PAD No. 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 Terminal SEGB126 SEGC126 SEGA127 SEGB127 SEGC127 SEGSA1 SEGSB1 SEGSC1 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 X(m) -8062.5 -8105.5 -8148.5 -8191.5 -8234.5 -8277.5 -8320.5 -8363.5 -8406.5 -8449.5 -8492.5 -8535.5 -8578.5 -8621.5 -8664.5 -8707.5 -8750.5 -8793.5 -8836.5 -8879.5 -8922.5 -8965.5 -9008.5 -9051.5 -9094.5 -9137.5 -9180.5 -9223.5 -9266.5 -9309.5 -9352.5 -9395.5 -9438.5 -9481.5 -9524.5 -9567.5 -9610.5 -9653.5 -9696.5 -9739.5 -9782.5 -9825.5 -9868.5 -9911.5 -9954.5 -9997.5 -10040.5 -10083.5 -10126.5 -10169.5 -10212.5 Y(m) 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0
-9-
NJU6824
s PAD COORDINATES 6
Chip Size 22070m x 2550m (Chip Center 0m x 0m )
PAD No. 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 Terminal COM107 COM108 COM109 COM110 COM111 COM112 COM113 DMY41 DMY42 DMY43 DMY44 DMY45 DMY46 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 DMY47 DMY48 DMY49 DMY50 DMY51 DMY52 DMY53 DMY54 DMY55 DMY56 DMY57 DMY58 DMY59 DMY60 DMY61 DMY62 DMY63 DMY64 DMY65 DMY66 DMY67 DMY68 DMY69 DMY70 X(m) -10255.5 -10298.5 -10341.5 -10384.5 -10427.5 -10470.5 -10513.5 -10556.5 -10599.5 -10642.5 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 -10845.0 Y(m) 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 881.5 838.5 795.5 752.5 709.5 666.5 623.5 580.5 537.5 494.5 451.5 408.5 365.5 322.5 279.5 236.5 193.5 150.5 107.5 64.5 21.5 -21.5 -64.5 -107.5 -150.5 -193.5 -236.5 -279.5 -322.5 -365.5 -408.5 -451.5 -494.5 -537.5 -580.5 -623.5 -666.5 -709.5 -752.5 -795.5 -838.5 PAD No. 817 Terminal DMY71 X(m) -10845.0 Y(m) -881.5 PAD No. Terminal X(m) Y(m)
- 10 -
NJU6824
s BLOCK DIAGRAM
SEGSA0 SEGSB0 SEGSC0
SEGA127 SEGB127 SEGC127 SEGSA1 SEGSB1 SEGSC1
VSS VSSA VVDDA VDD VLCD, V1 -V4 V1 A1 , V1 A2 , V4 A1 , V4 A2 C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VEE VREF VBA VREG 4 5
Segment Driver Gradation Circuit Data Latch Circuit
Common Driver
Shift Register
Voltage booster
COM0
VSSH
Display Data RAM (DD RAM) 128x128x(4+4+4)bit
D15 D14 D13 D12 D11 D10 D8 D7 D6 D5 D4/SPOL D3/SMODE D2 D1/SDA D0/SCL Pole Control I/O Buffer D9 RAM Interface
Column Address Decoder Display Timing Generator FR FLM CL
Column Address Counter
Column Address Register Oscillator
Line Counter
Voltage regulator
Initial Display Line Register
Row Address Decoder
Row Address Register
Line Address Decoder
Row Address Counter
COM127
SEGA0 SEGB0 SEGC0
CLK OSC2 OSC1
Bus Holder
Instruction Decoder
Register Read Control
Internal Bus
MPU Interface
CSb
RS
RDb
WRb
P/S
SEL68 RESb
- 11 -
NJU6824
! POWER SUPPLY CIRCUITS BLOCK DIAGRAM
VBA
Reference Voltage Generator Voltage regulator
+ -
+ + + + -
VLCD
VREG VREF + Gain Control (1x-6x)
V1
V2
E.V.R 1/2VREG
V3
+ -
V4
EVR register V1/V4 Bias Voltage Adjustment
Boost level register
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VEE
V1A1 V1A2 V4A1 V4A2
Voltage Booster
VOUT
- 12 -
NJU6824
s TERMINAL DESCRIPTION 1
No. 64~70 83~89 154~160 8,9, 28,29, 92,93, 100,101 4,5, 12,13, 46,47, 96,97, 104,105 106~111 112~117 118~123 124~129 130~135 Symbol VDD VSS VSSH VDDA I/O Power Power Power Power Function Power supply for logic circuits GND for logic circuits GND for high voltage circuits This terminal is internally connected to the VDD level. *This terminal is used to fix the selection terminals to the VDD level. Note) Do not use this terminal for a main power supply. This terminal is internally connected to the VSS level. *This terminal is used to fix the selection terminals to the VSS level. Note) Do not use this terminal for a main GND. LCD driving voltages *When the internal voltage booster is not used, external LCD driving voltages (V1 to V4 and VLCD) must be supplied on these terminals. The external voltages must be maintained with the following relation. VSSVSSA
Power
VLCD V1 V2 V3 V4
Power/O
175~180 181~186 187~192 193~198 199~204 205~210 211~216 217~222 223~228 229~234 148~153 142~147 168~174 161~167 136~141 90,91 94,95 98,99 102,103 14,15 6,7
C 1+ C 1C 2+ C 2C 3+ C 3C 4+ C 4C 5+ C 5VBA VREF VEE VOUT VREG V1A1 V1A2 V4A1 V4A2 RESb SEL68
O O O O O O I Power Power/O O I I I I
L 80 series
- 13 -
NJU6824
s TERMINAL DESCRIPTION 2
No. 30,31 Symbol D0/SCL I/O I/O Function Parallel interface: D7 to D0 : 8-bit bi-directional bus * In the parallel interface mode (P/S="1"), these terminals connect to 8-bit bi-directional MPU bus. Serial interface: SDA : serial data SCL : serial clock SMODE : 3-/4-line serial interface mode selection SPOL : RS polarity selection (in the 3-line serial interface mode) *In the 3-/4-line serial interface mode (P/S="0"), the D0 terminal is assigned to the SCL and the D1 terminal to the SDA. *In the 3-line serial interface mode, the D4 terminal is assigned to the SPOL. *Serial data on the SDA is fetched at the rising edge of the SCL signal in the order of the D7, D6...D0, and the fetched data is converted into 8-bit parallel data at the falling edge of the 8th SCL signal. *The SCL signal must be set to "0" after data transmissions or during non-access. 8-bit bi-directional bus *In the 16-bit data bus mode, these terminals are assigned to the upper 8-bit data bus. *In the serial interface mode or 8-bit data bus mode of the parallel interface, these terminals must be fixed to "1" or "0".
32,33
D1/SDA
I/O
36,37
D3/SMODE
I/O
38,39
D4/SPOL
I/O
34,35 40,41 42,43 44,45
D2 D5 D6 D7
I/O
48,49 50,51 52,53 54,55 56,57 58,59 60,61 62,63 17,18 20,21
D8 D9 D10 D11 D12 D13 D14 D15 CSb RS
I/O
I I
Chip select Active "0" Resister select *This signal distinguishes transferred data as an instruction or display data as follows. RS Distinct. H Instruction L Display data
26,27
RDb (E)
I
80 series MPU interface (P/S="1", SEL68="0") RDb signal. Active "0". 68 series MPU interface (P/S="1", SEL68="1") Enable signal. Active "1". 80 series MPU interface (P/S="1", SEL68="0") WRb signal. Active "0". 68 series MPU interface (P/S="1", SEL68="1") R/W signal. R/W H L Status Read Write
23,24
WRb (R/W)
I
- 14 -
NJU6824
s TERMINAL DESCRIPTION 3
No. 10,11 Symbol P/S I/O I Function Parallel / serial interface mode selection
P/S H L Chip Select CSb CSb Data/ Instruction RS RS Data D0 ~ D7 SDA (D1) Read/Write RDb, WRb Write only Serial clock SCL (D0)
71,72 73,74 75,76 77,78 79,80 81,82
CL FLM FR CLK OSC1 OSC2
O O O O I O
*Since the D15 to D5 and D2 terminals are in the high impedance in the serial inter face mode (P/S="0"), they must be fixed to "1" or "0". The RDb and WRb terminals also must be "1" or "0". This terminal must be opened. This terminal must be opened. This terminal must be opened. This terminal must be opened. OSC * When the internal oscillator clock is used, OSC1 terminal must be fixed to "1" or "0", and the OSC2 terminal must be opened. When the oscillation frequency from the internal oscillator is adjusted by an external resistor between OSC1 terminal and OSC2. * When an external oscillator is used, external clock is input to the OSC1 terminal or an external resistor is connected between the OSC1 and OSC2 terminals.
- 15 -
NJU6824
s TERMINAL DESCRIPTION 4
No. 336~719 Symbol SEGA0 ~ SEGA127, SEGB0 ~ SEGB127, SEGC0 ~ SEGC127 I/O O Function Segment output REV Mode Normal Reverse Turn-off 0 1 Turn-on 1 0
*These terminals output LCD driving waveforms in accordance with the combination of the FR signal and display data. In the B/W mode
FR signal Display data Normal display mode Reverse display mode
V2 VLCD
VLCD V2
V3 VSS
VSS V3
333,720 334,721 335,722 332~283, 276~263, 723~772, 779~792
SEGSA0, SEGSA1 SEGSB0, SEGSB1 SEGSC0, SEGSC1 COM0 ~ COM127
O O
Icon segment output terminal *These terminals are assigned at both edge of normal segment output terminals line for out line frame display. Common output *These terminals output LCD driving waveforms in accordance with the combination of the FR signal and scanning data. Data H L H L FR H H L L Output level VSS V1 VLCD V4
(Terminal No. 1~3,16,19,22,25,235~262,277~282,773~778,793~817 are dummy.)
- 16 -
NJU6824
s Functional Description
(1) MPU Interface (1-1) Selection of parallel / serial interface mode The P/S terminal is used to select parallel or serial interface mode as shown in the following table. In the serial interface mode, it is not possible to read out display data from the DDRAM and status from the internal registers. Table1 P/S P/S mode CSb RS H Parallel I/F CSb RS L Serial I/F CSb RS Note 1) " -" : Fix to "1" or "0".
RDb RDb -
WRb WRb -
SEL68 SEL68 -
SDA SDA
SCL SCL
Data D7-D0 (D15-D0) -
(1-2) Selection of MPU interface type In the parallel interface mode, the SEL68 terminal is used to select 68- or 80-series MPU interface type as shown in the following table. Table2 SEL68 MPU type H 68 series MPU L 80 series MPU
CSb CSb CSb
RS RS RS
RDb E RDb
WRb R/W WRb
Data D7-D0 (D15-D0) D7-D0 (D15-D0)
(1-3) Data distinction In the parallel interface mode, the combination of RS, RDb, and WRb (R/W) signals distinguishes transferred data between the LSI and MPU as instruction or display data, as shown in the following table. Table3 RS H H L L 68 series R/W H L H L 80 series RDb WRb L H H L L H H L Function Read out instruction data Write instruction data Read out display data Write display data
(1-4) Selection of serial interface mode In the serial interface mode, the SMODE terminal is used to select the 3- or 4-line serial interface mode as shown in the following table. Table4 SMODE H L
Serial interface mode 3-line 4-line
- 17 -
NJU6824
(1-5) 4-line serial interface mode In the 4-line serial interface mode, when the chip select is active (CSb="0"), the SDA and the SCL are enabled. When the chip select is not active (CSb="1"), the SDA and the SCL are disabled and the internal shift register and the counter are being initialized. The 8-bit serial data on the SDA is fetched at the rising edge of the SCL signal (serial clock) in order of the D7, D6...D0, and the fetched data is converted into the 8-bit parallel data at the rising edge of the 8th SCL signal. In the 4-line serial interface mode, the transferred data on the SDA is distinguished as display data or instruction data in accordance with the condition of the RS signal. Table5 Data distinction Instruction data Display data
RS H L
Since the serial interface operation is sensitive to external noises, the SCL should be set to "0" after data transmissions or during non-access. To release a mal-function caused by the external noises, the chip-selected status should be released (CSb="1") after each of the 8-bit data transmissions. The following figure illustrates the interface timing for the 4-line serial interface operation. CSb RS SDA SCL 1 2 Fig1 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 VALID D0
4-line serial interface timing
(1-6) 3-line serial interface mode In the 3-line serial interface mode, when the chip select is active (CSb="0"), the SDA and SCL are enabled. When the chip select is not active (CSb="1"), the SDA and SCL are disabled and the internal shift register and counter are being initialized. 9-bit serial data on the SDA is fetched at the rising edge of the SCL signal in order of the RS, D7, D6...D0, and the fetched data is converted into the 9-bit parallel data at the rising edge of the 9th SCL signal. In the 3-line serial interface mode, data on the SDA is distinguished as display data or instruction data in accordance with the condition of the RS bit of the SDA data and the status of the SPOL, as follows. Table6 RS L H SPOL=L Data distinction Display data Instruction data RS L H SPOL=H Data distinction Instruction data Display data
- 18 -
NJU6824
Since the serial interface operation is sensitive to external noises, the SCL must be set to "0" after data transmissions or during non-access. To release a mal-function caused by the external noises, the chipselected status should be released (CSb="1") after each of 9-bit data transmissions. The following figure illustrates the interface timing of the 3-line serial interface operation.
CSb SDA SCL 1 2 Fig2 3 4 5 6 7 8 9 RS D7 D6 D5 D4 D3 D2 D1 D0
3-line serial interface timing
- 19 -
NJU6824
(2) Access to the DDRAM When the CSb signal is "0", the transferred data from MPU is written into the DDRAM or instruction register in accordance with the condition of the RS signal. When the RS signal is "1", the transferred data is distinguished as display data. After the "column address" and "row address" instructions are executed, the display data can be written into the DDRAM by the "display data write" instruction. The display data is written at the rising edge of the WRb signal in the 80 series MPU mode, or at the falling edge of the E signal in the 68 series MPU mode. Table6 RS Data L Display RAM Data H Internal Command Register
In the sequence of the "display data read" operation, the transferred data from MPU is temporarily held in the internal bus-holder, then transferred to the internal data-bus. When the "display data read" operation is executed just after the "column address" and "row address" instructions or "display data write" instruction, unexpected data on the bus-holder is read out at the 1st execution, then the data of designated DDRAM address is read out from the 2nd execution. For this reason, a dummy read cycle must be executed to avoid the unexpected 1st data read.
Display data write operation D0 to D15 WRb Internal Bus Holder WRb n n+1 n+2 n+3 n+4 n n+1 n+2 n+3 n+4
Display data read operation WRb D0 to D7(D0 to D15) n Address Set n RDb Fig3 Note) In the16-bit data bus mode, instruction data must be 16-bit as well as the display data. Dummy Read n Data Read n Address n+1 Data Read n+1 Address n+2 Data Read n+2 Address
- 20 -
NJU6824
(3) Access to the instruction register Each instruction resisters is assigned to each address between 0H and FH, and the content of the instruction register can be read out by the combination of the "Instruction resister address" and "Instruction resister read". WRb D0 to D7 M
Instruction resister address set
m
Instruction resister contents read
N
Instruction resister address set
n
Instruction resister contents read
RDb Fig4 (4) 8-/16-bit data bus length for display data (in the parallel interface mode) The 8- or 16-bit data bus length for display data is determined by the "WLS" of the "Data bus length" instruction. In the 16-bit data bus mode, instruction data must be 16-bit data (D15 to D0) as well as display data. However, for the access to the instruction register, the only lower 8-bit data (D7 to D0) of the 16-bit data is valid. For the access to the DDRAM, all of the 16-bit data (D15 to D0) is valid. Table8 WLS L H Data bus length mode 8-bit 16-bit
(5) Initial display line register The initial display line resister specifies the line address, corresponding to the initial COM line, by the "Initial display line" instruction. The initial COM line signifies the common driver, starting scanning the display data in the DDRAM, and specified by the "Initial COM line" instruction. The line address, established in the initial display line resister, is preset into the line counter whenever the FLM signal becomes "1". At the rising edge of the CL signal, the line counter is counted-up and addressed 384bit display data corresponding to the counted-up line address, is latched into the data latch circuit. At the falling edge of the CL signal, the latched data outputs to the segment drivers.
- 21 -
NJU6824
(6) DDRAM mapping The DDRAM is capable of 1,536-bit (12-bit x 128-segment) for the column address and 128-bit for the row address. In the gradation mode, each pixel for RGB corresponds to successive 3-segment drivers, and each segment driver has 16-gradation. Therefore, the LSI can drive up to 128x128 pixels in 4096-color display (16-gradation x 16-gradation x 16-gradation). In 8-bit access mode(C256 mode) for DDRAM, sequential twice accesses to DDRAM complete one pixel data access. Therefore, it must be accessed with a couple of operation. # In the 8-bit data bus length mode
column-address
0H 0H 7bit 5bit 7bit
7FH 5bit
row-address
7FH
7bit
5bit
column-address
7bit
5bit
ABS='1' 0H 4bit
0H 8bit 4bit
7FH 8bit
row-address
7FH
4bit
8bit
column-address
4bit
8bit
C256='1' 0H
0H 8bit
1H 8bit
7EH 8bit
7FH 8bit
row-address
7FH
8bit
8bit Fig5
8bit
8bit
- 22 -
NJU6824
# In the 16-bit data bus length mode
column-address
0H
0H 12bit
7FH 12bit
row-address
7FH
12bit Fig6
12bit
In the B&W mode, only MSB data from each 4-bit display data group in the DDRAM is used. Therefore, 384 x 128 pixels in the B&W and 128 x 128 pixels in the 8-gradation are available. The range of the column address varies depending on data bus length. The range between 00H and 7FH is used in the 8-bit or 16-bit data bus length. The DDRAM is accessing 8-bit or 16-bit unit addressed by column and row address. In the 8-bit or 16-bit data bus length mode, over 80H address setting is prohibited. The increments for the column address and row address are set to the auto-increment mode by programming the "HV", "XD" and "YD" registers of the "Increment control" instruction. In this mode, the contents of the column address and row address counters automatically increment whenever the DDRAM is accessed. The column address and row address counters, independent of the line counter. They are used to designate the column and row addresses for the display data transferred from MPU. On the other hand, the line counter is used to generate the line address, and output display data to the segment drivers, being synchronized with the display control timing of the FLM and CL signals.
- 23 -
RAM Map 1 WLS SEG0 ABS 256 Palette A C3 C2 C1 C0 C3 C2 C1 C0 A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 X=00H
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
SEG1 Palette C X=01H X=01H X=00H (Lower) X=01H (Upper) X=01H (Upper) X=01H (Lower) X=01H (Lower) Palette A Palette B Palette C Palette A A0 B3
SEG126 Palette B C3 B2 B1 B0 X=7EH X=7EH X=7EH (Upper) X=7EH (Upper) X=7EH (Lower) X=7EH (Lower) Palette C C2 C1
SEG127
Mode
Palette B
Palette A
Palette B
Palette C
C0
C3
C2
C1 SEG126 Palette B Palette C C3 C2 C1 A1 A0 B3 B2 B1 B0 X=7EH -
1 16bit 1
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 0 X=00H (Upper) X=00H (Lower) 0 X=00H (Upper) 0 X=00H
0
X=7FH
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
X=7FH
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 8bit 0
X=7FH (Upper)
X=7FH (Lower)
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1
X=7FH (Upper)
X=7FH (Lower)
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
RAM Map 2 (256 Color Mode) W LS SEG0 ABS 256 Palette A C3 C2 C1 C0 A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 Palette B Palette C Palette A A1 A0 B3 SEG1 Palette B C3 B2 B1 B0 Palette C C2 C1 C0 A3 Palette A A2 Mode
SEG127
Palette A
Palette B
Palette C
C0
C3
C2
C1 X=01H - D7 D6 D5 D4 D3 D2 D1 D0 -
8bit X 1 -
0
X=00H - D7 D6 D5 D4 D3 D2 D1 D0 -
X=7FH
D7 D6 D5 D4 D3 D2 D1 D0
-
-
-
-
D7 D6 D5 D4 D3 D2 D1 D0
SWAP SWAP Palette A C3 A3 A2 A1 A0 B3 B2 B1 SEGAx SEGBx SEGBx SEGCx B0 Palette B Palette C C2 C1 SEGCx SEGAx C0
0 1
Note1) In the 256-color mode, the vacant LSB bit is filled with "1". Note2) The function of 256-color mode is different from that of fixed 8-gradation mode (fixed 256-color mode). Note3) The written data in the DD RAM in "C256"=0 is not compatible with the data in "C256"=1. Note4) In the 256-color mode, only 8-bit length mode is available, but 16-bit is not. Note5) In 8-bit access mode(C256 mode) for DDRAM, sequential twice accesses to DDRAM complete one pixel data access. Therefore, it must be accessed with a couple of operation.
NJU6824
Note6) In 8-bit access mode(non C256 mode) for DDRAM, After address set up display data will be written in an order from lower to higher. This order has no relation with address direction of RAM access (Display rotation)
C0
A3
A2
A1
A0
B3
B2
B1
B0
C0
A3
A2
A1
A0
B3
B2
B1
B0
- 24 -
NJU6824
Icon Segment Map 1 WLS SEGS0 ABS 256 Palette A C3 C2 C1 C0 C3 C2 C1 A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 X=00H X=00H X=00H (Upper) X=00H (Lower) X=00H (Lower) X=01H (Upper) X=00H (Upper) X=01H (Upper) X=01H X=01H (Lower) X=01H (Lower) X=01H B0 Palette B Palette C Palette A Palette B Palette C C0 SEGS1 Mode
1 0 0 0 0 0 1 0 1 16bit 1 0 8bit 0
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Icon Segment Map 2 (256 Color Mode) WLS SEGS0 ABS 256 Palette A C3 C2 C1 A3 A2 A1 A0 B3 B2 B1 B0 Palette B Palette C C0 A3 Palette A A2 A1 A0 B3 SEGS1 Palette B C3 B2 B1 B0 Palette C C2 C1 C0 Mode
8bit -
0
X 1
X=00H D7 D6 D5 D4 D3 D2 D1 D0 -
X=01H D7 D6 D5 D4 D3 D2 D1 D0
SWAP SWAP Palette A Palette B C3 A0 B3 B2 B1 B0 SEGSBx SEGSBx A3 A2 A1 SEGSAx SEGSCx Palette C C2 C1 C0 SEGSCx SEGSAx
0 1
Note1) In the 256-color mode, the vacant LSB bit is filled with "1". Note2) The function of 256-color mode is different from that of fixed 8-gradation mode (fixed 256-color mode). Note3) The written data in the DD RAM in "C256"=0 is not compatible with the data in "C256"=1. Note4) In the 256-color mode, only 8-bit length mode is available, but 16-bit is not. Note5) In 8-bit access mode(C256 mode) for DDRAM, sequential twice accesses to DDRAM complete one pixel data access. Therefore, it must be accessed with a couple of operation.
Note6) In 8-bit access mode(non C256 mode) for DDRAM, After address set up display data will be written in an order from lower to higher. This order has no relation with address direction of RAM access (Display rotation)
- 25 -
NJU6824
(7) Window addressing mode Window area must be designated before RAM access. In the window addressing mode, the address space of the DDRAM designated by the start and end point is defined. The start point is determined by the "column address" and "row address" instructions, and the end point is determined by the "Window end column address "and "Window end row address" instructions. The setting for the window addressing is listed in the following. 1. "Increment control" instruction set (HV, XD, YD) 2. Set the start point by the "column address" and "row address" instructions 3. Set the end point by the "Window end column address" and "Window end row address" instructions 4. Enable to access to the DDRAM in the window addressing mode In addition, the read-modify-write operation is available by setting "AIM" register to "L" in the "Increment control" instruction. For the window area designation, the address directions of RAM (HV, XD, YD) must be set first, and Column address and Row of Start point must be set second, Column address and Row of Stop point must be set third, then RAM should be accessed. Low address must be set first and High address must be set second in all of addresses. The directions of HV, XD, YD should be check to keep the area in RAM. And in the window addressing mode, the following start and end point must be maintained to abide a malfunction. column address
(X, Y) Start point row address
Window display area
End point (X, Y) Whole DDRAM area
Fig7 (8) Reverse display ON/OFF The "Reverse display ON/OFF" function is used to reverse the display data without changing the contents of the DDRAM. Table9 REV 0 1 DDRAM data Display data 0 0 1 1 0 1 1 0
Display Normal Reverse
(9) Address directions of RAM access (Display rotation) The bellow picture shows display image after set of HV, XD and YD for address directions. The display data from CPU can be written into RAM with rotation to 90 degrees or 180 degrees or 270 degrees, and also mirrored. The address directions of RAM access is set by HV, XD and YD. * : The segments of Icon are not rotated.
- 26 -
NJU6824
No.HVXDYD
(Xs, Ys)
Data writing direction
Display image
Valid address
Xs < Xe 1000 Ys < Ye (Xe, Ye) (Xe, Ye) Xs < Xe 2001 Ys > Ye (Xs, Ys) (Xs, Ys) Xs > Xe 3010 Ys < Ye (Xe, Ye) (Xe, Ye) Xs > Xe 4011 Ys > Ye (Xs, Ys) (Xs, Ys) Xs < Xe 5100 Ys < Ye (Xe, Ye) (Xe, Ye) Xs < Xe 6101 Ys > Ye (Xs, Ys) (Xs, Ys) Xs > Xe 7110 Ys < Ye (Xe, Ye) (Xe, Ye) Xs > Xe 8111 Ys > Ye (Xs, Ys) *:The display image shows the display direction when the same data as No.1 are written into RAM for condition change. *: The outside address of RAM must not be set for correct operation. Xs : start address of X , Ys : Start address of Y, Xe : End address of X, Ye : End address of Y
- 27 -
NJU6824
(10) The relationship among the DDRAM column address, display data and segment drivers
- 28 ABS SWAP 1 1
D11 SEGA0 D9 D8 D7 SEGB0 D5 D4 D3 D2 D1 D0 D1 SEGA0 D2 palette C D3 SEGC0 palette C D4 D7 D8 palette B D6 SEGB0 palette B D9 SEGB0 D10 palette B D12 D13 palette A SEGC0 SEGA0 D13 D12 D10 D9 D8 D7 D4 D3 SEGC0 palette C D2 D1 D10 palette A palette A D14 D14 D15 D15
ABS SWAP 1 0
ABS SWAP 0 1
ABS SWAP 0 0
D11
SEGC0
palette A
D10
D9
D8
D7
X=00H
X=00H
X=00H
X=00H
SEGB0
palette B
D6
D5
D4
D3
In the color mode, and 16-bit data bus mode
D2
SEGA0
palette C
D1
D0
Column address / bit / segment assign $%
Column address / bit / segment assign $%
Column address / bit / segment assign $%
Column address / bit / segment assign $%
SEGC127 D9 D8 D7 D6
X=7FH
X=7FH
X=7FH
X=7FH
SEGB127 D5 D4 D3 SEGC127 palette C D2 D1 D0
SEGA127
$%
D11 SEGA127 palette A D10 SEGC127 palette A SEGB127 palette B SEGB127 palette B SEGA127 palette C
palette A
palette B
palette C
$%
D11
D10
$%
$%
$%
$%
$%
$%
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
$%
D9
SEGA127
$%
palette A
$%
D15 D14 D13 D12 D10 SEGB127 palette B D9 D8 D7 D4 SEGC127 palette C D3 D2 D1
$%
D8
D7
D6
D5
D4
D3
D2
D1
D0
ABS SWAP 0 1
ABS SWAP 0 0
D3 SEGA0 D1 D0 D7 SEGB0 D5 D4 D3 D2 D1 D0 D1 SEGA0 D2 palette C D3 SEGC0 palette C D4 D7 D0 palette B SEGB0 SEGB0 D6 palette B D1 D2 D4 D5 palette A SEGC0 SEGA0 D2 palette A palette A D6 D6 D5 D4 D2 palette B D1 D0 D7 D4 D3 SEGC0 palette C D2 D1
D3
D7
D7
SEGC0
palette A
D2
D1
ABS SWAP 1 1 X=00H(Upper) X=00H(Upper) X=00H(Upper)
ABS SWAP 1 0 X=00H(Upper)
D0
D7
SEGB0
palette B
D6
D5
D4
In the color mode, and 8-bit data bus mode
D3
D2
SEGA0
palette C
D1
D0
$%
$%
$%
$%
$%
$%
SEGC127 D1 D0 D7 SEGB127 D5 D4 D3 SEGC127 palette C D2 D1 D0 palette B D6
Column address / bit / segment assign $% X=00H(Lower) X=7FH(Upper)
Column address / bit / segment assign $% X=00H(Lower) X=7FH(Upper)
Column address / bit / segment assign $% X=00H(Lower) X=7FH(Upper)
Column address / bit / segment assign $% X=00H(Lower) X=7FH(Upper)
SEGB127
X=7FH(Lower)
X=7FH(Lower)
SEGA127
$%
D3 SEGA127 palette A D2 SEGC127 SEGB127
palette A
palette B
palette C
$% X=7FH(Lower) X=7FH(Lower)
SEGA127
$%
$%
$%
$%
D3
D7 palette A D6 D5 D4 D2 palette B D1 D0 D7 D4 palette C D3 D2 D1
D7 SEGA127 palette A D6 D5 D4 D2 SEGB127 palette B D1 D0 D7 D4 SEGC127 palette C D3 D2 D1
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
NJU6824
D0
- 29 -
NJU6824
- 30 ABS SWAP * 1 ABS SWAP * 0
D7 D7 SEGA0 palette A D6 D5 D4 SEGB0 palette B D3 D2 D1 SEGC0 palette C D0 D0 SEGC0 D5 D4 palette A D6
X=00H
X=00H
SEGB0 D3 D2 D1
palette B
SEGA0
palette C
In the color mode, 8-bit data bus mode, and C256 mode (C256=1)
Column address / bit / segment assign $%
Column address / bit / segment assign $%
SEGC127
SEGB127
SEGA127
$%
palette A
palette B
palette C
$%
$%
D7 D6 D5 D4 D3 D2 D1 D0
SEGA127
$%
palette A
$%
$%
D7 D6 D5 D4
X=7FH
X=7FH
SEGB127
palette B
D3 D2 D1 SEGC127 palette C D0
ABS SWAP 1 0
ABS SWAP 0 1
ABS SWAP 1 1
SEGC0 SEGA0 SEGA0 SEGB0
ABS SWAP 0 0
SEGC0
SEGB0
X=00H
X=00H
X=00H
In the B&W mode, and 16-bit data bus mode
X=00H
SEGB0
SEGB0
SEGA0
SEGC0
SEGA0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SEGC0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
$%
$%
$%
$%
$%
$%
Column address / bit / segment assign $%
Column address / bit / segment assign $%
Column address / bit / segment assign $%
Column address / bit / segment assign $%
SEGC127
X=7FH
X=7FH
X=7FH
X=7FH
SEGB127
SEGA127
$%
D15 D15 D14 D13 D12 SEGA127 D11 D10 D9 SEGB127 D8 D7 D6 D5 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SEGC127 D4 D3 D2 D1 D0
$%
SEGC127
D15 D14 D13 D12 SEGB127 D11 D10 D9 D8 D7 D6 D5 SEGA127 D4 D3 D2 D1 D0
SEGA127
D15 D14 D13
SEGB127
D12 D11 D10 D9 D8 D7 D6 D5 SEGC127 D4 D3 D2 D1 D0
NJU6824
- 31 -
NJU6824
In the B&W mode, and 8-bit data bus mode
ABS SWAP 0 0
D7
X=00H(Upper)
D6 D5 D4 D2 D1 D0 D7
Column address / bit / segment assign $% X=00H(Lower) X=7FH(Upper) $%
D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0
X=7FH(Lower)
D7 D4 D3 D2 D2 D1 D1 D1 D0 D0 D1
$%
ABS SWAP 0 1
D7
X=00H(Upper)
D6 D5 D4 D2 D1 D0 D7
Column address / bit / segment assign $% X=00H(Lower) X=7FH(Upper) $%
D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7
X=7FH(Lower)
D4 D3 D3 SEGA127 SEGC127 SEGA127 D3 D2 D2
SEGC127
$%
ABS SWAP 1 0 X=00H(Upper)
D3 D2 D1 D0 D7 D6
Column address / bit / segment assign $% X=00H(Lower) X=7FH(Upper) $%
D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6
SEGB127
SEGC0
SEGB0
SEGA0
X=7FH(Lower)
D5 D4 D4
SEGA127
$%
ABS SWAP 1 1 X=00H(Upper)
D3 D2 D1 D0 D7 D6
Column address / bit / segment assign $% X=00H(Lower) X=7FH(Upper) $%
D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6
SEGB127
SEGC0
SEGA0
SEGB0
X=7FH(Lower)
D5
SEGC127
$%
- 32 -
SEGB127
SEGC0
SEGB0
SEGA0
SEGC127
SEGA127
SEGB127
SEGC0
SEGA0
SEGB0
NJU6824
Bit assignments between write and read data (in the 16-bit data bus mode) ABS=0
Write data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Read data
D15
D14
D13
D12
*
D10
D9
D8
D7
*
*
D4
D3
D2
D1
*
ABS=1
Write data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Read data
*
*
*
*
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Examples of write and read data (In the 8 bit bus mode) ABS=0, C256=0 (Address; Upper bit)
Write data D7 D6 D5 D4 D3 D2 D1 D0
Read data
D7
D6
D5
D4
*
D2
D1
D0
ABS=0, C256=0 (Address; Lower bit)
Write data D7 D6 D5 D4 D3 D2 D1 D0
Read data
D7
*
*
D4
D3
D2
D1
*
ABS=1, C256=0 (Address; Upper bit)
Write data D7 D6 D5 D4 D3 D2 D1 D0
Read data
*
*
*
*
D3
D2
D1
D0
ABS=1, C256=0 (Address; Lower bit)
Write data D7 D6 D5 D4 D3 D2 D1 D0
Read data
D7
D6
D5
D4
D3
D2
D1
D0
ABS=0, C256=1
Write data D7 D6 D5 D4 D3 D2 D1 D0
Read data
D7
D6
D5
D4
D3
D2
D1
D0
*: Invalid Data
- 33 -
NJU6824
Icon segment register address bit assignment
- 34 ABS SWAP 1 1
D11 SEGSA0 D9 D8 D7 SEGSB0 D5 D4 D3 D2 D1 D0 D11 SEGSA1 D9 D8 D7 D6 palette A SEGSC1 D10 SEGSA0 D2 D1 D15 palette A D14 D13 D12 D10 D9 SEGSB1 palette B D8 D7 D4 D2 D1 D0 SEGSA1 palette C D3 D2 D1 SEGSC1 palette C palette C D3 SEGSC0 palette C D4 D7 D8 palette B D6 SEGSB0 palette B D9 SEGSB0 D10 palette B D12 D13 palette A SEGSC0 SEGSA0 D10 palette A palette A D14 D15 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 SEGSC0 palette C D2 D1 D15 SEGSA1 palette A D14 D13 D12 D10 D9
ABS SWAP 1 0
ABS SWAP 0 1
ABS SWAP 0 0
D11
SEGSC0
palette A
D10
D9
D8
D7
X=00H
X=00H
X=00H
X=00H
SEGSB0
palette B
D6
D5
D4
D3
In the color mode, and 16-bit data bus mode
D2
SEGSA0
palette C
D1
D0
D11
SEGSC1
palette A
D10
D9
D8
Column address / bit / segment assign
Column address / bit / segment assign
Column address / bit / segment assign
Column address / bit / segment assign
D7
X=01H
X=01H
X=01H
X=01H
SEGSB1 D5 D4 D3 SEGSC1 palette C
palette B SEGSB1
D6 palette B
D5
SEGSB1
palette B
D8 D7 D4 D3 D2 D1
D4
D3
SEGSA1
palette C
D2
D1
D0
ABS SWAP 0 1
D7 SEGSC0 D5 D4 D2 SEGSB0 D0 D7 D4 D3 D2 D1 D7 SEGSC1 palette A D6 D5 D4 D2 SEGSB1 palette B D1 D0 D7 D4 SEGSA0 palette C palette B D1 palette A SEGSA0 D6 palette A D7 D6 D5 D4 D2 SEGSB0 palette B D1 D0 D7 D4 D3 SEGSC0 palette C D2 D1 D7 SEGSA1 palette A D6 D5 D4 D2 SEGSB1 palette B D1 D0 D7 D4
ABS SWAP 0 0
D3 SEGSA0 D1 D0 D7 SEGSB0 D5 D4 D3 D2 D1 D0 D3 SEGSA1 D1 D0 D7 SEGSB1 D5 D4 D3 SEGSC1 palette C D2 D1 D0 palette B D6 palette A D2 SEGSC0 palette C palette B D6 palette A D2
D3
SEGSC0
palette A
D2
D1
ABS SWAP 1 1 X=00H(Upper) X=00H(Upper) X=00H(Upper)
ABS SWAP 1 0 X=00H(Upper)
D0
D7
SEGSB0
palette B
D6
D5
D4
In the color mode, and 8-bit data bus mode
D3
D2
SEGSA0
palette C
D1
D0
D3
SEGSC1
palette A
D2
D1
D0
Column address / bit / segment assign X=00H(Lower) X=01H(Upper) Column address / bit / segment assign X=00H(Lower) X=01H(Upper)
Column address / bit / segment assign X=00H(Lower) X=01H(Upper)
Column address / bit / segment assign X=00H(Lower) X=01H(Upper)
D7
SEGSB1
palette B
D6
D5
D4
D3
X=01H(Lower)
X=01H(Lower)
X=01H(Lower)
X=01H(Lower)
SEGSA1
palette C
D2
D1
SEGSA1
palette C
D3 D2 D1
SEGSC1
palette C
D3 D2 D1
D0
NJU6824
- 35 -
NJU6824
- 36 ABS SWAP 0 1 ABS SWAP 1 0 ABS SWAP 0 0 ABS SWAP 1 1
SEGSC0 SEGSA0 SEGSA0 SEGSB0 SEGSC0 SEGSB0
X=00H
X=00H
X=00H
X=00H
SEGSB0
SEGSB0
SEGSA0
SEGSC0
In the B/W mode, and 16-bit data bus mode
SEGSA0
SEGSC0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 SEGSC1 SEGSA1 D14 D13 D14 D13
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13
SEGSC1
SEGSA1
Column address / bit / segment assign
Column address / bit / segment assign Column address / bit / segment assign
SEGSB1
Column address / bit / segment assign
D12 D11 D10 D9
D12 D11 D10 D9 D8
SEGSB1
D12 D11 D10 D9
X=01H
X=01H
X=01H
X=01H
SEGSB1
D8 D7 D6 D5 D4 D3 D2 D1 D0
SEGSB1
D7 D6 D5 D4 SEGSC1 D3 D2 D1 D0
D7 D6 SEGSA1
D8 D7 D6 D5 SEGSC1 D2 D1 D0 D5 D4 D3 D4 D3 D2 D1 D0
SEGSA1
NJU6824
In the B/W mode, and 8-bit data bus mode
ABS SWAP 0 0
D7
X=00H(Upper)
D6 D5 D4 D2 D1 D0
Column address / bit / segment assign X=00H(Lower) X=01H(Upper)
D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0
X=01H(Lower)
D7 D4 D3 D2 D2 D1 D1 D1 D0 D0 D1
SEGSC0
ABS SWAP 0 1
D7
X=00H(Upper)
D6 D5 D4 D2 D1 D0
Column address / bit / segment assign X=00H(Lower) X=01H(Upper)
D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7
X=01H(Lower)
D4 D3 D3 SEGSA1 SEGSC1 SEGSA1 D3 D2 D2
SEGSC0
SEGSC1
SEGSB0
SEGSA0
ABS SWAP 1 0 X=00H(Upper)
D3 D2 D1 D0 D7 D6
Column address / bit / segment assign X=00H(Lower) X=01H(Upper)
D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6
SEGSB1
X=01H(Lower)
D5 D4 D4
SEGSC0
SEGSA0
SEGSB0
SEGSA1
ABS SWAP 1 1 X=00H(Upper)
D3 D2 D1 D0 D7 D6
Column address / bit / segment assign X=00H(Lower) X=01H(Upper)
D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6
SEGSB1
X=01H(Lower)
D5
SEGSC0
SEGSC1
SEGSB0
SEGSA0
SEGSB1
SEGSC1
SEGSA0
SEGSB0
SEGSA1
SEGSB1
- 37 -
NJU6824
(11) Gradation palette In the gradation mode, either variable or fixed gradation mode is selected by programming the "PWM" register of the "Gradation control" instruction. PWM=0: PWM=1: Variable gradation mode (Select 16 gradation levels out of 32-gradation level of the gradation palette) Fixed gradation mode (Fixed 8-gradation levels)
In these modes, each of the gradation palettes Aj, Bj and Cj can select 16-gradation level out of 32-gradation level by setting 5-bit data to the "PA" registers in the "Gradation palette j" instructions (j=0 to Fh). For instance, the gradation palettes Aj correspond to the SEGAi, the Bj to SEGBi and the Cj to SEGCi (j=0 to 15, i=0 to 127).
- 38 -
NJU6824
Correspondence between display data and gradation palettes
Table 10 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))
(MSB) Display data (LSB) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Gradation palette Palette 0 Palette 1 Palette 2 Palette 3 Palette 4 Palette 5 Palette 6 Palette 7 Palette 8 Palette 9 Palette10 Palette11 Palette12 Palette13 Palette14 Palette15 Default palette value 00000 00011 00101 00111 01001 01011 01101 01111 10001 10011 10101 10111 11001 11011 11101 11111
Gradation palette table (Variable gradation mode, PWM="0", MON="0")
Table 11 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))
Palette value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Gradation level 0 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Gradation palette Palette 0(default) Palette value 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Gradation level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Gradation palette Palette 0(default)8 Palette 9(default) Palette 10(default) Palette 11(default) Palette 12(default) Palette 13(default) Palette 14(default) Palette 15(default)
Palette 1(default) Palette 2(default) Palette 3(default) Palette 4(default) Palette 5(default) Palette 6(default) Palette 7(default)
- 39 -
NJU6824
Gradation palette table (Fixed gradation mode, PWM="1", MON="0")
Table 12 8-gradation segment drivers
(MSB) Display data (LSB) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 * * * * * * * * Gradation level 0/7 1/7 2/7 3/7 4/7 5/7 6/7 7/7 (MSB) Display data (LSB) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 * * * * * * * * * * * * * * * * Gradation level 0/7 3/7 5/7 7/7
Correspondence between display data and gradation level (B&W mode, MON="1")
Table 13
(MSB) Display data (LSB) 0 * 1 * *:Don't care * * * * Gradation level 0 1
- 40 -
NJU6824
(12) Gradation control and display data (12-1) Gradation mode In the graduation mode, each pixel for RGB corresponds to successive 3 segment drivers, and each segment driver provides 16-gradation PWM output by controlling 4 bit display data of the DDRAM. Accordingly, the LSI can drive up to 128x128 pixels in 4096-color (16-gradation x 16-gradation x 16gradation = 4-bit x 4-bit x 4-bit). In addition, the LSI can transfer the display data for the RGB by 16-bit at once or 8-bit two-times. The data assignment between gradation palettes and segment drivers varies in accordance with setting for the "SWAP" registers of the "Display control (2)" instruction. - SWAP = 0 SEGAi SEGBi SEGCi (i=0 to 127)
Palette Aj
Palette Bj
Palette Cj
Gradation palette j=0 to 15 Gradation control circuit
0 MSB
0
0
0 0 LSB MSB
0
0
1 1 LSB MSB
1
1
1 LSB
Display data in DDRAM
0 D7
ABS=1 C256=1
0 D6 D2 D6
0 D5 D1 D5
0 D4 D0 *
0 D2 D7 D4
0 D1 D6 D3
0 D0 D5 D2
1 D7 D4 *
1 D4 D3 D1
1 D3 D2 D0
1 D2 D1 *
1 D1 D 0) *)
Display data from MPU
(Upper bit / Lower bit)
(D3 (D7
- SWAP = 1 SEGAi SEGBi SEGCi (i=0 to 127)
Palette Aj
Palette Bj
Palette Cj
Gradation palette j=0 to 15 Gradation control circuit
1 LSB
1
1
1 1 MSB LSB
0
0
0 0 MSB LSB
0
0
Display data in DDRAM 0 MSB
0 D7 ABS=1 (D3
C256=1
0 D6 D2 D6
0 D5 D1 D5
0 D4 D0 *
0 D2 D7 D4
0 D1 D6 D3
0 D0 D5 D2
1 D7 D4 *
1 D4 D3 D1
1 D3 D2 D0
1 D2 D1 *
1 D1 D 0) *)
Display data from MPU
(Upper bit / Lower bit)
(D7
- 41 -
NJU6824
In the 16-bit data bus mode, the data assignments between the gradation palettes and the segment drivers vary in accordance with setting for the "SWAP" bit of the "Display control (2)" instruction as well as the assignment in the 8-bit data bus mode. - SWAP = 0 SEGAi SEGBi SEGCi (i=0 to 127) Gradation palette j=0 to 15 Gradation control circuit
Palette Aj
Palette Bj
Palette Cj
0 MSB
0
0
0 0 LSB MSB
0
0
1 1 LSB MSB
1
1
1 LSB
Display data in DDRAM
0 D15
ABS=1
0 D14
0 D13 D9
0 D12 D8
0 D10 D7
0 D9 D6
0 D8 D5
1 D7 D4
1 D4 D3
1 D3 D2
1 D2 D1
1 D1 D 0)
Display data from MPU
(D11 D10
- SWAP = 1 SEGAi SEGBi SEGCi (i=0 to 127)
Palette Aj
Palette Bj
Palette Cj
Gradation palette j=0 to 15 Gradation control circuit
1 LSB
1
1
1 1 MSB LSB
0
0
0 0 MSB LSB
0
0
Display data in DDRAM 0 MSB
0 0 D15 D14 ABS=1 (D11 D10
0 D13 D9
0 D12 D8
0 D10 D7
0 D9 D6
0 D8 D5
1 D7 D4
1 D4 D3
1 D3 D2
1 D2 D1
1 D1 D 0)
Display data from MPU
- 42 -
NJU6824
(12-2) B&W mode (MON="1") In the B&W mode, 3 bits of the MSB data are used in both of the 16-bit and 8-bit data bus modes. In the 16-bit data bus mode (Similarly 8-bit data bus access) - SWAP = 0 SEGAi SEGBi SEGCi
(i=0 to 127)
Palette Aj
Palette Bj
Palette Cj
Gradation palette j=0 to 15 Gradation control circuit Display data in DDRAM
0 MSB 0 D15
ABS=1
0
0
0 0 LSB MSB 0 D12 D8 0 D10 D7
0
0
1 1 LSB MSB 1 D7 D4 1 D4 D3
1
1
1 LSB 1 D1 D 0)
0 D14
0 D13 D9
0 D9 D6
0 D8 D5
1 D3 D2
1 D2 D1
Display data in DDRAM
(D11 D10
- SWAP = 1 SEGAi SEGBi SEGCi (i=0 to 127)
Palette Aj
Palette Bj
Palette Cj
Gradation palette j=0 to 15 Gradation control circuit Display data in DDRAM 0 MSB
1 LSB
1
1
1 1 MSB LSB
0
0
0 0 MSB LSB
0
0
0 D15
ABS=1
0 D14
0 D13 D9
0 D12 D8
0 D10 D7
0 D9 D6
0 D8 D5
1 D7 D4
1 D4 D3
1 D3 D2
1 D2 D1
1 D1 D 0)
Display data in DDRAM
Column address;
nH
(D11 D10
The correlation of display data with gradation control is also applied to Icon segment.
- 43 -
NJU6824
(13) Display timing generator The display-timing generator creates the timing pulses such as the CL, the FLM, the FR and the CLK by dividing the oscillation frequency oscillate an external or internal resister mode. The each of timing pulses is outputted through the each output terminals by "SON"=1. (14) LCD line clock (CL) The LCD line clock (CL) is used as a count-up signal for the line counter and a latch signal for the data latch circuit. At the rising edge of the CL signal, the line counter is counted-up and the 384-bit display data, corresponding to this line address, is latched into the data latch circuit. And at the falling edge of the CL signal, this latched data output on the segment drivers. Read out timing of the display data, from DDRAM to the latch circuits is completely independent of the access timing to the MPU. For this reason, the MPU can access to the LSI regardless of an internal operation. (15) LCD alternate signal (FR) and LCD synchronous signal (FLM) The FR and FLM signals are created from the CL signal. The FR signal is used to alternate the crystal polarization on a LCD panel. It is programmed that the FR signal is toggle on every frame in the default setting or once every N lines in the N-line inversion mode. The FLM signal is used to indicate a start line of a new display frame. It presets an initial display line address of the line counter when the FLM signal becomes "1". (16) Data latch circuit The data latch circuit is used temporarily store the display data that will output to the segment drivers. The display data in this circuit is updated in synchronization of the CL signal. The "All pixels ON/OFF", "Display ON/OFF" and "Reverse display ON/OFF" instructions change the display data in this circuit but do not change the display data of the DDRAM. (17) Common and segment drivers The LSI includes 384+6-segment drivers and 128-common drivers. The common drivers generate the LCD driving waveforms composed of the VLCD, V1, V4 and VSS in accordance with the FR signal and scanning data. The segment drivers generate waveforms composed of the VLCD, V2, V3 and VSS in accordance with the FR signal and display data.
- 44 -
NJU6824
LCD Driving waveforms (In the B&W mode, Reverse display OFF, 1/129 duty)
COM0 COM1 CL
129 1
2345
129 1
2345
129 1
SEG0
SEG1
SEG2
FLM
FR VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS
COM0
COM1
SEG0
SEG1
Fig 8
- 45 -
NJU6824
(18) Icon Segment Driver Circuit Each 3 outputs (SEGSA0 to SEGSA1, SEGSB0 to SEGSB1, SEGSC0 to SEGSC1) placed at both edges of normal segment output terminals line are Segment outputs for Icon. Although normal Segment output generates the LCD driving voltage corresponding with the data in Display Data RAM, Icon segment driver provides the register instead of the display data RAM. The data corresponding to SEGSA0, SEGSB0 and SEGSC0 are in 12bit register and output the same driving voltage on the row direction. (The data corresponding to SEGSA1, SEGSB1 and SEGSC1 are same as SEGSA0, SEGSB0 and SEGSC0.) The outputs of SEGSA0 to SEGSA1 assign the same gradation pallet as SEGA0 to SEGA127, SEGSB0 to SEGSB1 are SEGB0 to SEGB127 and SEGSC0 to SEGSC1 are SEGC0 to SEGC127. Icon Segment Driver Circuit operates for the outline frame display or background. These displays are changed in accordance with attribute of ALLON or REV command, but no change by LREV command. The capacity of register corresponding with Icon segment driver (SEGSA0 to SEGSA1, SEGSB0 to SEGSB1, SEGSC0 to SEGSC1) is 24 bits. The access to from this register performed at DMY="1"..
Table14
RS L L L L DMY 0 0 1 1 68type R/W H L H L 80 type RD L H L H WR H L H L Function Display data read Display data write Icon segment register read Icon segment register read
Read out function from the Icon segment register is restricted as same as the display data read out function from Display Data RAM. After address set, the addressed data does not come out by the first read instruction immediately but comes out by the second read instruction. Therefore, one dummy read out function is required for data read from Icon segment register after the address set or the data write operation. When the Icon segment registers are accessed in DMY="1", the valid addressing is just a column address. Because of 24 bits Icon register, the valid addresses are "00h" and "01h" in 8-bit or 16-bit mode. When the Icon segment registers are accessed in DMY="1", the data write operation into Icon register is enabled with the increment / decrement operation. The column address increment operates as shown below. But the auto carry up operation like as the maximum address to "00h" does not operate of the display data RAM access. 00h -> Max.
* 8-bit or 16-bit data bus mode (DMY="1") SEGSA0, SEGSB0, SEGSC0 Column address 00H: SEGSA1, SEGSB1, SEGSC1 01H:
Note)
Refer the "Icon segment register address bit assignment" in (10) The relationship among the DDRAM column address, display data and segment drivers. Both of Icon segment register and Display data RAM operate a same address counter so that the address is set again in the status transition of DMY = "0" to "1" or "1" to "0". The access to Icon register must be operated in the condition of HV=0.
- 46 -
NJU6824
Examples for the dummy segment registers (DMY="1") (In the 16-bit data bus mode, gradation mode, (REF,SWAP)=(0,0))
Column address: 00H SEGSA0 SEGSB0 SEGSC0
Palette Aj
Palette Bj
Palette Cj
Gradation palette j=0 to 15 Gradation control circuit
0 MSB 0 D15
ABS=1
0
0
0 0 LSB MSB 0 D12 D8 0 D10 D7
0
0
1 1 LSB MSB 1 D7 D4 1 D4 D3
1
1
1 LSB 1 D1 D 0)
Display data in DDRAM
0 D14
0 D13 D9
0 D9 D6
0 D8 D5
1 D3 D2
1 D2 D1
Display data in DDRAM
(D11 D10
Column address: 01H SEGSA1 SEGSB1 SEGSC1
Palette Aj
Palette Bj
Palette Cj
Gradation palette j=0 to 15 Gradation control circuit
0 MSB 0 D15
ABS=1
0
0
0 0 LSB MSB 0 D12 D8 0 D10 D7
0
0
1 1 LSB MSB 1 D7 D4 1 D4 D3
1
1
1 LSB 1 D1 D 0)
Display data in DDRAM
0 D14
0 D13 D9
0 D9 D6
0 D8 D5
1 D3 D2
1 D2 D1
Display data in DDRAM
(D11 D10
- 47 -
NJU6824
(19) Oscillator The oscillator generates internal clocks for the display timing and the voltage booster. Since the LSI has internal capacitor (C) and resistor (R) for the oscillation, external capacitor and resistor are not usually required. However, in case that an external resistor is used, the resister is connected between the OSC1 and OSC2 terminals. The external resistor becomes enabled by setting "1" to the "CKS" register of "Data bus length" instruction. When the internal oscillator is not used, the external clocks with 50% duty cycle ratio must be input to the OSC1 terminal. In addition, the feed back resister for the oscillation is varied by programming the "Rf" register of the "Frequency control" instruction, so that it is possible to optimize the frame frequency for a LCD panel. Setting examples of the MON (B&W /Gradation) and the PWM (Variable gradation /Fixed gradation) are described, as follows. Internal oscillation mode (CKS=0) Symbol f1 f2 f3 MON 0 0 1 PWM 0 1 * Display mode Variable gradation mode Fixed gradation mode B&W mode
*: Don't care
External resistor oscillation mode(CKS=1) The internal clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the "MON" and "PWM" registers must be set as well. External clock input mode(CKS=1) The external clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the "MON" and "PWM" registers must be set as well. (20) Power supply circuits The internal power supply circuits are composed of the voltage booster, the electrical variable resister (EVR), the voltage regulator, reference voltage generator and the voltage followers. The condition of the power supply circuits is arranged by programming the "DCON" and "AMPON" registers on the "Power control" instruction. For this arrangement, some parts of the internal power supply circuits are activated in using an external power supply, as shown in the following table. Table 15
DCON 0 0 1 AMPON 0 1 1 Voltage booster Disable Disable Enable Voltage followers Voltage regulator EVR Disable Enable Enable External voltage VOUT, VLCD, V1, V2, V3, V4 VOUT - Note 1, 3 2, 3 -
Note1) The internal power circuits are not used. The external VOUT is required and the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, VREF, VREG and VEE terminals must be open. Note2) The internal power circuits except the voltage booster are used. The external VOUT is required and the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5- and VEE terminals must be open. The reference voltage is required to VREF terminal. Note3) The relation among the voltages should be maintained as follows. VOUT VLCD V1 V2 V3 V4 VSS
- 48 -
NJU6824
(21) Voltage booster The voltage booster generates maximum 6x voltage of the VEE level. It is programmed so that the boost level is selected out of 1x, 2x, 3x, 4x, 5x and 6x by the "Boost level select" instruction. The boosted voltage VOUT must not exceed beyond the value of 18.0V, otherwise the voltage stress may cause a permanent damage to the LSI. Boosted voltages VOUT=18V VOUT=9V
VEE=3V VSS=0V 3-time boost Capacitor connections for the voltage Booster 6-time boost
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSS
VEE=3V VSS=0V 6-time boost
5-time boost + + + + + +
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSS
+ + + +
+
4-time boost
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSS
3-time boost + + +
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSS
2-time boost + +
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSS
+
+
+
+
Fig 9
- 49 -
NJU6824
(22) Reference voltage generator The reference voltage generator is used to produce the reference voltage (VBA), which is output from the VBA terminal and should be input to the VREF terminal. VBA = VEE x 0.9 (23) Voltage regulator The voltage regulator, composed of the gain control circuit and an operational amplifier, and is used to gain the reference voltage (VREF) and to create the regulated voltage (VREG). The VREG is used as an input voltage to the EVR circuits, which is programmed by the "VU" register of the "Boost level" instruction. VREG = VREF x N (N: register value for the boost level)
(24) Electrical variable resister (EVR) The EVR is variable within 128-step, and is used to fine-tune the LCD driving voltage (VLCD) by programming the "DV" register in the "EVR control" instruction, so that it is possible to optimize the contrast level for a LCD panels. VLCD = 0.5 x VREG + M (VREG - 0.5 x VREG) / 127 (M: register value for the EVR) (25) LCD driving voltage generation circuit LCD driving voltage generation circuit generates the VLCD voltage levels as VLCD, V1, V2, V3 and V4 with internal E.V.R and the Bleeder resistors. The bias ratio of the LCD driving voltage is selected out of 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11 and 1/12. In using the internal power supply, the capacitors CA2 must be connected to the VLCD, V1, V2, V3 and V4 terminals, and the CA2 value must be determined by the evaluation with actual LCD modules. In using the external power supply, the external LCD driving voltages such as the VLCD, V1, V2, V3 and V4 are supplied and the internal power supply circuits must be set to "OFF" by DCON = AMPON = "0". In this mode, voltage booster terminals such as C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, VEE, VREF and VREG must be opened. In case that the voltage booster is not used but only some parts of internal power supply circuits (Voltage followers, Voltage regulator and EVR) are used, the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+ and C5terminals must be opened. And, the external power supply is input to the VOUT terminal, and the reference voltage to the VREF terminal. The capacitor CA3 must connect to the VREG terminal for voltage stabilization. < Bias adjustment function > NJU6824 prepares bias adjustment terminals V1A1, V1A2, V4A1 and V4A2 for fine adjustment of V1 and V4 out of voltages. The status combination of V1A1 terminal and V1A2 can adjust V1 voltage in below table and V4A1 and V4A2 can adjust V4 voltage. These adjustment performs by the connection change between the Bleeder resistors and the output buffer operational amplifier as voltage follower circuit. V1A1 terminal 0 0 1 1 V1A2 terminal 0 1 0 1 Fluctuation voltage [mV] *1 0 +5 -5 +10 V4A1 terminal 0 0 1 1 V4A2 terminal 0 1 0 1 Fluctuation voltage [mV] *1 0 +5 -5 -10
Note 1) The fluctuation voltage is a adjusted voltage against the default voltage at (V1A1, V1A2 = "0, 0" and V4A1, V4A2 = "0, 0"). The "+" mark means a direction of voltage fluctuation to VLCD and the "-" is to VSS. Note 2) The fluctuation voltage is an ideal value. Note 3) The fluctuation voltage is at VLCD=13.5V. Note 4) "0" of V1A1, V1A2, V4A1 and V4A2 means VSS and "1" means VDD.
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NJU6824
Connections of the capacitors for voltage boost
Using all of the internal power supply circuits (6-time boost) VDD VDD VEE VBA CA3 VSS CA3 VSS CA1 CA1 CA1 CA1 CA1 VREF VREG C 1C 1+ C 2C 2+ C 3C 3+ C 4C 4+ C 5C 5+
Using only external power supply circuits VDD VDD VEE VBA VREF VREG C 1C 1+ C 2C 2+ C 3C 3+ C 4C 4+ C 5C 5+
NJU6824
NJU6824
CA1 VSS CA2 CA2 CA2 CA2 VSS CA2
VOUT
VOUT
VLCD V1 V2 V3 V4
VLCD V1 External Power V2 circuit V3 V4
VLCD V1 V2 V3 V4
Fig 10
Reference values CA1 1.0 to 4.7uF CA2 1.0 to 2.2uF CA3 0.1uF Note) B grade capacitors are required.
Fig11
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NJU6824
Using internal power supply circuits Without the reference voltage generator(1) (6-time boost)
Using internal power supply circuit Without the reference voltage generator(2) (6-time boost)
VDD
VDD VEE VBA VREF
Thermistor
VDD
VDD VEE VBA VREF
CA3 VSS CA1 CA1 CA1 CA1 CA1
VREG C 1C 1+ C 2C 2+ C 3C 3+ C 4C 4+ C 5C 5+
CA3 VSS CA1 CA1 CA1 CA1 CA1
VREG C 1C 1+ C 2C 2+ C 3C 3+ C 4C 4+ C 5C 5+
NJU6824
NJU6824
CA1 VSS CA2 CA2 CA2 CA2 VSS CA2
VOUT
CA1 VSS CA2 CA2 CA2 CA2
VOUT
VLCD V1 V2 V3 V4 VSS
VLCD V1 V2 V3 V4
CA2
Fig 12
Fig 13
Reference value CA1 1.0 to 4.7F CA2 1.0 to 2.2F CA3 0.1F Note) B grade capacitors are required.
- 52 -
NJU6824
Using internal power supply circuits Without the voltage booster
VDD
VDD VEE VBA
CA3 CA3 VSS
VREF VREG C 1C 1+ C 2C 2+ C 3C 3+ C 4C 4+ C 5C 5+
VSS
NJU6824
External power circuit
VOUT
CA2 CA2 CA2 CA2 VSS CA2
VLCD V1 V2 V3 V4
Fig 14
Reference value CA1 1.0 to 4.7F CA2 1.0 to 2.2F CA3 0.1F Note) B grade capacitors are required.
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NJU6824
(26) Partial display function The partial display function is used to partially specify some parts of display area on LCD panels. By using this function, LCD modules can work in lower duty cycle ratio, lower LCD bias ratio, lower boost level and lower LCD driving voltage. It is usually used to display a time and calendar, and is also used to optimize the LSI condition in accordance with the display size. It can be programmed to select the duty cycle ratio (1/17, 1/25, 1/33, 1/41, 1/49, 1/57, 1/65, 1/73, 1/81, 1/89, 1/97, 1/105, 1/113, 1/121, 1/129, in DSE=0), the LCD bias ratio, the boost level and the EVR value by the instructions.
Partial display image
NJRC LCD DRIVER Low Power and Low Voltage Normal display
LCD DRIVER
Partial display
Partial display sequence
Optional status
Display OFF (ON/OFF="0")
Internal Power supply OFF (DCON="0", AMPON="0")
WAIT
Setting for LCD driving voltage-related functions
- Boost level - EVR value - LCD bias ratio
Internal Power supply ON (DCON="1", AMPON="1")
WAIT Setting for display-related functions - Duty cycle ratio - Initial display line - Initial COM line - Other instructions
Display ON (ON/OFF ="1")
Partial display Status
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NJU6824
(27) Discharge circuit Discharge circuit is used to discharge the electric charge of the capacitors on the V1 to V4 and VLCD terminals. This circuit is activated by setting "0" to the "DIS" register of the "Discharge" instruction or by setting "RESb" terminal to "0" level. The "Discharge ON/OFF" instruction is usually required just after the internal power supply is turned off by setting "0" into the "DCON" and "AMPON" registers, or just after the external power supply is turned off. During the discharge operation, the internal or external power supply must not be turned on. (28) Reset circuit The reset circuit initializes the LSI into the following default status. It is activated by setting the RESb terminal to "0". The RESb terminal is usually required to connect to MPU reset terminal in order that the LSI can be initialized at the same timing of the MPU.
q
Default status 1. DDRAM display data 2. column address 3. row address 4. Initial display line 5. Display ON/OFF 6. Reverse display ON/OFF 7. Duty cycle ratio 8. N-line Inversion ON/OFF 9. COM scan direction 10. Address direction of RAM 11. Read modify write 12. SWAP mode 13. EVR value 14. Internal power supply 15. Display mode 16. LCD bias ratio 17. Gradation Palette 0 18. Gradation Palette 1 19. Gradation Palette 2 20. Gradation Palette 3 21. Gradation Palette 4 22. Gradation Palette 5 23. Gradation Palette 6 24. Gradation Palette 7 25. Gradation Palette 8 26. Gradation Palette 9 27. Gradation Palette 10 28. Gradation Palette 11 29. Gradation Palette 12 30. Gradation Palette 13 31. Gradation Palette 14 32. Gradation Palette 15 33. Gradation mode control 34. Data bus length 35. Discharge circuit :Undefined :(00)H :(00)H :(0)H (1st line) :OFF :OFF (normal) :1/129 duty(DSE=0) :OFF :COM0 COM127 :(HV, XD, YD) = (0, 0, 0) :OFF (AIM=0) :OFF (normal) :(0, 0, 0, 0, 0, 0, 0) :OFF :Gradation display mode :1/9 bias :(0, 0, 0, 0, 0) :(0, 0, 0, 1, 1) :(0, 0, 1, 0, 1) :(0, 0, 1, 1, 1) :(0, 1, 0, 0, 1) :(0, 1, 0, 1, 1) :(0, 1, 1, 0, 1) :(0, 1, 1, 1, 1) :(1, 0, 0, 0, 1) :(1, 0, 0, 1, 1) :(1, 0, 1, 0, 1) :(1, 0, 1, 1, 1) :(1, 1, 0, 0, 1) :(1, 1, 0, 1, 1) :(1, 1, 1, 0, 1) :(1, 1, 1, 1, 1) :Variable gradation mode :8-bit data bus length :(DIS, DIS2)=(0,0)
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NJU6824
(29) Power supply ON/OFF sequences The following paragraphs describe power supply ON/OFF sequences, which are to protect the LSI from over current. (29-1) Using an external power supply
# Power supply ON sequence Logic voltage (VDD) must be always input first, and next the LCD driving voltages (V1 to V4 and VLCD) are turned on. In using the external VOUT, the VDD must be input first, next the reset operation must be performed, and finally the VOUT can be input. # Power supply OFF sequence Either the reset operation, cutting off the V1 to V4 and VLCD from the LSI by the RESb terminal or the "Power control" instruction must be performed first, and next the VDD is turned off. It is recommended that a series-resister between 50 and 100 is added on the VLCD line (or VOUT line in using only the external VOUT voltage) in order to protect the LSI from the over current.
(29-2) Using the internal power supply circuits
# Power supply ON sequence The VDD must be input first, next the reset operation must be performed, and finally the V1 to V4 and VLCD can be turned on by setting "1" to the "DCON" and "AMPON" registers of the "Power control" instruction. # Power supply OFF sequence Either the reset operation by the RESb terminal or the "Power control" instruction must be performed first, and next the input voltage for the voltage booster (VEE) and the VDD can be turned off. If the VEE is supplied from different power sources for VDD, the VEE is turned off first, and next the VDD is turned off.
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NJU6824
(30) Referential instruction sequences (30-1) Initialization in using the internal power supply circuits
VDD, VEE power ON
Wait for power-ON stabilization
RESET Input WAIT
Setting for LCD driving voltage-related functions
- EVR value - LCD bias ratio - Power control (DCON="1", AMPON="1")
End of initialization
(30-2) Display data writing
End of Initialization
Setting for display-related functions
- Initial display line - Address direction of RAM (HV, XD, YD) - Column address / -Row address (Start) - Column address / -Row address (End)
Display data write
Display ON (ON/OFF ="1") *: Before display data write / read operation, the address directions should be set first , then Column address set / Row address set of start point and end are set in order. (Display data write / read for whole display area or a portion requires the same procedure as above.) To avoid incorrect data writing into registers by noise and so forth, the written data from registers should be checked after write operation.
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NJU6824
(30-3) Power OFF
Optional status
Power save or reset operation
- All COM/SEG output VSS level.
Discharge ON
WAIT
VEE, VDD power OFF
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NJU6824
(31) Instruction table
Instruction Table (1)
Instructions Code (80 series MPU I/F) CSb RS RDb WRb RE2 RE1 RE0 D7 0 0 1 0 0/1 0/1 0/1 D6 D5 D4 Code D3 D2 D1 D0 Write display data to DDRAM Functions
Display data write
Write Data
Display data read column address (Lower) [0H] column address (Upper) [1H] row address (Lower) [2H] row address (Upper) [3H] Initial display line (Lower) [4H] Initial display line (Upper) [5H] N-line inversion (Lower) [6H] N-line inversion (Upper) [7H] Display control (1) [8H] Display control (2) [9H] Increment control [AH] Power control [BH] Duty cycle ratio [CH] Boost level [DH] LCD bias ratio [EH] RE register [FH]
0
0
0
1
0/1 0/1 0/1
Read Data
Read display data from DDRAM
0
1
1
0
0
0
0
0
0
0
0
AX3
AX2
AX1
AX0
DDRAM column address
0
1
1
0
0
0
0
0
0
0
1
AX7
AX6
AX5
AX4
DDRAM column address
0
1
1
0
0
0
0
0
0
1
0
AY3
AY2
AY1
AY0
DDRAM row address
0
1
1
0
0
0
0
0
0
1
1
*
AY6
AY5
AY4
DDRAM row address Row address for an initial COM line (Scan start line) Row address for an initial COM line (Scan start line) The number of N-line inversion
0
1
1
0
0
0
0
0
1
0
0
LA3
LA2
LA1
LA0
0
1
1
0
0
0
0
0
1
0
1
*
LA6
LA5
LA4
0
1
1
0
0
0
0
0
1
1
0
N3
N2
N1
N0
0
1
1
0
0
0
0
0
1
1
1
*
N6
N5
N4
The number of N-line inversion
SHIFT: Common direction
0
1
1
0
0
0
0
1
0
0
0
SHIFT MON
ALL ON
ON/ MON: Gradation or B/W display mode OFF ALLON: All pixels ON/OFF
ON/OFF: Display ON/OFF
0
1
1
0
0
0
0
1
0
0
1
REV
NLIN SWAP
*
REV: Reverse display ON/OFF NLIN: N-line inversion ON/OFF, SWAP: SWAP mode ON/OFF
0
1
1
0
0
0
0
1
0
1
0
AIM
HV
XD
0
1
1
0
0
0
0
1
0
1
1
AMP ON
HALT
DC ON
AIM: Read-modify-write ON/OFF HV: Increment / Decrement direction XD: Column Increment / Decrement set YD: Row Increment / Decrement set AMPON: Voltage followers ON/OFF HALT: Power save ON/OFF ACL DCON: Voltage booster ON/OFF ACL: Reset
YD DS0
0
1
1
0
0
0
0
1
1
0
0
DS3
DS2
DS1
Sets LCD duty cycle ratio
0
1
1
0
0
0
0
1
1
0
1
*
VU2
VU1
VU0
Sets boost level
0
1
1
0
0
0
0
1
1
1
0
*
B2
B1
B0
Sets LCD bias ratio
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0
RE2
RE1
RE0 RE flag set
Note 1) Note 2) Note 3)
* : Don't care. [ NH ] : Address of instruction register The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set.
- 59 -
NJU6824
Instruction Table (2)
Instructions Gradation palette A0/A8 (Lower) [0H] Gradation palette A0/A8 (Upper) [1H] Gradation palette A1/A9 (Lower) [2H] Gradation palette A1/A9 (Upper) [3H] Gradation palette A2/A10 (Lower) [4H] Gradation palette A2/A10 (Upper) [5H] Gradation palette A3/A11 (Lower) [6H] Gradation palette A3/A11 (Upper) [7H] Gradation palette A4/A12 (Lower) [8H] Gradation palette A4/A12 (Upper) [9H] Gradation palette A5/A13 (Lower) [AH] Gradation palette A5/A13 (Upper) [BH] Gradation palette A6/A14 (Lower) [CH] Gradation palette A6/A14 (Upper) [DH] RE register [FH] Code (80 series MPU I/F) CSb RS RDb WRb RE2 RE1 RE0 0 1 1 0 0 0 1 D7 0 D6 0 D5 0 Code D4 0 D3 D2 D1 D0 Functions Sets palette values to gradation palette A0(PS=0)/A8(PS=1) Sets palette values to gradation palette A0(PS=0)/A8(PS=1) Sets palette values to gradation palette A1(PS=0)/A9(PS=1) Sets palette values to gradation palette A1(PS=0)/A9(PS=1) Sets palette values to gradation palette A2(PS=0)/A10(PS=1) Sets palette values to gradation palette A2(PS=0)/A10(PS=1) Sets palette values to gradation palette A3(PS=0)/A11(PS=1) Sets palette values to gradation palette A3(PS=0)/A11(PS=1) Sets palette values to gradation palette A4(PS=0)/A12(PS=1) Sets palette values to gradation palette A4(PS=0)/A12(PS=1) Sets palette values to gradation palette A5(PS=0)/A13(PS=1) Sets palette values to gradation palette A5(PS=0)/A13(PS=1) Sets palette values to gradation palette A6(PS=0)/A14(PS=1) Sets palette values to gradation palette A6(PS=0)/A14(PS=1)
PA03/ PA02/ PA01/ PA00/ PA83 PA82 PA81 PA80
0
1
1
0
0
0
1
0
0
0
1
*
*
*
PA11/ PA91
PA04/ PA84
0
1
1
0
0
0
1
0
0
1
0
PA13/ PA12/ PA93 PA92
PA10/ PA90
0
1
1
0
0
0
1
0
0
1
1
*
*
*
PA14/ PA94
0
1
1
0
0
0
1
0
1
0
0
PA23/ PA22/ PA21/ PA20/ PA103 PA102 PA101 PA100
0
1
1
0
0
0
1
0
1
0
1
*
*
*
PA24/ PA104
0
1
1
0
0
0
1
0
1
1
0
PA33/ PA32/ PA31/ PA30/ PA113 PA112 PA111 PA110
0
1
1
0
0
0
1
0
1
1
1
*
*
*
PA34/ PA114
0
1
1
0
0
0
1
1
0
0
0
PA43/ PA42/ PA41/ PA40/ PA123 PA122 PA121 PA120
0
1
1
0
0
0
1
1
0
0
1
*
*
*
PA44/ PA124
0
1
1
0
0
0
1
1
0
1
0
PA53/ PA52/ PA51/ PA50/ PA133 PA132 PA131 PA130
0
1
1
0
0
0
1
1
0
1
1
*
*
*
PA54/ PA134
0
1
1
0
0
0
1
1
1
0
0
PA63/ PA62/ PA61/ PA60/ PA143 PA142 PA141 PA140
0
1
1
0
0
0
1
1
1
0
1
*
*
*
PA64/ PA144
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0 RE2
RE1
RE0 RE flag set
Note 1) Note 2) Note 3)
* : Don't care. [ NH ] : Address of Instruction register The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set.
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NJU6824
Instruction Table (3)
Instructions Gradation palette A7/A15 (Lower) [0H] Gradation palette A7/A15 (Upper) [1H] Gradation palette B0/B8 (Lower) [2H] Gradation palette B0/B8 (Upper) [3H] Gradation palette B1/B9 (Lower) [4H] Gradation palette B1/B9 (Upper) [5H] Gradation palette B2/B10 (Lower) [6H] Gradation palette B2/B10 (Upper) [7H] Gradation palette B3/B11 (Lower) [8H] Gradation palette B3/B11 (Upper) [9H] Gradation palette B4/B12 (Lower) [AH] Gradation palette B4/B12 (Upper) [BH] Gradation palette B5/B13 (Lower) [CH] Gradation palette B5/B13 (Upper) [DH] RE register [FH] Code (80 series MPU I/F) CSb RS RDb WRb RE2 RE1 RE0 0 1 1 0 0 1 0 D7 0 D6 0 D5 0 Code D4 0 D3 D2 D1 D0 Functions Sets palette values to gradation palette A7(PS=0)/A15(PS=1) Sets palette values to gradation palette A7(PS=0)/A15(PS=1) Sets palette values to gradation palette B0(PS=0)/B8(PS=1) Sets palette values to gradation palette B0(PS=0)/B8(PS=1) Sets palette values to gradation palette B1(PS=0)/B9(PS=1) Sets palette values to gradation palette B1(PS=0)/B9(PS=1) Sets palette values to gradation palette B2(PS=0)/B10(PS=1) Sets palette values to gradation palette B2(PS=0)/B10(PS=1) Sets palette values to gradation palette B3(PS=0)/B11(PS=1) Sets palette values to gradation palette B3(PS=0)/B11(PS=1) Sets palette values to gradation palette B4(PS=0)/B12(PS=1) Sets palette values to gradation palette B4(PS=0)/B12(PS=1) Sets palette values to gradation palette B5(PS=0)/B13(PS=1) Sets palette values to gradation palette B5(PS=0)/B13(PS=1)
PA73/ PA72/ PA71/ PA70/ PA153 PA152 PA151 PA150
0
1
1
0
0
1
0
0
0
0
1
*
*
*
PA74/ PA154
0
1
1
0
0
1
0
0
0
1
0
PB03/ PB02/ PB01/ PB00/ PB83 PB82 PB81 PB80
0
1
1
0
0
1
0
0
0
1
1
*
*
*
PB04/ PB84
0
1
1
0
0
1
0
0
1
0
0
PB13/ PB12/ PB11/ PB10/ PB93 PB92 PB91 PB90
0
1
1
0
0
1
0
0
1
0
1
*
*
*
PB14/ PB94
0
1
1
0
0
1
0
0
1
1
0
PB23/ PB22/ PB21/ PB20/ PB103 PB102 PB101 PB100
0
1
1
0
0
1
0
0
1
1
1
*
*
*
PB24/ PB104
0
1
1
0
0
1
0
1
0
0
0
PB33/ PB32/ PB31/ PB30/ PB113 PB112 PB111 PB110
0
1
1
0
0
1
0
1
0
0
1
*
*
*
PB34/ PB114
0
1
1
0
0
1
0
1
0
1
0
PB43/ PB42/ PB41/ PB40/ PB123 PB122 PB121 PB120
0
1
1
0
0
1
0
1
0
1
1
*
*
*
PB44/ PB124
0
1
1
0
0
1
0
1
1
0
0
PB53/ PB52/ PB51/ PB50/ PB133 PB132 PB131 PB130
0
1
1
0
0
1
0
1
1
0
1
*
*
*
PB54/ PB134
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0 RE2
RE1
RE0 RE flag set
Note 1) Note 2) Note 3)
* : Don't care. [ NH ] : Address of Instruction register The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set.
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NJU6824
Instruction Table (4)
Instructions Gradation palette B6/B14 (Lower) [0H] Gradation palette B6/B14 (Upper) [1H] Gradation palette B7/B15 (Lower) [2H] Gradation palette B7/B15 (Upper) [3H] Gradation palette C0/C8 (Lower) [4H] Gradation palette C0/C8 (Upper) [5H] Gradation palette C1/C9 (Lower) [6H] Gradation palette C1/C9 (Upper) [7H] Gradation palette C2/C10 (Lower) [8H] Gradation palette C2/C10 (Upper) [9H] Gradation palette C3/C11 (Lower) [AH] Gradation palette C3/C11 (Upper) [BH] Gradation palette C4/C12 (Lower) [CH] Gradation palette C4/C12 (Upper) [DH] RE register [FH] Code (80 series MPU I/F) CSb RS RDb WRb RE2 RE1 RE0 0 1 1 0 0 1 1 D7 0 D6 0 D5 0 Code D4 0 D3 D2 D1 D0 Functions Sets palette values to gradation palette B6(PS=0)/B14(PS=1) Sets palette values to gradation palette B6(PS=0)/B14(PS=1) Sets palette values to gradation palette B7(PS=0)/B15(PS=1) Sets palette values to gradation palette B7(PS=0)/B15(PS=1) Sets palette values to gradation palette C0(PS=0)/C8(PS=1) Sets palette values to gradation palette C0(PS=0)/C8(PS=1) Sets palette values to gradation palette C1(PS=0)/C9(PS=1) Sets palette values to gradation palette C1(PS=0)/C9(PS=1) Sets palette values to gradation palette C2(PS=0)/C10(PS=1) Sets palette values to gradation palette C2(PS=0)/C10(PS=1) Sets palette values to gradation palette C3(PS=0)/C11(PS=1) Sets palette values to gradation palette C3(PS=0)/C11(PS=1) Sets palette values to gradation palette C4(PS=0)/C12(PS=1) Sets palette values to gradation palette C4(PS=0)/C12(PS=1)
PB63/ PB62/ PB61/ PB60/ PB143 PB142 PB141 PB140
0
1
1
0
0
1
1
0
0
0
1
*
*
*
PB64/ PB144
0
1
1
0
0
1
1
0
0
1
0
PB73/ PB72/ PB71/ PB70/ PB153 PB152 PB151 PB150
0
1
1
0
0
1
1
0
0
1
1
*
PC03/ PC83
*
PC02/ PC82
*
PC01/ PC81
PB74/ PB154
0
1
1
0
0
1
1
0
1
0
0
PC00/ PC80
0
1
1
0
0
1
1
0
1
0
1
*
PC13/ PC93
*
PC12/ PC92
*
PC11/ PC91
PC04/ PC84
0
1
1
0
0
1
1
0
1
1
0
PC10/ PC90
0
1
1
0
0
1
1
0
1
1
1
*
*
*
PC14/ PC94
0
1
1
0
0
1
1
1
0
0
0
PC23/ PC22/ PC21/ PC20/ PC103 PC102 PC101 PC100
0
1
1
0
0
1
1
1
0
0
1
*
*
*
PC24/ PC104
0
1
1
0
0
1
1
1
0
1
0
PC33/ PC32/ PC31/ PC30/ PC113 PC112 PC111 PC110
0
1
1
0
0
1
1
1
0
1
1
*
*
*
PC34/ PC114
0
1
1
0
0
1
1
1
1
0
0
PC43/ PC42/ PC41/ PC40/ PC123 PC122 PC121 PC120
0
1
1
0
0
1
1
1
1
0
1
*
*
*
PC44/ PC124
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0 RE2
RE1
RE0 RE flag set
Note 1) Note 2) Note 3)
* : Don't care. [ NH ] : Address of Instruction register The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set.
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NJU6824
Instruction Table (5)
Instructions Gradation palette C5/C13 (Lower) [0H] Gradation palette C5/C13 (Upper) [1H] Gradation palette C6/C14 (Lower) [2H] Gradation palette C6/C14 (Upper) [3H] Gradation palette C7/C15 (Lower) [4H] Gradation palette C7/C15 (Upper) [5H] Initial COM line [6H] Display control Signal/ Duty Select [7H] Gradation mode control [8H]
Data bus length
Code (80 series MPU I/F) CSb RS RDb WRb RE2 RE1 RE0 0 1 1 0 1 0 0 D7 0 D6 0 D5 0
Code D4 0 D3 D2 D1 D0
Functions Sets palette values to gradation palette C5(PS=0)/C13(PS=1) Sets palette values to gradation palette C5(PS=0)/C13(PS=1) Sets palette values to gradation palette C6(PS=0)/C14(PS=1) Sets palette values to gradation palette C6(PS=0)/C14(PS=1) Sets palette values to gradation palette C7(PS=0)/C15(PS=1) Sets palette values to gradation palette C7(PS=0)/C15(PS=1) Sets scan-starting common driver SON : Display clock ON/OFF DSE : Duty-1 ON/OFF
PWM : Variable/Fixed gradation mode
PC53/ PC52/ PC51/ PC50/ PC133 PC132 PC131 PC130
0
1
1
0
1
0
0
0
0
0
1
*
*
*
PC54/ PC134
0
1
1
0
1
0
0
0
0
1
0
PC63/P PC62/ PC61/ PC60/ C143 PC142 PC141 PC140
0
1
1
0
1
0
0
0
0
1
1
*
*
*
PC64/ PC154
0
1
1
0
1
0
0
0
1
0
0
PC73/ PC72/ PC71/ PC70/ PC153 PC152 PC151 PC150
0
1
1
0
1
0
0
0
1
0
1
*
*
*
PC74/ PC154
0
1
1
0
1
0
0
0
1
1
0
SC3
SC2
SC1
SC0
0 0 0
1 1 1
1 1 1
0 0 0
1 1 1
0 0 0
0 0 0
0 1 1
1 0 0
1 0 0
1 0 1
*
*
DSE SON
PWM C256 FDC1 FDC2 C256 : 256-Color Mode ON/OFF
FDC : Boost Clock ABS : ABS mode ON/OFF
[9H] EVR control (Lower) [AH] EVR control (Upper) [BH] Frequency control [DH] Discharge ON/OFF [EH] RE register [FH]
Instruction register address
*
ABS CKS
WLS CKS : Internal/external oscilation
WLS : Display data Length
0
1
1
0
1
0
0
1
0
1
0
DV3
DV2
DV1
DV0
Sets EVR level (Lower bit) Sets EVR level (Upper bit) Oscillation frequency Discharge the electric charge in capacitors on V1 to V4 and VLCD
0
1
1
0
1
0
0
1
0
1
1
*
DV6
DV5
DV4
0
1
1
0
1
0
0
1
1
0
1
*
RF2
RF1
RF0
0
1
1
0
1
0
0
1
1
1
0
*
*
DIS2 DIS
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0 RE2
RE1
RE0 RE flag
[CH]
Instruction register read
0
1
1
0
1
0
0
1
1
0
0
Reading address
Sets instruction register address
0
1
0
1
0/1 0/1 0/1
*
*
*
*
Read Data
Read out instruction register data
Note 1) Note 2) Note 3)
* : Don't care. [ NH ] : Address of Instruction register The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set. Note 4) CKS=0: Internal oscillation mode (default) CKS=1: External oscillation mode
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NJU6824
Instruction Table (6)
Instructions Window end column address (Lower) [0H] Window end column address (Upper) [1H] Window end row address (Lower) [2H] Window end row address (Upper) [3H] Initial reverse line (Lower) [4H] Initial reverse line (Upper) [5H] Last reverse line (Lower) [6H] Last reverse line (Upper) [7H] Reverse line display ON/OFF [8H] Gradation palette setting control / Icon SEG address set [9H] PWM control [AH] RE register [FH] Code (80 series MPU I/F) CSb RS RDb WRb RE2 RE1 RE0 D7 0 1 1 0 1 0 1 0 D6 0 D5 0 Code D4 0 D3
EX3
D2
EX2
D1
EX1
D0
EX0
Functions
Sets column address for end point
0
1
1
0
1
0
1
0
0
0
1
EX7
EX6
EX5
EX4
Sets column address for end point
0
1
1
0
1
0
1
0
0
1
0
EY3
EY2
EY1
EY0
Sets row address for end point
0
1
1
0
1
0
1
0
0
1
1
*
EY6
EY5
EY4
Sets row address for end point
0
1
1
0
1
0
1
0
1
0
0
LS3
LS2
LS1
LS0
Sets address for reverse line
0
1
1
0
1
0
1
0
1
0
1
*
LS6
LS5
LS4
Sets address for reverse line
0
1
1
0
1
0
1
0
1
1
0
LE3
LE2
LE1
LE0
Sets address for reverse line
0
1
1
0
1
0
1
0
1
1
1
*
LE6
LE5
LE4
Sets address for reverse line
BT : Blink type setting LREV : Reverse line display ON/OFF
0
1
1
0
1
0
1
1
0
0
0
*
*
BT
LREV
0
1
1
0
1
0
1
1
0
0
1
*
*
DMY PS
PS : gradation setting DMY : Icon SEG address set Sets PWM mode
0
1
1
0
1
0
1
1
0
1
0
PWM PWM PWM PWM S A B C
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0 RE2
RE1
RE0 RE flag
Note 1) Note 2) Note 3)
* : Don't care. [ NH ] : Address of Instruction register The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set.
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NJU6824
(32) Instruction descriptions This chapter provides detail descriptions and instruction registers. Nonexistent instruction codes must not be set into the LSI. (32-1) Display data write The "Display data write" instruction is used to write 8-bit display data into the DDRAM. CSb 0 RS 0 RDb WRb 1 0 RE2 0/1 RE1 0/1 RE0 0/1 D7 D6 D5 D4 D3 D2 D1 D0
Display data
(32-2) Display data read The "Display data read" instruction is used to read out 8-bit display data from the DDRAM, where the column address and row address must be specified beforehand by the "column address" and "row address" instructions. The dummy read is required just after the "column address" and "row address" instructions. CSb 0 RS 0 RDb WRb 0 1 RE2 0/1 RE1 0/1 RE0 0/1 D7 D6 D5 D4 D3 D2 D1 D0
Display data
(32-3) Column address The "column address" instruction is used to specify the column address for the display data's reading and writing operations. It requires dual bytes for lower 4-bit and upper 4-bit data. The instruction for the lower 4-bit data must be executed first, next the instruction for the upper 4-bit. CSb 0 CSb 0 RS 1 RS 1 RDb WRb 1 0 RE2 0 RE2 0 RE1 0 RE1 0 RE0 0 RE0 0 D7 0 D7 0 D6 0 D6 0 D5 0 D5 0 D4 0 D4 1 D3 AX3 D3 AX7 D2 AX2 D2 AX6 D1 AX1 D1 AX5 D0 AX0 D0 AX4
RDb WRb 1 0
(32-4) Row address The "row address" instruction is used to specify the row address for the display data read and write operations. It requires dual bytes for lower 4-bit and upper 3-bit data. The instruction for the lower 4-bit data must be executed first, next the instruction for upper 3-bit. The row address is specified in between 00H and 7FH. The setting for nonexistent row address between 80H and FFH is prohibited. CSb 0 CSb 0 RS 1 RS 1 RDb WRb 1 0 RE2 0 RE2 0 RE1 0 RE1 0 RE0 0 RE0 0 D7 0 D7 0 D6 0 D6 0 D5 1 D5 1 D4 0 D4 1 D3 AY3 D3 * D2 AY2 D2 AY6 D1 AY1 D1 AY5 D0 AY0 D0 AY4
RDb WRb 1 0
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NJU6824
(32-5) Initial display line The "Initial display line" instruction is used to specify the line address corresponding to the initial COM line. The initial COM line specified by the "Initial COM line" instruction and indicates the common driver that starts scanning data. CSb 0 CSb 0 RS 1 RS 1 RDb WRb 1 0 RE2 0 RE2 0 RE1 0 RE1 0 RE0 0 RE0 0 D7 0 D7 0 D6 1 D6 1 D5 0 D5 0 D4 0 D4 1 D3 LA3 D3 * D2 LA2 D2 LA6 D1 LA1 D1 LA5 D0 LA0 D0 LA4
RDb WRb 1 0
LA6 0 0
LA5 0 0
LA4 0 0
LA3 0 0 : : 1
LA2 0 0
LA1 0 0
LA0 0 1
Line address 0 1 : :
1
1
1
1
1
1
127
(32-6) N-line inversion The "N-line inversion" instruction is used to control the alternate rates of the liquid crystal direction. It is programmed to select the N value between 2 and 128, and the FR signal toggles once every N lines by setting "1" into the "NLIN" register of the "Display control (2)" instruction. When the N-line inversion is disabled by setting "0" into the "NLIN" register, the FR signal toggles by the frame. CSb 0 CSb 0 RS 1 RS 1 RDb WRb 1 0 RE2 0 RE2 0 RE1 0 RE1 0 RE0 0 RE0 0 D7 0 D7 0 D6 1 D6 1 D5 1 D5 1 D4 0 D4 1 D3 N3 D3 * D2 N2 D2 N6 D1 N1 D1 N5 D0 N0 D0 N4
RDb WRb 1 0
N6 0 0
N5 0 0
N4 0 0
N3 0 0 : : 0
N2 0 0
N1 0 0
N0 0 1
N value Inhibited 2 : :
0
1
0
0
0
0
128
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NJU6824
# N-line Inversion Timing (1/129 duty cycle ratio)
N-line inversion OFF
1st line 2nd line 3rd line 128th line 1st line 129th line
CL FLM FR
N-line inversion ON
1st line 3rd line
N-line control
2nd line N line 1st line 2nd line
CL FR
(32-7) Display control (1) The "Display control (1)" instruction is used to control display conditions by setting the "Display ON/OFF", "All pixels ON/OFF", "Display mode" and "Common direction" registers. CSb 0 RS 1 RDb WRb 1 0 RE2 0 RE1 0 RE0 0 D7 1 D6 0 D5 0 D4 0 D3
SHIFT
D2
MON
D1
D0
ALLON ON/OFF
# ON/OFF register
ON/OFF=0 ON/OFF=1 : Display OFF (All COM/SEG output Vss level.) : Display ON
# All ON register The "All pixels ON/OFF" register is used to turn on all pixels without changing display data of the DDRAM. The setting for the "All pixels ON/OFF" register has a priority over the "Reverse display ON/OFF" register.
ALLON=0 ALLON=1 : Normal : All pixels turn on.
# MON register
MON=0 MON=1 : Gradation mode : B&W mode
# SHIFT register
SHIFT=0 SHIFT=1 : COM0 COM127 : COM127 COM0
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NJU6824
(32-8) Display control (2) The "Display control (2)" instruction is used to control display conditions by setting the "SWAP mode ON/OFF", "N-line inversion ON/OFF" and "Reverse display ON/OFF" registers. CSb 0 RS 1 RDb WRb 1 0 RE2 0 RE1 0 RE0 0 D7 1 D6 0 D5 0 D4 1 D3
REV
D2
NLIN
D1
SWAP
D0
*
# SWAP register The "SWAP" register is used to reverse the arrangement of display data in the DDRAM.
SWAP=0 SWAP=1 : SWAP mode OFF : SWAP mode ON SWAP="0" Write data D7 D6 D5 D4 D3 D2 D1 D0 (Normal)
SWAP="1" D7 D6 D5 D4 D3 D2 D1 D0
RAM data
D7 d6 d5 d4 d3 d2 d1 d0
d0 d1 d2 d3 d4 d5 d6 d7
Read data
D 7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
# NLIN register The "NLIN" is used to enable or disable the N-line inversion.
NLIN=0 NLIN=1 : N-line inversion OFF : N-line inversion ON (The FR signal toggles by the flame.) (The FR signal toggles once every N frames.)
# REV register The "REV" register is used to enable or disable the reverse display mode that reverses the polarity of display data without changing display data of the DDRAM.
REV=0 REV=1 REV 0 1 : Reverse display mode OFF : Reverse display mode ON Display Normal Reverse DDRAM data Display data 0 0 1 1 0 1 1 0
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NJU6824
(32-9) Increment control The "Increment control" instruction is used for the increment mode. In using the auto-increment mode, DDRAM address automatically increments (+1) whenever the DDRAM is accessed by the "Display data write" or "Display data read" instruction. Therefore, once "Display data write" or "Display data read" instruction is established, it is possible to continuously access to the DDRAM without the "column address" and "row address" instructions. The settings for the "AIM", "HV", "XD" and "YD" registers are listed in the following tables. CSb 0 RS 1 RDb WRb 1 0 RE2 0 RE1 0 RE0 0 D7 1 D6 0 D5 1 D4 0 D3 AIM D2 HV D1 XD D0 YD
# AIM, HV, XD and YD registers
AIM 0 1 Increment mode
Auto-increment for both of the display data read and write operations Auto-increment for the display write operation (Read modify write)
Note 1 2
Note 1) It is effective for usual operations accessing successive addresses. Note 2) It is effective for the read-modify-write operation. HV 0 0 0 0 1 1 1 1 XD 0 0 1 1 0 0 1 1 YD 0 1 0 1 0 1 0 1 Increment / Decrement mode / Scanning Direction Column increment / Row increment / Horizontal direction Column increment / Row decrement / Horizontal direction Column decrement / Row increment / Horizontal direction Column decrement / Row decrement / Horizontal direction Column increment / Row increment / Vertical direction Column increment / Row decrement / Vertical direction Column decrement / Row increment / Vertical direction Column decrement / Row decrement / Vertical direction
For the window area designation, the address directions of RAM (HV, XD, YD) must be set first, and Column address and Row of Start point must be set second, Column address and Row of Stop point must be set third, then RAM should be accessed. Low address must be set first and High address must be set second in all of addresses. The directions of HV, XD, YD should be check to keep the area in RAM.
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NJU6824
(32-10) Power control CSb 0 RS 1 RDb WRb RE2 1 0 0 RE1 0 RE0 0 D7 1 D6 0 D5 1 D4 1 D3
AMPON
D2
HALT
D1
DCON
D0
ACL
# ACL register The "ACL" register is used to initialize the internal power supply circuits.
ACL=0 ACL=1 : Initialization OFF (Normal) : Initialization ON
When the data of the "ACL register" is read out by the "Instruction register read" instruction, the read-out data is "1" during the initialization and "0" after the initialization. This initialization is performed by using the signal produced by 2 clocks on the OSC1. For this reason, the wait time for 2 clocks of the OSC1 is necessary until next instruction.
# DCON register The "DCON" register is used to enable or disable the voltage booster.
DCON=0 DCON=1 : Voltage booster OFF : Voltage booster ON
# HALT register The "HALT" register is used to enable or disable the power save mode. It is possible to reduce operating current down to stand-by level. The internal status in the power save mode is listed below.
HALT=0 HALT=1 : Power save OFF (Normal) : Power save ON
Internal status in the power save mode
* The oscillation circuits and internal power supply circuits are halted. * All segment and common drivers output VSS level. * The clock input into the OSC1 is inhibited. * The display data in the DDRAM is maintained. * The operational modes before the power save mode are maintained. * The V1 to V4 and VLCD are in the high impedance.
As a power save ON sequence, the "Display OFF" must be executed first, next the "Power save ON" instruction, and then all common and segment drivers output the VSS level. And as power save OFF sequence, the "Power save OFF" instruction is executed first, next the "Display ON" instruction. If the "Power save OFF" instruction is executed in the display ON status, unexpected pixels may instantly turn on.
# AMPON register The "AMPON" register is used to enable or disable the voltage followers, voltage regulator and EVR.
AMPON=0 AMPON=1 : The voltage followers, voltage regulator and the EVR OFF : The voltage followers, voltage regulator and the EVR ON
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NJU6824
(32-11) Duty cycle ratio The "Duty cycle ratio" instruction is used to select LCD duty cycle ratio for the partial display function. The partial display function specifies some parts of display area on a LCD panel in the condition of lower duty cycle ratio, lower LCD bias ratio, lower boost level and lower LCD driving voltage. Therefore, it is possible to optimize the LSI's conditions with extremely low power consumption. CSb 0 RS 1 DS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RDb WRb RE2 1 DS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 DS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 RE1 0 DS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RE0 0 D7 1 D6 1 D5 0 D4 0 D3 DS3 D2 DS2 D1 DS1 D0 DS0
Duty cycle ratio DSE=0 DSE=1 1/129 1/128 1/121 1/120 1/113 1/112 1/105 1/104 1/97 1/96 1/89 1/88 1/81 1/80 1/73 1/72 1/65 1/64 1/56 1/57 1/48 1/49 1/41 1/40 1/33 1/32 1/25 1/24 1/17 1/16 Inhibited
Row way displays 128 commons 120 commons 112 commons 104 commons 96 commons 88 commons 80 commons 72 commons 64 commons 56 commons 48 commons 40 commons 32 commons 24 commons 16 commons
The duty cycle ratio is controlled by the "DS3 to DS0" registers of the "Duty cycle ratio" instruction and the "DSE" register of the "Display Clock / Duty-1" instruction. DSE="0" DSE="1" : The number of commons + 1 (Duty cycle ratio in the default setting) : The number of commons (Duty-1)
When the "DSE" is "0", all common drivers output non-selective levels in period of last common. And the segment drivers output the same data for the last line as the data for previous line: For th th instance they output the same data for the 128 and 129 lines when the duty cycle ratio is set to 1/129. For the setting of the "DSE" register, see (32-17) "Display clock / Duty-1". (32-12) Boost level The "Boost level" is used to select the multiple of the voltage booster for the partial display function. CSb 0 RS 1 RDb WRb 1 0 VU2 0 0 0 0 1 1 1 1 RE2 0 VU1 0 0 1 1 0 0 1 1 RE1 0 VU0 0 1 0 1 0 1 0 1 RE0 0 D7 1 D6 1 D5 0 D4 1 D3 * D2 VU2 D1 VU1 D0 VU0
Boost level 1-time (No boost) 2-time 3-time 4-time 5-time 6-time Inhibited Inhibited
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NJU6824
(32-13) LCD bias ratio The "LCD bias ratio" is used to select the LCD bias ratio for the partial display function. CSb 0 RS 1 RDb WRb 1 0 RE2 0 RE1 0 RE0 0 D7 1 D6 1 D5 1 D4 0 D3 * D2 B2 D1 B1 D0 B0
B2 0 0 0 0 1 1 1 1
B1 0 0 1 1 0 0 1 1
B0 0 1 0 1 0 1 0 1
LCD bias ratio 1/9 1/8 1/7 1/6 1/5 1/10 1/11 1/12
(32-14) RE flag The "RE flag" registers are used to determine the contents for the RE registers (RE2, RE1 and RE0) and it is possible to access to the instruction registers. The data in the "TST0" register must be "0", and it is used maker tests only. CSb 0 RS 1 RDb WRb 1 0 RE2 0/1 RE1 0/1 RE0 0/1 D7 1 D6 1 D5 1 D4 1 D3 TST0 D2 RE2 D1 RE1 D0 RE0
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NJU6824
(32-15) Gradation palette A, B and C CSb 0 RS 1 RDb WRb 1 0 RE2 0 RE1 0 RE0 1 D7 0 D6 0 D5 0 D4 0 D3
PA03/ PA83
D2
PA02/ PA82
D1
PA01/ PA81
D0
PA00/ PA80
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 0
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PA04/ PA84
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 0
D6 0
D5 1
D4 0
D3
PA13/ PA93
D2
PA12/ PA92
D1
PA11/ PA91
D0
PA10/ PA90
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 0
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0
PA14/ PA94
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 0
D6 1
D5 0
D4 0
D3
PA23/ PA103
D2
PA22/ PA102
D1
PA21/ PA101
D0
PA20/ PA100
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 0
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PA24/ PA104
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 0
D6 1
D5 1
D4 0
D3
PA33/ PA113
D2
PA32/ PA112
D1
PA31/ PA111
D0
PA30/ PA110
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 0
D6 1
D5 1
D4 1
D3 *
D2 *
D1 *
D0
PA34/ PA114
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 1
D6 0
D5 0
D4 0
D3
PA43/ PA123
D2
PA42/ PA122
D1
PA41/ PA121
D0
PA40/ PA120
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NJU6824
CSb 0 RS 1 RDb WRb 1 0 RE2 0 RE1 0 RE0 1 D7 1 D6 0 D5 0 D4 1 D3 * D2 * D1 * D0
PA44/ PA124
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 1
D6 0
D5 1
D4 0
D3
PA53/ PA133
D2
PA52/ PA132
D1
PA51/ PA131
D0
PA50/ PA130
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 1
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0
PA54/ PA134
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 1
D6 1
D5 0
D4 0
D3
PA63/ PA143
D2
PA62/ PA142
D1
PA61/ PA141
D0
PA60/ PA140
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 0
RE0 1
D7 1
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PA64/ PA144
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 0
D6 0
D5 0
D4 0
D3
PA73/ PA153
D2
PA72/ PA152
D1
PA71/ PA151
D0
PA70/ PA150
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 0
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PA74/ PA154
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 0
D6 0
D5 1
D4 0
D3
PB03/ PB83
D2
PB02/ PB82
D1
PB01/ PB81
D0
PB00/ PB80
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 0
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0
PB04/ PB84
- 74 -
NJU6824
CSb 0 RS 1 RDb WRb 1 0 RE2 0 RE1 1 RE0 0 D7 0 D6 1 D5 0 D4 0 D3
PB13/ PB93
D2
PB12/ PB92
D1
PB11/ PB91
D0
PB10/ PB90
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 0
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PB14/ PB94
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 0
D6 1
D5 1
D4 0
D3
PB23/ PB103
D2
PB22/ PB102
D1
PB21/ PB101
D0
PB20/ PB100
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 0
D6 1
D5 1
D4 1
D3 *
D2 *
D1 *
D0
PB24/ PB104
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 1
D6 0
D5 0
D4 0
D3
PB33/ PB113
D2
PB32/ PB112
D1
PB31/ PB111
D0
PB30/ PB110
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 1
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PB34/ PB114
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 1
D6 0
D5 1
D4 0
D3
PB43/ PB123
D2
PB42/ PB122
D1
PB41/ PB121
D0
PB40/ PB120
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 1
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0
PB44/ PB124
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 0
D7 1
D6 1
D5 0
D4 0
D3
PB53/ PB133
D2
PB52/ PB132
D1
PB51/ PB131
D0
PB50/ PB130
- 75 -
NJU6824
CSb 0 RS 1 RDb WRb 1 0 RE2 0 RE1 1 RE0 0 D7 1 D6 1 D5 0 D4 1 D3 * D2 * D1 * D0
PB54/ PB134
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 0
D6 0
D5 0
D4 0
D3
PB63/ PB143
D2
PB62/ PB142
D1
PB61/ PB141
D0
PB60/ PB140
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 0
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PB64/ PB144
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 0
D6 0
D5 1
D4 0
D3
PB73/ PB153
D2
PB72/ PB152
D1
PB71/ PB151
D0
PB70/ PB150
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 0
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0
PB74/ PB154
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 0
D6 1
D5 0
D4 0
D3
PC03/ PC83
D2
PC02/ PC82
D1
PC01/ PC81
D0
PC00/ PC80
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 0
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PC04/ PC84
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 0
D6 1
D5 1
D4 0
D3
PC13/ PC93
D2
PC12/ PC92
D1
PC11/ PC91
D0
PC10/ PC90
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 0
D6 1
D5 1
D4 1
D3 *
D2 *
D1 *
D0
PC14/ PC94
- 76 -
NJU6824
CSb 0 RS 1 RDb WRb 1 0 RE2 0 RE1 1 RE0 1 D7 1 D6 0 D5 0 D4 0 D3
PC23/ PC103
D2
PC22/ PC102
D1
PC21/ PC101
D0
PC20/ PC100
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 1
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PC24/ PC104
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 1
D6 0
D5 1
D4 0
D3
PC33/ PC113
D2
PC32/ PC112
D1
PC31/ PC111
D0
PC30/ PC110
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 1
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0
PC34/ PC114
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 1
D6 1
D5 0
D4 0
D3
PC43/ PC123
D2
PC42/ PC122
D1
PC41/ PC121
D0
PC40/ PC120
CSb 0
RS 1
RDb WRb 1 0
RE2 0
RE1 1
RE0 1
D7 1
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PC44/ PC124
CSb 0
RS 1
RDb WRb 1 0
RE2 1
RE1 0
RE0 0
D7 0
D6 0
D5 0
D4 0
D3
PC53/ PC133
D2
PC52/ PC132
D1
PC51/ PC131
D0
PC50/ PC130
CSb 0
RS 1
RDb WRb 1 0
RE2 1
RE1 0
RE0 0
D7 0
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PC54/ PC134
CSb 0
RS 1
RDb WRb 1 0
RE2 1
RE1 0
RE0 0
D7 0
D6 0
D5 1
D4 0
D3
PC63/ PC143
D2
PC62/ PC142
D1
PC61/ PC141
D0
PC60/ PC140
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NJU6824
CSb 0 RS 1 RDb WRb 1 0 RE2 1 RE1 0 RE0 0 D7 0 D6 0 D5 1 D4 1 D3 * D2 * D1 * D0
PC64/ PC144
CSb 0
RS 1
RDb WRb 1 0
RE2 1
RE1 0
RE0 0
D7 0
D6 1
D5 0
D4 0
D3
PC73/ PC153
D2
PC72/ PC152
D1
PC71/ PC151
D0
PC70/ PC150
CSb 0
RS 1
RDb WRb 1 0
RE2 1
RE1 0
RE0 0
D7 0
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0
PC74/ PC154
Gradation Palette Table (Variable gradation mode, PWM="0" and MON="0") (Palette Aj, Palette Bj, Palette Cj, (j=0 to 15)) Palette Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Gradation Level 0/31 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Gradation Palette 7 Initial Value Gradation Palette 6 Initial Value Gradation Palette 5 Initial Value Gradation Palette 4 Initial Value Gradation Palette 3 Initial Value Gradation Palette2 Initial Value Gradation Palette 1 Initial Value Note Gradation Palette 0 Initial Value Palette Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 000 000 001 001 010 010 011 011 100 100 101 101 110 110 111 111 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation Level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Gradation Palette 15 Initial Value Gradation Palette 14 Initial Value Gradation Palette 13 Initial Value Gradation Palette 12 Initial Value Gradation Palette 11 Initial Value Gradation Palette 10 Initial Value Gradation Palette 9 Initial Value Gradation Palette 8 Initial Value Note
- 78 -
NJU6824
(32-16) Initial COM line The "Initial COM line" instruction is used to specify the common driver that starts scanning the display data. The line address, corresponding to the initial COM line, is specified by the "Initial display line" instruction. CSb 0 RS 1 RDb WRb 1 0 RE2 1 RE1 0 RE0 0 D7 0 D6 1 D5 1 D4 0 D3 SC3 D2 SC2 D1 SC1 D0 SC0
SC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
SC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Initial COM line (SHIFT=0) COM0 COM4 COM8 COM16 COM24 COM32 COM40 COM48 COM56 COM64 COM72 COM80 COM88 COM96 COM104 COM112
Initial COM line (SHIFT=1) COM127 COM123 COM119 COM111 COM103 COM95 COM87 COM79 COM71 COM63 COM55 COM47 COM39 COM31 COM23 COM15
SHIFT=0: Positive scan direction SHIFT=1: Negative scan direction
(for instance, COM0 COM127) (for instance, COM127 COM0)
(32-17) Display clock / Duty-1 The "Display clock / Duty-1" instruction is used to enable or disable the display clocks (CL, FLM, FR, and CLK), and to control ON/OFF of the "Duty-1". For more detail about the "Duty-1", see (32-11) "Duty cycle ratio". CSb 0 RS 1 RDb WRb 1 0 RE2 1 RE1 0 RE0 0 D7 0 D6 1 D5 1 D4 1 D3 * D2 * D1 DSE D0
SON
SON=0: SON=1: DSE=0: DSE=1:
CL, FLM, FR, and CLK outputs level "0". CL, FLM, FR, and CLK outputs are active. Duty -1 OFF Duty -1 ON
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NJU6824
(32-18) Gradation mode control The "Gradation mode control" is used to select display mode as follows. CSb 0 RS 1 RDb WRb 1 0 RE2 1 RE1 0 RE0 0 D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0
PWM C256 FDC1 FDC2
# PWM register
PWM=0: PWM=1: Variable gradation mode (Variable 16-gradation levels out of 32-gradation level of the gradation palette) Fixed gradation mode (Fixed 8-gradation levels)
# C256 register
C256=0 C256=1 256-color mode OFF (4,096-color in the default setting) 256-color mode ON
# FDC1 and FDC2 register
FDC1 0 0 1 1 FDC2 0 1 0 1 Boost Clock x1 x2 x4 x1/2
- 80 -
NJU6824
(32-19) Data bus length The "Data bus length" instruction is used to select the 8- or 16- bit data bus length and determine the internal or external oscillation. In the 16-bit data bus mode, instruction data must be 16-bit (D15 to D0) as well as display data. However, for the access to the instruction registers, the lower 8-bit data (D7 to D0) of the 16-bit data is valid. For the access to the DDRAM, all of the 16-bit data (D15 to D0) is valid. CSb 0 RS 1 RDb WRb 1 0 RE2 1 RE1 0 RE0 0 D7 1 D6 0 D5 0 D4 1 D3 * D2 ABS D1 D0
CKS WLS
# ABS register
ABS=0: ABS=1: ABS mode OFF (normal) ABS mode ON
# WLS register
WLS=0: WLS =1: 8-bit data bus length 16-bit data bus length
# CKS register
CKS =0: CKS =1: Internal oscillation (The OSC1 terminal must be fixed "1" or "0".) External oscillation (By the external clock into the OSC1 or external resister between the OSC1 and OSC2. OSC2 should be open when clock is inputted from OSC1.)
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NJU6824
(32-20) EVR control The "EVR control" instruction is used to fine-tune the LCD driving voltage (VLCD) so that it is possible to optimize the contrast level for a LCD panel. This instruction must be programmed by upper 3-bit data first, next lower 4-bit data. And it becomes enabled when the lower 4-bit data is programmed, so that it can prevent unexpected high voltage for the VLCD from being generated. CSb 0 CSb 0 RS 1 RS 1 RDb WRb 1 0 RE2 1 RE2 1 DV5 0 0 DV4 0 0 RE1 0 RE1 0 DV3 0 0 : : 1 RE0 0 RE0 0 DV2 0 0 D7 1 D7 1 DV1 0 0 D6 0 D6 0 DV0 0 1 D5 1 D5 1 D4 0 D4 1 VLCD Low : : : High D3 DV3 D3 * D2 DV2 D2 DV6 D1 DV1 D1 DV5 D0 DV0 D0 DV4
RDb WRb 1 DV6 0 0 0
1
1
1
1
1
1
The formula of the VLCD is shown below.
VLCD [V] = 0.5 x VREG + M (VREG - 0.5 x VREG) / 127
VBA = VEE x 0.9 VREG = VREF x N VBA VREF VREG N M : Output voltage of the reference voltage generator : Input voltage of the voltage regulator : Output voltage of the voltage regulator : Register value for the voltage booster : Register value for the EVR
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NJU6824
(32-21) Frequency control The "Frequency control" instruction is used to control the frame frequency for a LCD panel. CSb 0 RS 1 RDb WRb 1 0 RE2 1 RE1 0 RE0 0 D7 1 D6 1 D5 0 D4 1 D3 * D2 Rf2 D1 Rf1 D0 Rf0
# Rfx register (x=0, 1, 2) The "Rfx" register is used to determine the feed back resister value for the internal oscillator and it is possible to adjust the frame frequency for the LCD modules.
Rf 2 0 0 0 0 1 1 1 1 Rf 1 0 0 1 1 0 0 1 1 Rf 0 0 1 0 1 0 1 0 1 Feedback resistor value Reference value 0.8 x reference value 0.9 x reference value 1.1 x reference value 1.2 x reference value 0.7 x reference value 1.3 x reference value Inhibited
(32-22) Discharge ON/OFF Discharge circuit is used to discharge the electric charge of the capacitors on the V1 to V4 and the VLCD terminals. The "Discharge ON/OFF" instruction is usually required just after the internal power supply is turned off by setting "0" into the "DCON" and "AMPON" registers, or just after the external power supply is turned off. During the discharge operation, the internal or external power supply must not be turned on. CSb 0 RS 1 RDb WRb 1 0 RE2 1 RE1 0 RE0 0 D7 1 D6 1 D5 1 D4 0 D3 * D2 * D1 DIS2 D0 DIS
DIS=0: DIS=1: DIS2=0: DIS2=1:
Discharge OFF Discharge ON Discharge OFF Discharge ON
(Capacitors on the VLCD, V1, V2, V3 and V4) (Capacitors on the VLCD, V1, V2, V3 and V4) (Resistance between VOUT and VEE) (Resistance between VOUT and VEE)
Note ) VOUT and VEE are internally connected with the resistor (100k typical) in the power-ON.
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NJU6824
(32-23) Instruction register address The "Instruction register address" is used to specify the instruction register address, so that it is possible to read out the contents of the instruction registers in combination with the "Instruction register read" instruction. CSb 0 RS 1 RDb WRb 1 0 RE2 1 RE1 0 RE0 0 D7 1 D6 1 D5 0 D4 0 D3 RA3 D2 RA2 D1 RA1 D0 RA0
(32-24) Instruction register read The "Instruction register read" instruction is used to read out the contents of the instruction register in combination with the "Instruction register address" instruction.
CSb 0
RS 1
RDb WRb 0 1
RE2 0/1
RE1 0/1
RE0 0/1
D7 *
D6 *
D5 *
D4 *
D3
D2
D1
D0
Internal register data read
(32-25) Window end column address The "Window end column address" is used to specify the column address for the window end point. The lower 4-bit data is required to be programmed first and then the upper 4-bit data can be programmed. CSb 0 CSb 0 RS 1 RS 1 RDb WRb 1 0 RE2 1 RE2 1 RE1 0 RE1 0 RE0 1 RE0 1 D7 0 D7 0 D6 0 D6 0 D5 0 D5 0 D4 0 D4 1 D3 EX3 D3 EX7 D2 EX2 D2 EX6 D1 EX1 D1 EX5 D0 EX0 D0 EX4
RDb WRb 1 0
(32-26) Window end row address set The "Window end row address" is used to specify the row address for the window end point. The lower 4-bit data is required to be programmed first and then the upper 4-bit data can be programmed. CSb 0 CSb 0 RS 1 RS 1 RDb WRb 1 0 RE2 1 RE2 1 RE1 0 RE1 0 RE0 1 RE0 1 D7 0 D7 0 D6 0 D6 0 D5 1 D5 1 D4 0 D4 1 D3 EY3 D3 * D2 EY2 D2 EY6 D1 EY1 D1 EY5 D0 EY0 D0 EY4
RDb WRb 1 0
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NJU6824
(32-27) Initial reverse line The "Initial reverse line" instruction is used to specify the initial reverse line address for the reverse line display. Lower 4-bit data must be programmed first, next upper 3-bit data. It is programmed in between 00H and 7FH and the line address beyond 7FH is inhibited. The address relation: LSi < LEi (i=7 to 0) must be maintained in the reverse line display. CSb 0 CSb 0 RS 1 RS 1 RDb WRb 1 0 RE2 1 RE2 1 RE1 0 RE1 0 RE0 1 RE0 1 D7 0 D7 0 D6 1 D6 1 D5 0 D5 0 D4 0 D4 1 D3 LS3 D3 * D2 LS2 D2 LS6 D1 LS1 D1 LS5 D0 LS0 D0 LS4
RDb WRb 1 0
(32-28) Last reverse line The "Last reverse line" instruction is used to specify the last reverse line address for the reverse line display. Lower 4-bit must be programmed first, next upper 3-bit data. It is programmed in between 00H and 7FH and the line address beyond 7FH is inhibited. The address relation: LSi < LEi (i=7 to 0) must be maintained in the reverse line display. CSb 0 CSb 0 RS 1 RS 1 RDb WRb 1 0 RE2 1 RE2 1 RE1 0 RE1 0 RE0 1 RE0 1 D7 0 D7 0 D6 1 D6 1 D5 1 D5 1 D4 0 D4 1 D3 LE3 D3 * D2 LE2 D2 LE6 D1 LE1 D1 LE5 D0 LE0 D0 LE4
RDb WRb 1 0
(32-29) Reverse line display ON/OFF The "Reverse line display ON/OFF" is used to enable or disable the reverse line display for the blink operation and determine the reverse line display mode. CSb 0 RS 1 RDb WRb 1 0 RE2 1 RE1 0 RE0 1 D7 1 D6 0 D5 0 D4 0 D3 * D2 * D1 BT D0 LREV
# LREV register The "LREV" register is used to enable or disable the reverse line display.
LREV =0: LREV =1: Reverse line display OFF (Normal) Reverse line display ON
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NJU6824
# BT register The "BT" register is used to determine the reverse line display mode in the reverse line display ON (LREV=1) status.
BT =0: BT =1: Normal reverse line display Blink once every 32 frames Display examples in the LREV="1" and BT="1"
!"""! "!!!" "!!!! !"""! !!!!" "!!!" !"""! !!!!!
Blink once every 32 frames
"!!!" !"""! !"""" "!!!" """"! !"""! "!!!" """""
NJRC LCD DRIVER Low Power and Low Voltage
Blink once every 32 frames
NJRC LCD DRIVER Low Power and Low Voltage
Initial reverse line address Last reverse line address
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NJU6824
(32-30) Gradation palette setting control / Icon SEG address set CSb 0 RS 1 RDb WRb 1 0 RE2 1 RE1 0 RE0 1 D7 1 D6 0 D5 0 D4 1 D3 * D2 * D1 DMY D0 PS
# PS register PS=0: Lower 8 Gradation setting PS=1: Upper 8 Gradation setting # DMY register Although segment drivers in normal condition output LCD driving voltage corresponding to data in Display data RAM, Icon segment driver output LCD driving voltage corresponding to registers. The 24 bits register corresponds to SEGSA0 ~ SEGSA1, SEGSB0 ~ SEGSB1, SEGSC0 ~ SEGSC1.
DMY=0: DMY=1: Normal RAM access Icon segment driver RAM access
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NJU6824
(32-31) PWM control The "PWM control" is used to determine the PWM type for the segment waveforms, where the type can be specified for each of the SEGAi, SEGBi and SEGCi (i=0-127) drivers. CSb 0 RS 1 RDb WRb 1 0 RE2 1 RE1 0 RE0 1 D7 1 D6 0 D5 1 D4 0 D3 D2 D1 D0
PWMS PWMA PWMB PWMC
# PWMS register
PWMS=0: Type 1 PWMS=1: Type 2
# PWMA, B and C registers The "PWMA, PWMB and PWMC" registers are used to select the type 1-O or type 1-E.
PWMZ=0 (Z=A, B and C): Type 1-O PWMZ=1 (Z=A, B and C): Type 1-E
PWM type1 (PWMS="0")
"H" CL "L" VLCD Type-O SEG VLCD Type-E V2 Odd line Even line
V2
PWM type2 (PWMS="1")
CL "H" "L"
SEG
VLCD
V2
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NJU6824
(33) The relationship between Common drivers and row addresses Row address assignment of common drivers is programmed by the " SHIFT " register of the " Display control (1) " , " Duty cycle ratio ", " Internal display line " and " Initial COM line " instructions.
# When initial display line is "0" If the " SHIFT " is " 0 ", the scan direction is normal. When the " LA0 to LA6 " registers of the " Initial display line "instruction is " 0 ", the " MY " corresponding to the initial COM line is " 0 " and is increasing during display. # When initial display line is not "0" If the " SHIFT " is " 1 ", the scan direction is inversed. When the " LA0 to LA6 " registers of the " Initial display line "instruction is not " 0 ", the " MY " corresponding to the initial COM line is this setting value and is increasing during display.
The following are examples of setting the start-line 0 or 5 at 1/129, 1/128, or 1/17 duty.
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NJU6824
(33-1) Initial display line "0", 1/129 duty cycle (Common forward scan)
SC3
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 : COM103 COM104 : COM111 COM112 : COM125 COM126 COM127 (129th COM period) *1
SC2
SC1
SC0
0000
0
SHIFT="0"(Common forward scan), DS3, 2, 1, 0="0000", LA7....LA0="00000000"(Initial display line 0) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
124 120 112 104 96 88 80 72 64 56
1011
48
1100
40
1101
32
1110
24
1111
16
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0 127 0 127 0
127 127
123 127
119 127
111 127
103 127
95 127
87 127
79 127
71 127
63 127
55 127
47 127
39 127
31 127
23 127
15 127
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line *1 : 129th COM period is not selected.
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NJU6824
(33-2) Initial display line "0", 1/17 duty cycle (Common forward scan)
SC3
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 : COM95 COM96 : COM103 COM104 : COM111 COM112 : COM119 : COM127 (17th COM period) *1
SC2
SC1
SC0
0000
0
SHIFT="0"(Common forward scan), DS3, 2, 1, 0="1110", LA7....LA0="00000000"(Initial display line 0) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
1011
1100
1101
1110
1111
0
0
15 0
15
15 0
15 0
15 0
15 0
15 0
15 0
15 0
15 0
15 0 15 0 15 0 15 0 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line *1 : 17th COM period is not selected.
- 91 -
NJU6824
(33-3) Initial display line "0", 1/129 duty cycle (Common backward scan)
SC3
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 : COM15 COM16 : COM23 COM24 : COM31 COM32 : COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 (129th COM period) *1
SC2
SC1
SC0
0000
127
SHIFT="1"(Common backward scan), DS3, 2, 1, 0="0000", LA7....LA0="00000000"(Initial display line 0) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
123 119 111 103 95 87 79 71 63 55
1011
47
1100
39
1101
31
1110
23
1111
15
0 127 0 127 0 127 0 127
0 127
0 127
0 127
0 127
0 127
0 127
0 127
0 127
0 127
0 127
0 127
0 127
124 127
120 127
112 127
104 127
96 127
88 127
80 127
72 127
64 127
56 127
48 127
40 127
32 127
24 127
16 127
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line *1 : 129th COM period is not selected.
- 92 -
NJU6824
(33-4) Initial display line "5", 1/129 duty cycle (Common forward scan)
SC3
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 : COM80 COM81 COM82 COM83 : COM88 COM89 COM90 COM91 : COM96 COM97 COM98 COM99 : COM104 COM105 COM106 COM107 : COM112 : COM122 COM123 COM124: COM125 COM126 COM127 (129
th
SC2
SC1
SC0
0000
5
SHIFT="0"(Common forward scan), DS3, 2, 1, 0="0000", LA7....LA0="00000101"(Initial display line 5) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
1 125 126 127 0 117 109 101 93 85 77 69 61
1011
53
1100
45
1101
37
1110
29
1111
21
5
5 127 0
5 127 0
5 127 0
5 127 0
5 127 0
5 127 0
5 127 0
5 127 0
5 127 0 5 127 0 5 127 0 5 127 0 5 127 0 5 127 0
4 127
127 0 127
124 127
116 127
108 127
100 127
92 127
84 127
76 127
68 127
60 127
52 127
44 127
38 127
28 127
20 127
COM period) *1
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line *1 : 129th COM period is not selected.
- 93 -
NJU6824
(33-5) Initial display line "0", 1/128 duty cycle (Common forward scan, DSE="1")
SC3
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 : COM103 COM104 : COM111 COM112 : COM125 COM126 COM127
SC2
SC1
SC0
0000
0
SHIFT="0"(Common forward scan), DS3, 2, 1, 0="0000", LA7....LA0="00000000"(Initial display line 0) DSE="1" 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
124 120 112 104 96 88 80 72 64 56 48
1100
40
1101
32
1110
24
1111
16
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0
127 0 127 0 127 0
127
123
119
111
103
95
87
79
71
63
55
47
39
31
23
15
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 94 -
NJU6824
s ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Supply Voltage (4) Supply Voltage (5) Supply Voltage (6) Input Voltage Storage Temperature SYMBOL VDD VEE VOUT VREG VLCD V1, V2, V3, V4 VI Tstg CONDITION TERMINAL VDD VEE VOUT VREG VLCD V1, V2, V3, V4 *1 RATING -0.3 to +4.0 -0.3 to +4.0 -0.3 to +20.0 -0.3 to +20.0 -0.3 to +20.0 -0.3 to VLCD + 0.3 -0.3 to VDD + 0.3 -45 to +125 UNIT V V V V V V V C
VSS=0V Ta = +25C
Note 1) D0 to D15, CSb, RS, RDb, WRb, OSC1, RESb terminals.
!
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage SYMBOL VDD1 VDD2 VEE VLCD VOUT VREG VREF Topr TERMINAL VDD VEE VLCD VOUT VREG VREF MIN 1.7 2.4 2.4 5 TYP MAX 3.3 3.3 3.3 18.0 18.0 VOUT x 0.9 3.3 85 UNIT V V V V V V V C NOTE *1 *2 *3 *4
Operating Voltage Operating Temperature
2.1 -30
*5
Note1) Note2) Note3) Note4)
Applies to the condition when the reference voltage generator is not used. Applies to the condition when the reference voltage generator is used. Applies to the condition when the voltage booster is used. The following relationship among the supply voltages must be maintained. VSS- 95 -
NJU6824
s DC CHARACTERISTICS 1
VSS = 0V, VDD = +1.7 to +3.3V, Ta = -30 to +85C PARAMETER High level input voltage Low level input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage Input leakage current Output leakage current Driver ON-resistance Stand-by current Internal oscillation Frequency External oscillation Frequency Voltage converter output voltage Supply current (1) Supply current (2) Supply current (3) Supply current (4) Supply current (5) Supply current (6) VBA Operating voltage VREG Operating voltage
SYM BOL VIH VIL VOH1 VOL1 VOH2 VOL2 ILI ILO RON1 ISTB fOSC1 fOSC2 fOSC3 fr1 fr2 fr3 VOUT IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 VBA VREG V2 V3 VD12 VD34 VD24
CONDITION
MIN 0.8 VDD 0 VDD - 0.4 VDD - 0.4 -10 -10
TYP
MAX VDD 0.2VDD 0.4 0.4 10 10 2 4 15 710 160 22.9
UNIT NOTE V V V V V V A A k A kHz *1 *1 *2 *2 *3 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12
IOH = -0.4mA IOL = 0.4mA IOH = -0.1mA IOL = 0.1mA VI = VSS or VDD VI = VSS or VDD |VON| = 0.5V CS=VDD, Ta=25C VDD = 3V Ta = 25C Rf=15k Rf=68k Rf=510k N-time booster (N=2 to 6) RL = 500k (VOUT - VSS) VDD = 3V, 6-time booster Whole ON pattern VDD = 3V, 6-time booster Checker pattern VDD = 3V, 5-time booster Whole ON pattern VDD = 3V, 5-time booster Checker pattern VDD = 3V, 4-time booster Whole ON pattern VDD = 3V, 4-time booster Checker pattern VEE = 2.4 to 3.3V VEE = 2.4 to 3.3V VREF = 0.9 x VEE N-time booster (N=2 to 6)
VLCD = 10V VLCD = 6V VDD = 3V
1 2 490 110 15.9 600 135.5 19.4 575 135 19.6
kHz V
(N x VEE) x 0.95 760 930 520 650 360 450 (0.9 VEE) x 0.98
(VREF x N)
1140 1400 780 980 540 680 (0.9 VEE) x 1.02
(VREF x N)
A
*13
0.9 VEE
(VREF x N)
V V
*14 *15
x 0.97 -100 -100 -30 -30 -30
x 1.03 +100 +100 +30 +30 +30
Output Voltage
0 0 0 0 0
mV
*16
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NJU6824
s CLOCK and FRAME FREQUENCY
Display duty cycle ratio (1/D)
1/129 to 1/81 1/73 to 1/41 1/33 to 1/25 1/17
PARAMETER SYMBOL
Display mode 16 Gradation mode
NOTE
fOSC / (62xD) fOSC / (14xD) fOSC / (2xD) fCK / (62xD) fCK / (14xD) fCK / (2xD)
fOSC / (62xDx2) fOSC / (14xDx2) fOSC / (2xDx2) fCK / (62xDx2) fCK / (14xDx2) fCK / (2xDx2)
fOSC / (62xDx4) fOSC / (14xDx4) fOSC / (2xDx4) fCK / (62xDx4) fCK / (14xDx4) fCK / (2xDx4)
fOSC / (62xDx8) fOSC / (14xDx8) fOSC / (2xDx8) FLM fCK / (62xDx8) fCK / (14xDx8) fCK / (2xDx8)
Internal clock
fOSC
Simplified 8 gradation mode B&W mode 16 Gradation mode
External clock
fCK
Simplified 8 gradation mode B&W mode
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NJU6824
APPLIED TERMINALS and CONDITIONS
Note 1) Note 2) Note 3) Note 4) Note 5) D0-D15, CSb, RS, RDb, WRb, P/S, SEL68, RESb D0-D15 CL, FLM, FR, CLK CSb, RS, SEL68, RDb, WRb, P/S, RESb, OSC1 D0-D15 in the high impedance
Note 6) - SEGA0-SEGA127, SEGB0-SEGB127, SEGC0-SEGC127, COM0-COM127 and SEGSA0-SEGSA1, SEGSB0-SEGSB1, SEGSC0-SEGSC1 - Defines the resistance between the COM/SEG terminals and the power supply terminals (VLCD, V1, V2, V3 and V4) at the condition of 0.5V deference and 1/9 LCD bias ratio. Note 7) VDD - The oscillator is halted, CSb="1" (disabled), No-load on the COM/SEG drivers Note 8) OSC - Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the variable gradation mode. Note 9) OSC - Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the fixed gradation mode. Note 10) OSC - Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the Black & White mode. Note 11) VDD=3V, Ta=25C Note 12) VOUT - Applies to the condition when the internal voltage booster, the internal oscillator and the internal power circuits are used. - VEE=2.4V to 3.3V, EVR= (1,1,1,1,1,1,1), 1/5 to 1/12 LCD bias, 1/129 duty cycle, No-load on COM/SEG drivers. - RL=500K between the VOUT and the VSS, CA1=CA2=1.0uF, CA3=0.1uF, DCON="1", AMPON="1" Note 13) VDD - Applies to the condition using the internal oscillator and internal power circuits, no access between the LSI and MPU. - EVR= (1,1,1,1,1,1,1), All pixels turned-on or checkerboard display in gradation mode. No-load on the COM/SEG drivers. - VDD=VEE, VREF=0.9VEE, CA1=CA2=1.0uF, CA3=0.1uF, DCON="1", AMPON="1", NLIN="0", 1/129 Duty cycle, Ta=25C Note 14) VBA - Applies to the condition that VBA=VREF and voltage booster N= 1. DCON="0", VOUT=13.5V input. Note 15) VREG - VEE=2.4V to 3.3V, VREF=0.9VEE, VOUT=18V, 1/5 to 1/12 LCD bias ratio, 1/129 duty cycle, EVR=(1,1,1,1,1,1,1) - Checkerboard display, No-load on the COM/SEG drivers, the voltage booster N=2 to 6, V1A1, V1A2, V4A1, V4A2 = "0". CA1=CA2=1.0uF, CA3=0.1uF, DCON="0", AMPON="1", NLIN="0" Note 16) VLCD, V1, V2, V3, V4 - VEE=3.0V, VREF=0.9VEE, VOUT=15V, 1/5 to 1/12 LCD Bias, EVR= (1,1,1,1,1,1,1), Display OFF, Noload on the COM/SEG drivers, voltage booster N=5, V1A1, V1A2, V4A1, V4A2 = "0". CA1=CA2=1.0uF, CA3=0.1uF, DCON="0", AMPON="1" (1) (2) (3) (4) VLCD V1 V2 V3 V4 VSS
VD12: (1)-(2) VD34: (3)-(4) VD24: (2)-(4)
- 98 -
NJU6824
s AC CHARACTERISTICS
#
Write operation (80-type MPU) tAS8 CSb RS
tAH8
WRb
tWRLW8
tWRHW8 tDS8 tDH8
D0 to D15 tCYC8 (VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSb ns RS ns ns ns ns ns WRb D0 to D15
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time
SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8
CONDITION
MIN. 0 0 90 35 35 30 5
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time
SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8
CONDITION
MIN. 0 0 160 70 70 40 5
(VDD=2.2 to 2.5V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSb ns RS ns ns ns ns ns WRb D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 CONDITION MIN. 0 0 180 80 80 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSb RS WRb D0 to D15
Data setup time tDS8 70 Data hold time tDH8 10 Note) Each timing is specified based on 20% and 80% of VDD.
- 99 -
NJU6824
# Read operation (80-type MPU)
tAS8 CSb RS tAH8
RDb
tWRLR8
tWRHR8 tRDH8
D0 to D15 tRDD8 tCYC8 (VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSb ns RS ns ns ns 60 ns ns RDb
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 TRDD8 TRDH8
CONDITION
MIN. 0 0 180 80 80
CL=15pF
0
D0 to D15
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 TRDD8 TRDH8
CONDITION
MIN. 0 0 180 80 80
(VDD=2.2 to 2.5V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSb ns RS ns ns ns 60 ns ns RDb
CL=15pF
0
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 CONDITION MIN. 0 0 250 120 120 110 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSb RS RDb
Read Data delay time tRDD8 CL=15pF Read Data hold time tRDH8 0 Note) Each timing is specified based on 20% and 80% of VDD.
D0 to D15
- 100 -
NJU6824
# Write operation (68-type MPU)
tAS6 CSb RS R/W (WRb) tAH6
E (RDb)
tEHW6 tDS6 tDH6
tELW6
D0 to D15 tCYC6 (VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSb ns RS ns ns ns ns ns E
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width
SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6 SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6 SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6
CONDITION
MIN. 0 0 90 35 35 40 5
D0 to D15
CONDITION
MIN. 0 0 160 70 70 50 5
(VDD=2.2 to 2.5V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns CSb ns RS ns ns ns ns ns MAX. UNIT ns ns ns ns ns ns ns E
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85C) CONDITION MIN. 0 0 180 80 80 TERMINAL CSb RS E
Data setup time tDS6 70 Data hold time tDH6 10 Note) Each timing is specified based on 20% and 80% of VDD.
D0 to D15
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NJU6824
# Read operation (68-type MPU) tAS6
CSb RS tAH6
R/W (WRb) tELR6 E (RDb) tRDH6 tEHR6
D0 to D15 tRDD6 tCYC6 (VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns 70 ns ns CSb RS E
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6 SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6 SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6
CONDITION
MIN. 0 0 180 80 80
CL=15pF
0
D0 to D15
CONDITION
MIN. 0 0 180 80 80
(VDD=2.2 to 2.5V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns 70 ns ns CSb RS E
CL=15pF
0
D0 to D15
CONDITION
MIN. 0 0 250 120 120
(VDD=1.7 to 2.2V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns 110 ns ns CSb RS E
CL=15pF
0
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD.
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NJU6824
# Serial interface
CSb tCSS tCSH
RS tASS SCL tSHW tCYCS tSLW tAHS
tDSS
tDHS
SDA
PARAMETER Serial clock cycle SCL "H" level pulse width SCL "L" level pulse width Address setup time Address hold time Data setup time Data hold time CSb - SCL time CSb hold time PARAMETER Serial clock cycle SCL "H" level pulse width SCL "L" level pulse width Address setup time Address hold time Data setup time Data hold time CSb - SCL time CSb hold time
SYMBOL CONDITION tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH SYMBOL CONDITION tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH
MIN. 100 45 45 20 20 20 20 20 20
(VDD=2.5 to 3.3V, Ta=-30 to +85C) UNIT MAX. TERMINAL ns ns SCL ns ns RS ns ns SDA ns ns CSb ns (VDD=2.2 to 2.5V, Ta=-30 to +85C) UNIT MAX. TERMINAL ns ns SCL ns ns RS ns ns SDA ns ns CSb ns (VDD=1.7 to 2.2V, Ta=-30 to +85C) UNIT MAX. TERMINAL ns ns SCL ns ns RS ns ns SDA ns ns CSb ns
MIN. 100 45 45 20 20 20 20 20 20
PARAMETER SYMBOL CONDITION MIN. 160 Serial clock cycle tCYCS 75 SCL "H" level pulse width tSHW 75 tSLW SCL "L" level pulse width 35 Address setup time tASS 35 Address hold time tAHS 35 Data setup time tDSS 35 Data hold time tDHS 35 CSb - SCL time tCSS 35 tCSH CSb hold time Note) Each timing is specified based on 20% and 80% of VDD.
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NJU6824
# Display control timing
CLK
tDCL
CL tDFLM tDFLM FLM tFR FR
Output timing PARAMETER FLM delay time FR delay time CL delay time
SYMBOL CONDITION tDFLM CL=15pF tFR tDCL
MIN. 0 0 0
(VDD=2.4 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL 500 ns FLM 500 ns FR 200 ns CL
Output timing PARAMETER SYMBOL CONDITION MIN. FLM delay time tDFLM CL=15pF 0 FR delay time tFR 0 CL delay time tDCL 0 Note) Each timing is specified based on 20% and 80% of VDD.
(VDD=1.7 to 2.4V, Ta=-30 to +85C) MAX. UNIT TERMINAL 1000 ns FLM 1000 ns FR 200 ns CL
- 104 -
NJU6824
# Input clock timing
tCKLW OSC1 tCKHW
PARAMETER OSC1 "H" level pulse width (1) OSC1 "L" level pulse width (1) OSC1 "H" level pulse width (2) OSC1 "L" level pulse width (2) OSC1 "H" level pulse width (3) OSC1 "L" level pulse width (3)
SYMBOL tCKHW1 tCKLW1 tCKHW2 tCKLW2 tCKHW3 tCKLW3
CONDITION
MIN. 0.70 0.70 3.13 3.13 21.8 21.8
(VDD=1.7 to 3.3V, Ta=-30 to +85C) UNIT MAX. TERMINAL OSC1 1.02 s 1 1.02 s OSC1 4.55 s 2 4.55 s OSC1 31.4 s 3 31.4 s
Note) Each timing is specified based on 20% and 80% of VDD. Note 1) Applied to the variable gradation mode / MON="0",PWM="0" Note 2) Applied to the fixed gradation mode / MON="0",PWM="1" Note 3) Applied to the B&W mode / MON="1"
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NJU6824
#
Reset input timing
tRW RESb tR Internal circuit status
During reset
End of reset
PARAMETER Reset time RESb "L" level pulse width
SYMBOL CONDITION tR tRW
MIN.
(VDD=2.4 to 3.3V, Ta=-30 to +85C) UNIT MAX. Terminal 1.0
s s
RESb
10.0
PARAMETER Reset time RESb "L" level pulse width
SYMBOL CONDITION tR tRW
MIN.
(VDD=1.7 to 2.4V, Ta=-30 to +85C) UNIT MAX. Terminal 1.5
s s
RESb
10.0
Note) Each timing is specified based on 20% and 80% of VDD.
- 106 -
NJU6824
#
Typical characteristic PARAMETER Basic delay time of gate SYMBOL Ta=+25C, VSS=0V, VDD=3.0V MIN TYP 10 MAX UNIT ns
#
Input output terminal type (a) Input circuit VDD I VSS(0V) Terminals: CSb, RS, RDb, WRb, SEL68, P/S, RESb
Input signal
(b) Output circuit VDD Terminals: FLM, CL, FR, CLK
O VSS(0V)
Output control signal Output signal
(c) Input/Output circuit VDD I/O VSS(0V) VSS(0V) Input control signal VDD Output control signal Output signal VSS(0V) Terminals: D0 to D15
Input signal
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NJU6824
(d) Display output circuit VLCD Output control signal 1 O Output control signal 3 VSS(0V) V3/V4 VSS(0V) Output control signal 4 VSS(0V) VLCD VLCD V1/V2 Output control signal 2
Terminals:
SEGA0 to SEGA127 SEGB0 to SEGB127 SEGC0 to SEGC127 COM0 to COM127 SEGSA0 to SEGSA1 SEGSB0 to SEGSB1 SEGSC0 to SEGSC1
- 108 -
NJU6824
s APPLICATION CIRCUIT EXAMPLES
(1) MPU Connections
80-type MPU interface
1.7V to 3.3V
VCC
A0 Decoder 8
RS CSb
VDD
A1 to A7 7 (80-type MPU) IORQ D0 to D7 RD WR GND RES
D0 to D7 RDb WRb RESb V SS
RESET
68-type MPU interface
1.7V to 3.3V
VCC
A0 15 Decoder 8
RS CSb
VDD
A1 to A15 (68-type MPU) VMA D0 to D7 E R/W GND RES
D0 to D7 RDb(E) WRb(R/W) RESb VSS
RESET
Serial interface
1.7V to 3.3V
VCC (MPU)
A0 A1 to A7 7 Decoder
RS CSb
VDD
PORT1 PORT2 GND RES RESET
SDA SCL RESb VSS
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NJU6824
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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