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| OKI Semiconductor MSM51V16400F 4,194,304-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE FEDD51V16400F-01 Issue Date: Sep. 29, 2003 DESCRIPTION The MSM51V16400F is a 4,194,304-word x 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM51V16160F achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM51V16400F is available in a 26/24-pin plastic TSOP. FEATURES * 4,194,304-word x 4-bit configuration * Single 3.3V power supply, 0.3V tolerance * Input : LVTTL compatible, low input capacitance * Output : LVTTL compatible, 3-state * Refresh : 4096 cycles/64ms * Fast page mode, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * Packages 26/24-pin 300mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM51V16400F-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Access Time (Max.) Family tRAC 50ns 60ns 70ns tAA 25ns 30ns 35ns tCAC 13ns 15ns 20ns tOEA 13ns 15ns 20ns Cycle Time (Min.) 90ns 110ns 130ns Power Dissipation Operating (Max.) 270mW 252mW 234mW Standby (Max.) 1.8mW MSM51V16400F 1/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F PIN CONFIGURATION (TOP VIEW) VCC 1 DQ1 2 DQ2 3 WE 4 RAS 5 A11R 6 A10R 8 A0 9 A1 10 A2 11 A3 12 VCC 13 26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE 21 A9 19 A8 18 A7 17 A6 16 A5 15 A4 14 VSS 26/24-Pin Plastic TSOP (K Type) Pin Name A0-A9, A10R,A11R RAS CAS DQ1-DQ4 OE WE VCC VSS NC Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (3.3V) Ground (0V) No Connection Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F BLOCK DIAGRAM RAS CAS Timing Generator Timing Generator 10 Column Address Buffers Internal Address Counter 10 Column Decoders Write Clock Generator WE OE 4 Output Buffers 4 4 4 Input Buffers 4 A0 - A9 Refresh Control Clock Sense Amplifiers 4 I/O Selector 4 DQ1 - DQ4 10 A10R , A11R 2 Row Address Buffers 12 Row Decoders Word Drivers Memory Cells VCC On Chip VBB Generator VSS 3/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Voltage on Any Pin Relative to VSS Voltage VCC Supply relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD* Topr Tstg Value -0.5 to VCC+ 0.5 -0.5 to 4.6 50 1 0 to 70 -55 to 150 Unit V V mA W C C *: Ta = 25C RECOMMENDED OPERATIING CONDITIONS (Ta = 0 to 70C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 3.0 0 2.0 - 0.3*2 Typ. 3.3 0 Max. 3.6 0 VCC + 0.3 0.8 *1 Unit V V V V Notes: *1. The input voltage is VCC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 1.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied). PIN CAPACITANCE (Vcc = 3.3V 0.3V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (A0 - A9, A10R, A11R) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ4) Symbol CIN1 CIN2 CI/O Min. -- -- -- Max. 5 7 7 Unit pF pF pF 4/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F DC CHARACTERISTICS (VCC = 3.3V 0.3V, Ta = 0 to 70C) MSM51V16400 MSM51V16400 MSM51V16400 F-50 F-60 F-70 Unit Note Min. Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) VOH VOL IOH = -2.0mA IOL = 2.0mA 0V VI VCC + 0.3V; ILI All other pins not under test = 0V DQ disable 0V VO VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC - 0.2V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. 70 65 60 mA 1,3 5 5 5 mA 1 75 70 65 mA 1,2 - 10 10 - 10 10 - 10 10 A 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 V V Parameter Symbol Condition ILO - 10 10 - 10 10 - 10 10 A ICC1 75 70 65 mA 1,2 2 0.5 2 0.5 2 mA 0.5 1 ICC6 75 70 65 mA 1,2 Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 5/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F AC CHARACTERISTICS (1/2) (VCC = 3.3V 0.3V, Ta = 0 to 70C) Note1,2,3 Parameter Symbol MSM51V16400 F-50 Min. Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time tRC tRWC tPC 90 131 35 76 0 0 0 1 30 50 50 13 13 7 13 50 5 30 17 12 0 Max. 50 13 25 30 13 13 13 50 64 10,000 100,000 10,000 37 25 MSM51V16400 F-60 Min. 110 155 40 85 0 0 0 1 40 60 60 15 15 10 15 60 5 35 20 15 0 Max. 60 15 30 35 15 15 15 50 64 10,000 100,000 10,000 45 30 MSM51V16400 F-70 Min. 130 185 45 100 0 0 0 1 50 70 70 20 20 10 20 70 5 40 20 15 0 Max. 70 20 35 40 20 20 20 50 64 10,000 100,000 10,000 50 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns 12 12 5 6 14 4, 5, 6 4, 5 4, 6 4, 12 4 4 7 7 3 Unit Note Fast Page Mode Read Modify Write tPRWC Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS CAS to Data Output Buffer Turnoff Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tRP tRAS RAS Pulse Width (Fast Page Mode) tRASP RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time tRSH tROH tCP tCAS tCSH tCRP RAS Hold Time from CAS Precharge tRHCP RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time tRCD tRAD tASR 6/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F AC CHARACTERISTICS (2/2) (VCC = 3.3V 0.3V, Ta = 0 to 70C) Note1,2,3 Parameter Symbol MSM51V16400 F-50 Min. Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tOEH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH 7 0 7 25 0 0 0 0 7 7 13 13 13 0 7 13 36 48 73 53 5 5 10 10 10 10 10 Max. MSM51V16400 F-60 Min. 10 0 10 30 0 0 0 0 10 10 15 15 15 0 10 15 40 55 85 60 5 5 10 10 10 10 10 Max. MSM51V16400 F-70 Min. 10 0 15 35 0 0 0 0 15 10 20 20 20 0 15 20 50 65 100 70 5 5 10 10 10 10 10 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 11 11 12 13 10, 11 10, 11 11 8, 11 8 9, 11 11 11 11 Unit Note 7/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. -50 is measured with a load circuit equivalent to 1 TTL load and 50pF, and -60/-70 is measured with a load circuit equivalent to 1 TTL load and 100pF. The output timing reference levels are VOH=2.0 and VOL=0.8V. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.), tRWD tRWD(Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test CA8 and CA9 are not used and each DQ pin now access 4-bit locations. Since all 4 DQ pins are used, a total 16 data bits can be written in parallel into the memory array. In a read cycle, if 4 data bits are equal, the DQ pin will indicate a high level. If the 4 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameter is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F TIMING CHART Read Cycle RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL VIH VIL VIH VIL tRAC DQ VOH VOL tCLZ Open Valid Data-out "H" or "L" tCAC tOEZ tOFF tAA tROH tOEA OE tRCH tRAD tRAL tRAH tASC Column tRCS tRRH tCAH tRCD tRP tCSH tRSH tCAS tCRP tRC tRAS Row WE Write Cycle (Early Write) VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL tRAD tRAL tRAH tASC tCAH Column tCWL tWCS tWP WE VIH VIL VIH VIL VIH VIL tDS tDH Open "H" or "L" tRWL tWCH tRCD tRC tRAS tRP tCSH tRSH tCAS tCRP RAS Row OE DQ Valid Data-in 9/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F Read Modify Write Cycle tRWC tRAS RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL tRAD tRAH tASC Colum tRCS tRWD WE VIH VIL VIH VIL tRAC DQ VI/OH VI/OL tCLZ Valid Data-out tRP tCSH tRCD tRSH tCAS tCWL tRWL tCRP tCAH Row tCWD tWP tAWD tAA tOEA tOED tCAC tOEZ tDS Valid Data-in tOEH OE tDH "H" or "L" 10/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F Fast Page Mode Read Cycle tRASP RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL VIH VIL VIH VIL tRAC tCAC DQ VOH VOL tCLZ tCPA tOFF tOEZ Valid Data-out tRP tPC tRHCP tCP tCAS tRSH tCAS tRAL tRCD tCAS tRAD tCSH tRAH tASC tCA tCP tCRP tASC tCAH tASC Column tRCH tAA tRCS tCAH Row tRCS Column tRCH tAA tOEA Column tRCS tAA tOEA tRCH WE tOEA tCPA tOFF tOEZ Valid Data-out tRRH OE tCAC tCLZ tCAC tOEZ tCLZ Valid Data-out tOFF "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP RAS VIH VIL VIH VIL tASR Address VIH VIL Row tRAD tRAH tASC tCSH tCAH tASC tCAH tASC tRAL tCAH Column tRWL tCWL tWCS WE VIH VIL tDS VIH DQ VIL Valid * Data-in tCWL tRP tPC tRHPC tCP tCAS tRSH tCAS tCRP tCRP tRCD tCAS tCP CAS Column Column tCWL tWCS tWCH tWP tWCS tWCH tWP tWP tWCH tDH tDS Valid * Data-in tDH tDS Valid * Data-in tDH Note: OE = "H" or "L" "H" or "L" 11/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F Fast Page Mode Read Modify Write Cycle tRASP tCSH RAS VIH VIL VIH VIL tRAH tASR VIH Address VIL Row tPRWC tCAS tCP tCAS tCAH tCP tRSH tCAS tCAH tASC tCR tRP tRCD tRAD tASC Column CAS tCAH tCWL tASC tCWL Column tRAL Column tRCS WE VIH VIL tRAC tAA tRWD tCWD tAWD tWP tDH tOEA tDS tOED tCAC tOEZ Out tRCS tCPWD tRC tCPWD tCWL tRWL tCWD tAWD tCPA tAA tOEA tOED tOEZ tCAC In tCLZ Out tDS tCAC In tCLZ tWP tDH tAA tCWD tAWD tWP tROH tCPA tOEA tOED tOEZ tDH tDS OE VIH VIL VI/OH DQ VI/OL tCLZ Out In Note: In = Valid Data-in, Out = Valid Data-out "H" or "L" RAS-only Refresh Cycle tRC tRAS RAS VIH VIL tCRP CAS VIH VIL VIH VIL VOH VOL tASR tRAH tRPC tRP Address Row tOFF Open Note: WE, OE = "H" or "L" "H" or "L" DQ 12/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F CAS before RAS Refresh Cycle tRP RAS VIH VIL VIH VIL VIH VIL tOFF DQ VOH VOL Open Note: OE, Address = "H" or "L" "H" or "L" tWRP tWRH tWRP tRPC tCP tCSR tCHR CAS tRAS tRP tRPC tRC WE Hidden Refresh Read Cycle tRC tRAS RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL tRAD tRAH Row tRCS WE tASC Column tCAC tRAL tAA tROH OE VIH VIL VOH VOL tRAC tCLZ Open Valid Data-out "H" or "L" tOEA tOEZ tWRP tWRH tOFF tRRH tCAH tCRP tRCD tRSH tRP tCHR CAS tRP tRAS tRC DQ 13/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F Hidden Refresh Write Cycle tRC tRAS RAS VIH VIL VIH VIL tASR Address VIH VIL tRAD tRAH Row tASC tCAH Column tRAL tRWL tWP WE VIH VIL tWCS OE VIH VIL VIH VIL "H" or "L" tDS tDH Valid Data-in tWCH tWRP tWRH tCRP tRCD tRSH tRP tCHR CAS tRP tRAS tRC DQ 14/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F REVISION HISTORY Document No. FEDD51V16400F-01 Date Sep. 29, 2003 Page Previous Current Edition Edition - - Final edition 1 Description 15/16 FEDD51V16400F-01 1 Semiconductor MSM51V16400F NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2003 Oki Electric Industry Co., Ltd. 16/16 |
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