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FEDL9222-02 Semiconductor
FEDL9222-02 This version: Feb. 2000 ML9222 Previous version: Nov. 1999
Semiconductor ML9222
GENERAL DESCRIPTION
32-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, ADC and Keyscan
The ML9222 is a full CMOS controller/driver for Duplex or Triplex vacuum fluorescent display tube. It conststs of 32-segment driver outputs and 3-grid pre-driver outputs, so that it can drive directly up to 96-segment VFD. ML9222 features a digital dimming function, a 8-ch ADC, a 5 5 keyscan circuit and an encoder type switch interface. ML9222 provides an interface with a microcontroller only by four signal lines: DATA I/O, CLOCK, CS and INT.
FEATURES
* Supply voltage (VDD) * Duplex/Triplex selectable * Applicable VFD tube : 8 to 18.5V (Built-in 5V regulator for logic)
: 2 Grids 32 Anodes VFD tube : 3 Grids 32 Anodes VFD tube * 32-segment driver outputs : IOH=-5mA at VOH=VDD-0.8V (SEG1 to 22) IOH=-10mA at VOH=VDD-0.8V (SEG23 to 32) * 3-grid pre-driver outputs : IOL=10mA at VOL=2V * Built-in digital dimming circuit (10-bit resolution) * Built-in 8-ch A/D converter * Built-in 5 5 keyscan circuit * 3 interface circuits for an encoder type rotary switch * Built-in oscillation circuit (external R and C) * Built-in Power-On-Reset circuit * Package: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) Product name: ML9222GA
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FEDL9222-02 Semiconductor ML9222
BLOCK DIAGRAM
SEG1
SEG32
GRID1 GRID2 GRID3
D-GND VDD VCC (5V) VREG (5V) L-GND 5V Regulator & Power On Reset
0H 7H
32 Segment Driver
3 Grid pre Driver
POR in1-32
Out1-32 96 to 32 Segment Control in1-32
in1-32
1H
Mode Select
POR
0H POR
in1-3
Out1-32 Segment Latch 1 in1-32
2H 0H POR
Out1-32 Segment Latch 2 in1-32
3H 0H POR
Out1-32 Segment Latch 3 in1-32
CS CLOCK DATA I/O Control
Out1-3 3bit Shift Register
Out1-32 32bit Shift Register
4H POR
in1-10 Dimming Latch Out1-10
POR
POR
OSCO
OSC
POR
10bit Digital Dimming
DIM OUT SYNC OUT1 DUP/TRI Timing Generator SYNC OUT2
8ch, 8bit A/D Converter
7H
5H 6H
5 5 Key Scan and Encoder Switch Interface
INT
CH1
CH8
COL1
COL5
ROW1
ROW5
A1 B1 A2 B2 A3 B3
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FEDL9222-02 Semiconductor ML9222
PIN CONFIGURATION (TOP VIEW)
80 SEG27
78 SEG25
76 SEG24
75 SEG23
74 SEG22
73 SEG21
71 SEG20
70 SEG19
69 SEG18
67 SEG17
66 SEG16
65 SEG15
79 SEG26
77 NC
72 NC
68 NC
VDD SEG28 SEG29 SEG30 SEG31 SEG32 GRID1 GRID2 GRID3 D-GND ROW1 ROW2 ROW3 ROW4 ROW5 COL1 COL2 COL3 COL4 COL5 A3 B3 A2 B2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
64 VDD 63 SEG14 62 SEG13 61 SEG12 60 SEG11 59 SEG10 58 SEG9 57 SEG8 56 SEG7 55 SEG6 54 SEG5 53 SEG4 52 SEG3 51 SEG2 50 SEG1 49 CH8 48 CH7 47 CH6 46 CH5 45 CH4 44 CH3 43 CH2 42 CH1 41 Vreg
A1 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
B1 INT NC DUP/TRI VCC OSC0 NC L-GND DATA I/O CLOCK CS NC SYNC OUT2 SYNC OUT1 DIM OUT
NC: No connection 80-pin Plastic QFP
40
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FEDL9222-02 Semiconductor ML9222
PIN DESCRIPTIONS
Pin 1, 64 10 33 30 41 50 to 63, 65 to 67, 69 to 71, 73, 74 75, 76, 78 to 80, 2 to 6 7, 8, 9 GRID1 to 3 O SEG23 to 32 O Symbol VDD D-GND L-GND VCC VREG SEG1 to 22 Type -- -- -- O O O Power supply pins. Pin1 and pin64 should be connected externally. D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the logic circuit. Pins 8 and 26 should be connected externally. 5V output pin for internal logic portion and external logic circuit. Reference voltage (5V) output pin for A/D converter. Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. IOH-5 mA Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. IOH-10 mA Inverted Grid signal output pins. For pre-driver, the external circuit is requiend. IOL10 mA 36 35 34 CS CLOCK DATA I/O I I I/O Chip Select input pin. Data input/output operation is valid when this pin is set at a High level. Serial clock input pin.
Data is input and/or output through the DATA I/O pin at the rising edge of the serial clock.
Description
Serial data input/output pin. Data is input to / comes out from the shift register at the rising edge of the serial clock. Interrupt signal output to microcontroller. When any key of key matrix is pressed or released, key scanning is started. After the completion of the one cycle, this pin goes to high level and keeps the high level until keyscan stop mode is selected. Duplex/Triplex operation select input pin.
27
INT
O
29 42 to 49 21 to 26
DUP/TRI CH1 to 8 A1 to A3 B1 to B3
I I I
Duplex (1/2 duty) operation is selected when this pin is set at a VCC level. Triplex (1/3 duty) operation is selected when this pin is set at a GND level. Analog voltage input pin for the 8-bit A/D converter. Input pin for the encoder type rotary switch. Each input has chattering absorption function of 620ns typical. Return inputs from the key matrix. These pins are active low. When key matrix are in the inactive sate, these pins are at high level through the internal pull-up resistors. All the inputs do not have the cahttering absorption function for the keyscans. Key switch scanning outputs. Normally low level is output through these pin. When any switch of key matrix
16 to 20
COL1 to 5
I
11 to 15
ROW1 to 5
O
is depressed or released, key scanning is started and is continued until keyscan stop mode is selected. When keyscan stop mode is selected, all outputs of ROW1 to 5 go back to low level.
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FEDL9222-02 Semiconductor ML9222
Pin 40
Symbol DIM OUT
Type O Dimming pulse output.
Description Connect this pin to the slave side DIM IN pin. Synchronous signal input. Connect these pins to the SYNC IN1 and SYNC IN2 pins of a slave side. RC oscillator connecting pins. Connect a resistor (R2) between the VCC and OSC0 pins, VCC R2 C3 C2
38, 39
SYNC OUT 1, 2
O
31
OSC0
I/O
and a capacitor (C2) between the OSC0 pin and the GND, OSC0
and a capacitor (C3) between the VCC and the GND. C3 is for VCC stabilization.
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FEDL9222-02 Semiconductor ML9222
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDD VIN PD TSTG IO1 Output Current IO2 IO3 IO4 Condition -- -- Ta = 85C -- SEG1 to 22 SEG23 to 32 GRID1 to 3 DIM OUT, SYNC OUT1, SYNC OUT2 Rating -0.3 to +20 -0.3 to +6.0 764 -55 to +150 -10.0 to +2.0 -20.0 to +2.0 -7.0 to +20.0 -2.0 to +2.0 Unit V V mW C mA mA mA mA
RECOMMENDED OPERATING CONDITIONS
Parameter Driver Supply Voltage High Level Input Voltage Low Level Input Voltage Clock Frequency Oscillation Frequency Frame Frequency Operating Temperature Symbol VDD VIH VIL fC fOSC fFR TOP Condition -- All inputs except OSC0 All inputs except OSC0 -- R2 = 10kW5%, C2 = 27pF5% R2 = 10kW5% C2 = 27pF5% -- 1/3 Duty 1/2 Duty Min. 8.0 3.8 0.0 -- 2.6 211 317 -40 Typ. 13.0 -- -- -- 3.3 269 403 -- Max. 18.5 5.5 0.8 1.0 4.0 325 488 +85 Unit V V V MHz MHz Hz Hz C
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FEDL9222-02 Semiconductor ML9222
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta=-40 to +85C, VDD=8.0 to 18.5V) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol Applied pin VIH VIL IIH1 IIH2 IIL1 IIL2 VOH1 VOH2 High Level Output Voltage VOH3 VOH4 VOL1 Low Level Output Voltage VOL2 VOL3 VOL4 Supply Current Supply Voltage for Logic IDD VL *1) *1) *2) *3) *2) *3) SEG1 to 22 SEG23 to 32 GRID1 to 3 *4) SEG1 to 22 SEG23 to 32 GRID1 to 3 *5) VDD VCC VDD=9.5V VDD=9.5V Condition -- -- VIH=3.8V VIH=3.8V VIL=0.0V VIL=0.0V IOH1=-5mA IOH2=-10mA IOH3=-5mA IOH4=-200mA Output Open IOL1=500mA IOL2=500mA IOL3=10mA IOL4=300mA fOSC=3.3MHz, no load C3=0.01mF10%, IO=0 to -10mA Min. 3.8 0.0 -5.0 -100 -5.0 -300 VDD-0.8 VDD-0.8 VDD-0.8 4.0 4.5 -- -- -- -- -- 4.5 Max. 5.5 0.8 +5.0 -5.0 +5.0 -70 VDD VDD VDD 5.5 5.5 2.0 2.0 2.0 0.8 10 5.5 Unit V V mA mA mA mA V V V V V V V V V mA V
*1) *2) *3) *4) *5)
CS, CLOCK, DATA I/O DUP/TRI, A1 to A3, B1 to B3, COL1 to 5 CS, CLOCK, DATA I/O DUP/TRI, A1 to A3, B1 to B3 COL1 to 5 DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2 DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2, ROW1 to 5
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FEDL9222-02 Semiconductor ML9222
AC Characteristics
(Ta=-40 to +85C, VDD=8.0 to 18.5V) Parameter Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time CS Off Time CS Setup Time (CS-Clock) CS Hold Time (Clock-CS) DATA Output Delay Time (Clock-DATA I/O) Output Slew Rate Time VDD Rise Time VDD Off Time CS Wait Time Symbol fC tCW tDS tDH tCSL tCSS tCSH tPD tR tF tPRZ tPOF tRSOFF CL=100pF Condition -- -- -- -- R2=10kW5%, C2=27pF5% -- -- -- tR=20% to 80% tF=80% to 20% Min. -- 400 400 400 20 400 400 -- -- -- -- 5.0 400 Max. 1.0 -- -- -- -- -- -- 1.0 4.0 4.0 100 -- -- Unit MHz ns ns ns ms ns ns ms ms ms ms ms ms
Mounted in a unit Mounted in a unit, VDD=0.0V --
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FEDL9222-02 Semiconductor ML9222
TIMING DIAGRAM
Data Input Timing
tCSS 1/fC tCW CLOCK tDS DATA I/O (INPUT) VALID VALID tDH -3.8V VALID VALID -0.8V tCW tCSH -3.8V -0.8V tCSL -3.8V -0.8V
CS
Data Output Timing
tCSS tCSH -3.8V CLOCK tPD DATA I/O (OUTPUT) -3.8V -0.8V -0.8V -3.8V -0.8V
CS
Reset Timing
tPRZ tRSOFF -3.8V CS -0.0V tPOF -0.8VDD -0.0V
VDD
Driver Output Timing
SEG1-32, GRID1-3 tR tF -0.8VDD -0.2VDD
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FEDL9222-02 Semiconductor A/D Converter Characteristics
(Ta = -40 to +85C, VDD = 8.0 to 18.0 V) Parameter A/D Conversion Accuracy Reference Voltage (VREG) Output Current Input Voltage Range Conversion Time/Channel Condition -- -- -- -- R2 = 10kW5%, C2 = 27pF5% Min. -- 4.5 -- GND 256 Typ. -- 5.0 -- -- 310 Max. 1 5.5 -10 VREG 394 Unit LSB V mA V ms
ML9222
Keyscan Characteristics
(Ta = -40 to +85C, VDD = 8.0 to 18.0 V) Parameter Keyscan Cycle Time Keyscan Pulse Width Condition R2 = 10kW5%, C2 = 27pF5% R2 = 10kW5%, C2 = 27pF5% Min. 160 32 Typ. 194 39 Max. 246 49 Unit ms ms
Keyscan Timing
Keyscan Cycle Time ROW1 Keyscan Pulse Width ROW2
ROW3
ROW4
ROW5
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FEDL9222-02 Semiconductor ML9222 *1bit time=4/fOSC
Output Timing (Duplex Operation) (The dimming data is 1016/1024)
2048bit times (1 display cycle) VDD GRID1 1016bit times 8bit times GRID2 1016bit times D-GND VDD GRID3 3bit times SEG1-32 1019bit times 5bit times 1019bit times 5bit times DIM OUT 1019bit times 1019bit times 5bit times SYNC OUT1 1019bit times 1029bit times 5bit times SYNC OUT2 1029bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1029bit times 5bit times L-GND 5V L-GND 5bit times L-GND 5V 5bit times D-GND 5V 5bit times D-GND VDD 1016bit times 8bit times 8bit times D-GND VDD
Output Timing (Triplex Operation) (The dimming data is 1016/1024)
*1bit time=4/fOSC
3072bit times (1 display cycle) VDD
GRID1
1016bit times 8bit times 8bit times D-GND VDD
GRID2
1016bit times 8bit times D-GND VDD 5bit times D-GND VDD
GRID3 3bit times SEG1-32 1019bit times 5bit times 1019bit times 5bit times DIM OUT 1019bit times 1019bit times 5bit times SYNC OUT1 1019bit times 1029bit times 5bit times SYNC OUT2 1029bit times 1019bit times
1016bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 5bit times 5bit times
D-GND 5V L-GND 5V L-GND 5V L-GND
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FEDL9222-02 Semiconductor ML9222 *1bit time=4/fOSC
Output Timing (Duplex Operation) (The dimming data is 64/1024)
2048bit times (1 display cycle) VDD GRID1 64bit times 960bit times GRID2 64bit times D-GND VDD GRID3 3bit times 957bit times SEG1-32 67bit times 957bit times DIM OUT 67bit times 957bit times SYNC OUT1 67bit times 957bit times SYNC OUT2 1981bit times 67bit times 1981bit times 957bit times 1981bit times L-GND 67bit times 957bit times 67bit times 957bit times L-GND 5V 67bit times 957bit times 67bit times 957bit times L-GND 5V 957bit times 67bit times 957bit times D-GND 5V 957bit times D-GND VDD 960bit times 64bit times 960bit times D-GND VDD
Output Timing (Triplex Operation) (The dimming data is 64/1024)
*1bit time=4/fOSC
3072bit times (1 display cycle) VDD
GRID1
64bit times 960bit times 960bit times 64bit times 960bit times D-GND 64bit times 3bit times 957bit times 957bit times 67bit times 957bit times 957bit times 67bit times 957bit times 957bit times 1981bit times 957bit times 957bit times 67bit times 67bit times L-GND 67bit times 957bit times L-GND 5V 67bit times 957bit times L-GND 5V 67bit times 957bit times D-GND 5V 957bit times VDD D-GND VDD D-GND VDD
GRID2
GRID3
SEG1-32
67bit times
DIM OUT
67bit times
SYNC OUT1
67bit times
SYNC OUT2
1981bit times
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FEDL9222-02 Semiconductor ML9222
FUNCTIONAL DESCRIPTION
Power-on Reset When power is turned on, ML9222 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: * The contents of the shift registers and latches are set to "0". * The digital dimming duty cycle is set to "0". * All segment outputs are set to Low level. * All grid outputs are set to High level. * All the ROW outputs are set to Low level. * INT output is set to Low level. Data Input and Output Data input and output through the DATA I/O pin is valid only when the CS pin is set at a High level. The input data to DATA I/O pin is shifted into the shift register at the rising edge of the serial clock. The data is automatically loaded to the latches when the CS pin is set at a Low level. 10-bit dimming data (D1 to D10) and 32-bit segment data (S1 to S32) are used for inputting of dimming data and display data. To transfer these two data, the mode data (M0 to M2) must be sent after each of these data succeddingly. The output data from the DATA I/O pin is output from the shift register at the rising edge of the serial clock. ML9222 outputs 64-bit (8ch 8bits) A/D data (A11 to A88) and 37-bit key data (S11 to S55, R1, Q11 to Q13, R2, Q21 to Q23, R3 and Q31 to Q33). To receive these data, the mode data (M0 to M2) mast be sent first and then CS must be set once to Low level and set again to High level. Then inputting serial clocks, these data are output from the DATA I/O pin. When the CS pin is set at a Low level, the DATA I/O pin returns to an input pin. To stop the keyscan, the only mode data (M0 to M2) must be sent. After the mode data transfer, the key scanning is stopped immediately. Mode Data ML9222 has the seven function modes. The function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data (M0 to M2) is as follows:
FUNCTION MODE 0 1 2 3 4 5 6 7
OPERATING MODE Segment Data for GRID1-3 Input Segment Data for GRID1 Input Segment Data for GRID2 Input Segment Data for GRID3 Input Digital Dimming Data Input Keyscan Stop Switch Data Output A/D Data Output
FUNCTION DATA M0 0 1 0 1 0 1 0 1 M1 0 0 1 1 0 0 1 1 M2 0 0 0 0 1 1 1 1
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FEDL9222-02 Semiconductor ML9222
Segment Data Input [Function Mode: 0 to 3] * ML9222 receives the segment data when function mode 0 to 3 are selected. * The same segment data is transferred to the 3 segment data latch correspond to GRID 1 to 3 at the same time when the function mode 0 is selected. * The segment data is transferred to only one segment data latch that is selected by mode data, when the function mode is 1, 2 or 3 is selected. * Segment output (SEG1 to 32) becomes High level when the segment data (S1 to 32) is High level. [Data Format] Input Data : 35 bits Segment Data : 32 bits Mode Data : 3 bits
Bit Input Data 1 S1 2 S2 3 S3 4 S4 29 30 31 32 33 M0 34 M1 35 M2
S29 S30 S31 S32
Segment Data (32bits)
Mode Data (3bits)
[Bit correspondence between segment output and segment data]
SEG n SEG n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Segment data S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Segment data S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32
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FEDL9222-02 Semiconductor ML9222
Digital Dimming Data Input [Function Mode: 4] * ML9222 receives the digital dimming data when function mode 4 is selected. * The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. * The 10-bit digital dimming data is input from LSB. [Data Format] Input Data : 13 bits Digital Dimming Data: 10 bits Mode Data : 3 bits
Bit Input Data 1 D1 LSB 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 10 11 12 13
Digital Dimming Data (10bits)
D10 M0 M1 M2 MSB Mode Data (3bits) (MSB)
(LSB) D1 0 1 1 0 1 1 D2 0 0 1 0 0 1 D3 0 0 1 0 0 1 D4 0 0 0 1 1 1
Dimming Data D5 0 0 1 1 1 1 D6 0 0 1 1 1 1 D7 0 0 1 1 1 1 D8 0 0 1 1 1 1 D9 0 0 1 1 1 1
D10 0 0 1 1 1 1
Duty Cycle 0/1024 1/1024 1015/1024 1016/1024 1016/1024 1016/1024
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FEDL9222-02 Semiconductor ML9222
Keyscan Stop [Function Mode: 5] * ML9222 stops a key scanning when function mode 5 are selected. * To select this mode, the only mode data (M0 to M2) is needed. * The actual time lag range between receipt of the keyscan stop command and the ceasing of scanning is 2.4ms to 3.6ms [Input Data Format] Input Data Mode Data
Bit Input Data
: 3 bits : 3 bits
28 M0 29 M1 30 M2
Mode Data (3bits)
Switch Data Output [Function Mode: 6] * ML9222 output the switch data when function mode 6 is selected. * To select this mode, the only mode data (M0 to M2) is needed. * When ML9222 recieves this mode, the DATA I/O pin is changed to an output pin. * 37-bit switch data come out from the DATA I/O pin synchronizing with the rise edge of the clock. * When the CS pin is set at the low level, the DATA I/O pin returns to an input pin. * R1, R2, R3=0, implies Right rotation of the knob (Clockwise) * R1, R2, R3=1, implies Left rotation of the knob (Counter Clockwise) * Contact Count bits are Q11 (LSB) to Q13 (MSB), Q21 (LSB) to Q23 (MSB) and Q31 (LSB) to Q33 (MSB) [Input Data Format] Input Data Mode Data
Bit Input Data
: 3 bits : 3 bits
28 M0 29 M1 30 M2
Mode Data (3bits)
[Output Data Format] Output Data : 37 bits 55 push swithc Data : 25 bits Encoder switch Data : 12 bits
Bit Output Data Bit Output Data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
S11 S12 S13 S14 S15 S21 S22 S23 S24 S25 S31 S32 S33 S34 S35 S41 S42 S43 S44 S45 S51 S52 S53 S54 S55
26 27 28 29 30 31 32 33 34 35 36 37
R1 Q11 Q12 Q13 R2 Q21 Q22 Q23 R3 Q31 Q32 Q33
Sij:i=ROW1 to 5, j=COL1 to 5 Sij=1: Switch ON Sij=0: Switch OFF
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FEDL9222-02 Semiconductor ML9222
A/D Data Output [Function Mode: 7] * ML9222 output the A/D data when function mode 7 is selected. * To select this mode, the only mode data (M0 to M2) is needed. * When ML9222 recieves this mode, the DATA I/O pin is changed to an output pin. * 64-bit A/D data come out from the DATA I/O pin synchronizeing with the rise edge of the clock. * When the CS pin is set at the low level, the DATA I/O pin returns to an input pin. [Input Data Format] Input Data Mode Data
Bit Input Data
: 3 bits : 3 bits
28 M0 29 M1 30 M2
Mode Data (3bits)
[Output Data Format] Output Data A/D Data
Bit Output Data A/D Bit Output Data A/D Bit Output Data A/D Bit Output Data A/D
: 64 bits : 64 bits
1
(LSB)
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
(MSB)
A11 A12 A13 A14 A15 A16 A17 A18 A21 A22 A23 A24 A25 A26 A27 A28
(MSB)(LSB)
CH1
CH2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A31 A32 A33 A34 A35 A36 A37 A38 A41 A42 A43 A44 A45 A46 A47 A48
(LSB) (MSB)(LSB) (MSB)
CH3
CH4
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
A51 A52 A53 A54 A55 A56 A57 A58 A61 A62 A63 A64 A65 A66 A67 A68
(LSB) (MSB)(LSB) (MSB)
CH5 CH6 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
A71 A72 A73 A74 A75 A76 A77 A78 A81 A82 A83 A84 A85 A86 A87 A88
(LSB) (MSB)(LSB) (MSB)
CH7
CH8
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FEDL9222-02 Semiconductor ML9222
The rotary encoder switch function. As figure 1 shows, the rotary encoder switch circuit is consisted of Phase detection, Interrupt generation, Up/down counter, Direction latch and Parallel-in serial-out shift register.
A B
Phase Detection
UP DOWN
Interrupt Generation
for INT
UP/DOWN Counter
Q3 Q2 Q1
Direction Latch
R1
P-in/S-out Shift Registor
Output data
Fig.1 The Rotary Encoder Switch Circuit 1) Phase detection 1-1) Clockwise The input A and B have a chattering absorption circuit of 620ns (typ.). When signal A and B input as fig. 2, the phase detection circuit outputs UP signal after the chattering absorption period. At this time, the output INT also goes to high level, so this signal can be used as an interrupt. The INT stays High level until the switch data-output mode is selected.
A chattering absorption time B
UP (internal)
INT
Fig.2 The Input and Output Timing in Case of Clockwise.
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FEDL9222-02 Semiconductor ML9222
1-2) counter clockwise When signal A and B input as fig. 3, the phase detection circuit outputs Down signal after the chattering absorption period. At this time, the output INT also goes to High level. The INT stays High level until the switch data-output mode is selected.
A chattering absorption time B
DOWN (internal)
INT
Fig.3 The Input and Output Timing in Case of Counter Clockwise.
2) UP/DOWN COUNTER When the UP/DOWN COUNTER is input UP, it counts up and when it is input DOWN, it counts down. But if overcounte of "111" occurs the UP/DOWN COUNTER stays "111".
A
B Q3, Q2, Q1 001 010 011 100 101 110 111 111
Fig.4 3) Direction latch When the Direction latch is input DOWN the output R goes "1". But if the UP pulse is input and the counts value change to plus value, the output R goes to "0".
A
B
R1 Q1, Q2, Q3 100 010 100 000 100 010
Fig.5 19/25
FEDL9222-02 Semiconductor ML9222
4) P-in/S-out shift resistor When the switch data output mode is selected and SC goes L, all the key data send to the shift resistor, and the up/down counter is reset and the INT signal goes "L".
CS Data I/O C1 C2 C3 C4 C5 C1 C2 C3 C4 C5 ROW1 CLOCK ROW2 C1 C2 C3 C4 C5 R1 Q11Q12Q13 R2 Q21Q22Q23 R3 Q31Q32Q33 ROW5 Rotary
INT
When CS goes L, the up/downn counter is reset and the INT goes "L".
Fig.6
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FEDL9222-02 Semiconductor ML9222
Keyscan Keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. The INT pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT pin can be used as an interrupt signal. [Keyscan Timing]
ROW 1
ROW 2 ROW 3
ROW 4
ROW 5 1 Cycle INT
Depress/Release
Keyscan stop mode is selected.
Note: Keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. To stop keyscanning, it is required to select the keyscan stop mode once again.
Depress
Depress
Release
INT
Keyscan
Keyscan
CS
MODE5 MODE5 : Keyscan stop
MODE5
MODE5
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1. Circuit for the duplex VFD tube with 128 segments (2 Grid 64 Anode)
APPLICATION CIRCUITS
Semiconductor
VCC
VDD SEG1 SEG32 GRID1 GRID2 GRID3 GND
VDD
VDISP SEG1 SEG32 GRID1 GRID2 GRID3
S1 S2 S3 G1 S62 S63 S64
ML9222
VDISP DUP/TRI VREG CH1 to 8 GND 55 Key matrix ROW1 to 5 COL1 to 5
MSM9210 (SLAVE)
DUP/TRI M/S
G2
Duplex VFD Tube
Ef
Microcontroller
GND
SYNC OUT 2 SYNC OUT 1 DIM OUT CS DATA I/O CLOCK VCC OSC0 L-GND GND
SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC 0 L-GND
SYNC OUT 2 SYNC OUT 1 DIM OUT
FEDL9222-02
ML9222
GND
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2. Circuit for the triplex VFD tube with 192 segments (3 Grid 64 Anode)
Semiconductor
VCC
VDD SEG1 SEG32 GRID1 GRID2 GRID3
VDD
VDISP SEG1 SEG32 GRID1 GRID2 GRID3
S1 S2 S3 G1 G2 G3 S62 S63 S64
ML9222
VDISP VREG CH1 to 8 GND 55 Key matrix ROW1 to 5 COL1 to 5 DUP/TRI
MSM9210 (SLAVE)
DUP/TRI M/S GND
Triplex VFD Tube
Ef
Microcontroller
GND
SYNC OUT 2 SYNC OUT 1 DIM OUT
CS DATA I/O CLOCK VCC OSC0 L-GND GND
SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC 0 L-GND
SYNC OUT 2 SYNC OUT 1 DIM OUT
FEDL9222-02
ML9222
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GND
FEDL9222-02 Semiconductor ML9222
PACKAGE DIMENSIONS
(Unit : mm) QFP80-P-1420-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL9222-02 Semiconductor ML9222
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
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