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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
MCM62Y308
J PACKAGE 300 MIL SOJ CASE 857-02
Synchronous Line Buffer: 8K x 8 Bit Fast Static Dual Ported Memory
With IEEE Standard 1149.1 Test Access Port and Boundary-Scan (JTAG)
The MCM62Y308 is a synchronous, dual ported memory organized as 8,192 words of 8 bits each, fabricated using Motorola's double-metal, double-poly, 0.65 m CMOS process. It is intended for high speed video or other applications which process data on a line-by-line basis. Through the use of a single clock and port control inputs, separate read and write data ports provide simultaneous access to a common memory array. Simultaneous read/write access to the same address location is also allowed, with old data being read followed by a write of the new data. This allows multiple devices to be cascaded with the output of one directly driving the input of another. In this configuration the data stream can be tapped at strategic interconnect points to perform various digital filtering functions. Since there are no external address inputs, separate internal read and write address counters are provided as a means of indexing the memory array. These counters are preloaded and then selectively incremented or decremented by asserting read enable (RE) and write enable (WE) inputs, allowing cycle to cycle control. The address counters can be reloaded back to their initial values through the use of the read reload (RR) and write reload (WR) control inputs. These inputs initiate the transfer of address reload register values into the address counters which index the memory array. When an address counter reaches 0000 it will roll over on the next count. On the down count the roll over condition will cause the roll-over flag (WRF or RRF) to assert high. On the up count these flags must be treated as don't cares. The roll-over flag outputs are cleared when their associated roll-over reset pin is asserted low. The TDI input is used to write the reload registers using special test access port instructions. The read and write address counters are 16 bits long, and only 13 of the 16 bits are required to index the 8K deep memory array. The remaining three bits are used for depth expansion. These three bits are compared to the lower three bits in the control register, and as long as they are equal that port (i.e., read or write) will remain active. If the bits do not compare, the port will become inactive (i.e., for read outputs, high-z; for write inputs, disabled) however, the counter will continue to count on the rising edge of K as long as the port enable signal (RE or WE) is asserted. The TDI input is used to write the control register using special test access port instructions. The output enable Input can be programmed to be either synchronous or asynchronous through the control register. The MCM62Y308 is available in a 32 pin SOJ package. * 8K x 8 Fast Access Static Memory Array * Single 5 V Power Supply -- MCM62Y308-17: 5% * Synchronous, Simultaneous Read/Write Memory Access * 50 MHz Maximum Clock Cycle Time, < 15 ns Read Access * Single Clock Operation * Separate Read/Write Address Counters with Reload Control * Separate Up/Down Counter Control for Both Read and Write * Separate Roll-Over Flag Outputs for Read and Write * Programmable Output Enable Control (Synchronous or Asynchronous) * Cascadable I/O Interface * IEEE Standard 1149.1 Test Port (JTAG) * Expand ID Register for Depth Expansion * High Board Density SOJ Package
REV 2 5/95
32 1
PIN ASSIGNMENT
WRR D7 D6 D5 D4 D3 D2 D1 D0 VDD K WE WR TDI TCK RRR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 WRF Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VSS G RE RR TDO TMS RRF
PIN NAMES
K . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input WE . . . . . . . . . . . . . . . . . . Write Enable Input WR . . . . . . . . . . Write Address Reload Input RE . . . . . . . . . . . . . . . . . .Read Enable Input RR . . . . . . . . . Read Address Reload Input RRF . . . . . . . . Read Roll-Over Flag Output WRF . . . . . . . Write Roll-Over Flag Output RRR . . . . . . . . Read Roll-Over Reset Input WRR . . . . . . . Write Roll-Over Reset Input G . . . . . . . . . . . . . . . . . Output Enable Input D0 - D7 . . . . . . . . . . . . . . . . . . . . Data Inputs Q0 - Q7 . . . . . . . . . . . . . . . . . . Data Outputs TCK . . . . . . . . . . . . . . . . . . . Test Clock Input TMS . . . . . . . . . . . . . . . . . . Test Mode Select TDI . . . . . . . . . . . . . . . . . . . . Test Data Input TDO . . . . . . . . . . . . . . . . . . Test Data Output VDD . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc. 1994 MOTOROLA FAST SRAM
MCM62Y308 1
BLOCK DIAGRAM
WR WRR
WRITE RELOAD REGISTER UP/DOWN AND CLEAR/RELOAD CONTROL 16 16 WRITE COUNTER 13 3 EXP ID CONTROL REGISTER
WRF WE
D0 D1 INPUT REGISTER OUTPUT LATCH D2 D3 D4 D5 D6 D7 K 13 RE RRF 16 READ COUNTER EXP. ID COMPARE 3
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8
8K x 8 STATIC MEMORY ARRAY
8
UP/DOWN AND CLEAR/RELOAD CONTROL 16 RRR RR READ RELOAD REGISTER TEST ACCESS PORT
TMS TCK TDO TDI
G
TRUTH TABLE (X = Don't Care)
WE X H L H H H H WR L H H H H H H RE X H L H H H H RR L H H H H H H G L L L H X X L Match EXP ID (Read/Write) Match Read/Match Write Match Read/Match Write Match Read/Match Write Match Read/Match Write No Match Read/No Match Write No Match Read/Match Write Match Read/No Match Write Mode (Read/Write) Reload, Read/Reload, Write Disable Count, Read/Write, Count Read Count Disable/Write Disable Count, Read/Write, Count Count, No Read/No Write, Count Count, No Read/Write, Count Count, Read/No Write, Count Supply Current ICC ICC ICC ICC ISB ISB ICC Q0 - 7 Status Data Out Data Out Data Out High-Z High-Z High-Z Data Out
MCM62Y308 2
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
SOJ Pin Locations 11 Symbol K Type Input Description CLOCK - System clock input pin accepting a minimum 8 ns clock high or clock low pulse at a minimum 20 ns clock cycle. All other synchronous inputs excluding the test access port are captured on the rising edge of this signal. WRITE ENABLE - Write enable is captured on K leading edge. When asserted this causes the input data D0 - D7 to be written into the RAM address controlled by the write address counter and increments the counter for the next write. READ ENABLE - Read enable is captured on K leading edge. When asserted increments the counter for the next read operation. This causes a RAM read access from address controlled by the read address counter to be inserted in the output register Q0 - Q7. WRITE RELOAD - Write reload is captured on K leading edge. When asserted this causes the write address counter to be initialized to the contents of the write reload register or "cleared" as specified by control register bit 3. See control register bit 3 for "cleared" description. READ RELOAD - Read reload is captured on K leading edge. When asserted this causes the read address counter to be initialized to the contents of the read reload register or "cleared" as specified by control register bit 5. See control register bit 5 for "cleared" description. OUTPUT ENABLE - When asserted low causes the outputs Q0 - Q7 to become active and when deasserted high causes them to High-Z. This pin can be either synchronous with K leading edge or asynchronous as specified by control register bit 7. DATA INPUT - The levels on these pins are captured on the K leading edge. The value captured will be written into the RAM if WE is also asserted and the expand ID bits match the upper three bits of the write address counter. DATA OUTPUT - Data outputs are available from the read output register < 15 ns from the rising edge of K when RE or RR is asserted. outputs are disabled when the upper three bits of the read address counter do not match the three expand ID bits of the control register. G will also control the disabling of the outputs either synchronously or asynchronously. See G description. ROLL-OVER FLAG - These signals are asserted high on the clock cycle where the address counters (write address counter for WRF and read address counter for RRF) roll-over to 0000 during count down. During count up these pins must be treated as don't cares. ROLL-OVER RESET - The level on these pins is captured on the K leading edge. When asserted low, each will reset their associated roll-over flag output.
12
WE
Input
21
RE
Input
13
WR
Input
20
RR
Input
22
G
Input
9, 8, 7, 6, 5, 4, 3, 2
D0 - D7
Input
24, 25, 26, 27, 28, 29, 30, 31
Q0 - Q7
Output
17, 32
RRF, WRF
Output
16, 1
RRR, WRR
Input
TEST ACCESS PORT PIN DESCRIPTIONS (The Test Access Port Conforms with the IEEE Standard 1149.1. It is also Used to Load Device Specific Registers Used to Configure the MCM62Y308.)
SOJ Pin Locations 15 Symbol TCK Type Input Description TEST CLOCK - Samples and clocks all TAP events. All inputs are captured on TCK rising edge and all outputs propagate from TCK falling edge. It also can take the place of K in device operation in certain test conditions. TEST MODE SELECT - Sampled on the rising edge of TCK. Determines the movement through the TAP state machine (Figure 2). This circuit is designed in such a way that an undriven input will produce a response identical to the application of a logic 1. TEST DATA IN - Sampled on the rising edge of TCK. This is the input side of the serial register placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP state machine and what instruction is active in the TAP instruction register. This circuit is designed in such a way that an undriven input will produce a response identical to the application of a logic 1. TEST DATA OUT - Output that is active depending on the state of the TAP state machine. Output changes off the trailing edge of TCK. This is the output side of the serial register placed between TDI and TDO.
18
TMS
Input
14
TDI
Input
19
TDO
Output
MOTOROLA FAST SRAM
MCM62Y308 3
MAXIMUM RATINGS* (Voltages Referenced to VSS = 0)
Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Symbol VDD Vin, Vout Iout PD Tbias TA Tstg Value - 0.5 to + 7.0 - 0.5 to VDD + 0.5 20 1.0 - 10 to + 85 0 to + 70 - 55 to + 125 Unit V V mA W C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISITICS
(TA = 0 to 70 C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) = - 3.0 V ac (pulse width 20 ns) MCM62Y308-17 Symbol VDD VIH VIL Min 4.75 2.2 - 0.5* Typ 5.0 -- -- Max 5.25 VDD + 0.3 0.8 Unit V V V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VDD) Output Leakage Current (G = VIH, Vout = 0 to VDD) AC Supply Current (G = VIH, Iout = 0 mA, All Inputs VIL = 0.0 V and VIH 3.0, Cycle Time = 20 ns) AC Standby Current (When Expand ID Bits Do Not Match the Read Address Counter, Cycle Time = 20 ns) Output Low Voltage (IOL = + 4.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) ICCA ISB VOL VOH Min 2.4 Max 1.0 1.0 150 100 0.4 Unit A A mA mA V V
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance Output Capacitance (Q0 - Q7, TDO, WRF, RRF) Symbol Cin Cout Typ 4 6 Max 6 8 Unit pF pF
MCM62Y308 4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(TA = 0 to + 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . Terminated 50 Ohm Transmission Line
READ/WRITE CYCLE TIMING
MCM62Y308-17 Parameter Cycle Time Clock High Time Clock Low Time Clock High to Output Valid Clock High to Roll-Over Flag Valid Clock High to Output High-Z Output Enable Low to Output Valid Output Enable High to Output High-Z Setup Times: RE WE WR RRR WRR G RR Data In RE WE RR WR RRR WRR G Data In Symbol tKHKH tKHKL tKLKH tKHQV tKHRFV tKHQZ tGLQV tGHQZ tREVKH tWEVKH tWRVKH tRRRVKH tWRRVKH tGVKH tRRVKH tDVKH tKHREX tKHWEX tKHRRX tKHWRX tKHRRRX tKHWRRX tKHGX tKHDX Min 22 9 9 5 5 5 3 0 2 Max -- -- -- 17 11 15 10 5 -- Unit ns ns ns ns ns ns ns ns ns 1 2, 4 2, 3, 4 5 Notes
3 1 2
-- -- -- ns
6 5 5
Hold Times:
6
NOTES: 1. The outputs High-Z from a clock high edge when the upper three bits of the Read Address Counter do not match the 3 ID Expansion bits. 2. G is a don't care when the three ID expansion bits do not match the upper three bits of the Read Address Counter. 3. tGLQV and tGHQZ only apply when G is programmed as Asynchronous. (See TAP LDCONT instruction.) 4. Transition is measured 500 mV from steady-state voltage. This parameter is sampled and not 100% tested. At any given voltage and temperature, tGHQZ max is less than tGLQV min for a given device and from device to device. 5. This is a synchronous device. All inputs must meet the specified setup and hold times for ALL rising edges of Clock except for G when it is programmed to be asynchronous. 6. tGVKH and tKHGX only apply when G is programmed as synchronous.
AC TEST LOADS
+5V RL = 50 OUTPUT Z0 = 50 VL = 1.5 V OUTPUT 255 5 pF 480
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MCM62Y308 5
READ/WRITE CYCLE TIMING DIAGRAM
tKHKL tKHKH K tKHRRX tRRVKH RR tREVKH RE tKHREX G tGHQZ (NOTE 3) HIGH-Z tGLQV (NOTE 3) tKHQV Q0 - Q7 Qout0 tKHWRX tWRVKH WR tKHWEX WE tWEVKH tDVKH D0 - D7 Din0 tKHDX Din1 Din2 Din3 tWRRVKH, tRRRVKH RRR, WRR tKHRRRX, tKHWRRX tKHRFV (NOTE 1) RRF, WRF tKHRFV Din4 tKHWEX tWEVKH Qout1 Qout2 tKHGX (NOTE 4) tKHQZ (NOTE 2) HIGH-Z tKHQV Qout4 tGVKH (NOTE 4) tKHREX tREVKH tKLKH
NOTE: THIS TIMING DIAGRAM ALSO SHOWS THE FUNCTIONALITY OF THE PART
1. Roll-Over Outputs assert high when counters reach their initial value. This timing diagram shows the relationship between the roll-over output and reset pin only. 2. The outputs High-Z from a clock high edge when the upper three bits of the Read Address Counter do not match the 3 ID Expansion bits. 3. tGLQV and tGHQZ only apply when G is programmed as Asynchronous. (See TAP LDCONT instruction.) 4. tGVKH and tKHGX only apply when G is programmed as synchronous.
MCM62Y308 6
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS FOR THE TEST ACCESS PORT (IEEE 1149.1)
(TA = 0 to + 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . 50 Ohm Transmission Line
TAP CONTROLLER TIMING
MCM62Y308-17 Parameter Cycle Time Clock High Time Clock Low Time Clock Low to Output Valid Clock Low to Output High-Z Clock Low to Output Active Setup Time, Test Mode Select Setup Time, Test Data In Hold Time, Test Mode Select Symbol tCYC tCKH tCKL tA tCKZ tCKX tS tSD tH Min 30 12 12 5 0 0 2 2 2 Max -- -- -- 9 9 9 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns 1 2, 3 Notes
Hold Time, Test Data In tHD 2 -- NOTES: 1. Test Data Out will High-Z from a clock low edge depending on the current state of the TAP state machine. 2. Test Data Out is active only in the SHIFT-IR and SHIFT-DR state of the TAP state machine. 3. Transition is measured 500 mV from steady-state voltage. This parameter is sampled and not 100% tested.
TAP CONTROLLER TIMING DIAGRAM
tCYC TEST CLOCK (TCK) tH TEST MODE SELECT (TMS) tS tCKH tCKL
TEST DATA IN (TDI)
tHD tSD
tA TEST DATA OUT (TDO)
tCKZ
tCKX
MOTOROLA FAST SRAM
MCM62Y308 7
1
TEST-LOGIC RESET 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 0 1 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 0 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 0 0 1 1 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 0 1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 2. TAP Controller State Diagram
MCM62Y308 8
MOTOROLA FAST SRAM
TEST ACCESS PORT DESCRIPTIONS
INSTRUCTION SET A four pin IEEE Standard 1149.1 Test Port (JTAG) is included on this device. There are two classes of instructions; standard instructions as defined in the IEEE 1149.1 standard and device specific, or public, instructions that are used to control the functionality of the device. When the TAP (Test Access Port) controller is in the Shift-IR state the Instruction Register is placed between TDI and TDO, least significant bit closest to TDO. In this state the desired instruction would be serially loaded through the TDI input (while the previous instruction would be shifted out of TDO). The TAP instruction set for this device is listed in Table 1. TAP STANDARD INSTRUCTION SET NOTE: The descriptions in this section are not intended to be used without the supporting IEEE 1149.1-1993 Standard. SAMPLE/PRELOAD TAP INSTRUCTION The SAMPLE/PRELOAD TAP instuction is used to allow scanning of the boudary-scan register without causing interference to the normal operation of the chip logic. The 26 bit boundary scan register contains bits for all device signal and clock pins and associated control signals (Table 2). This register is accessible when the SAMPLE/PRELOAD TAP instruction is loaded into the TAP instruction register. When the TAP controller is then moved to the Shift-DR state, the boundary scan register is placed between TDI and TDO. This scan register can then be used prior to the EXTEST instruction to preload the output pins with desired values so that these pins will drive the desired state when the EXTEST instruction is loaded. It would be used prior to the INTEST instruction to preload values into the input pins. As data is written into TDI, data also streams out of TDO which can be used to pre-sample the inputs and outputs. SAMPLE/PRELOAD would also be used prior to the CLAMP instruction to preload the values on the output pins that will be driven out when the CLAMP instruction is loaded. Table 2 shows the boundary-scan bit definitions. The first column defines the bit's ordinal position in the boundary-scan
register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 0; the last bit to be shifted is 25. The second column is the pin name and the third column is the pin type. EXTEST TAP INSTRUCTION The EXTEST instruction is intended to be used in conjunction with the SAMPLE/PRELOAD instruction to assist in testing board level connectivity. Normally, the SAMPLE/PRELOAD instruction would be used to preload all output pins (i.e., Q0 - Q7, RRF, and WRF). The EXTEST instruction would then be loaded. During EXTEST the boundary-scan register is placed between TDI and TDO in the Shift- DR state of the TAP controller. Once the EXTEST instruction is loaded, the TAP controller would then be moved to the Run- Test/Idle state. In this state one cycle of TCK would cause the preloaded data on the ouput pins to be driven while the values on the input pins would be sampled (Q0 - Q7 will be active only if G is preloaded with a zero; the value of the expand ID bits is ignored). Note that TCK, not the Clock pin, K, is used as the clock input while K is only sampled during EXTEST. After one clock cycle of TCK, the TAP controller would then be moved to the Shift-DR state where the sampled values would be shifted out of TDO (and new values would be shifted in TDI). These values would normally be compared to expected values to test for board connectivity.
THE INTEST TAP INSTRUCTION The INTEST instruction is intended to be used to assist in testing internal device functionality. When the INTEST instruction is loaded the boundary-scan register is placed between TDI and TDO in the Shift-DR state of the TAP controller (Table 2). While in the Shift-DR state, all input pins would be preloaded via the boundary scan register to set up the desired mode (i.e., read, write, reload, etc.). The TAP controller would then be moved to the Run-Test/Idle state. In this state one or more cycles of TCK would cause the preloaded data in the boundary-scan register to be driven while the values of Q0 - Q7 would be sampled (Q0 - Q7 will be active only if G is preloaded with a zero, however the values of Q0 - Q7 will
Table 1. TAP Instruction Set
Instruction Standard Instructions: BYPASS INTEST SAMPLE/PRELOAD EXTEST HIGHZ CLAMP Device Specific (Public) Instructions: LDRREG LDWREG LDBREG LDCONT RDCOUNT EZWRITE EZREAD EZREADZ *Default state at power-up. Code (Binary) 1111* 0111 1100 0000 1010 1001 0001 0100 0101 0010 1000 0011 0110 1110 Description Bypass Instruction Intest Instruction Sample and/or Preload Instruction Extest Instruction High-Z all Output pins while bypass reg. is between TDI and TDO Clamp Output pins while bypass reg. is between TDI and TDO Load Read Address Reload Register Load Write Address Reload Register Load both Address Reload Registers (Write then Read) Load Control Register Read the values of the Read and Write Address Counters Serial Write (using Write Address Counter) Serial Read (using Read Address Counter) Serial Read, outputs High-Z
MOTOROLA FAST SRAM
MCM62Y308 9
be sampled regardless of G). Only one action will be performed in the Run-Test/Idle state no matter how many clock cycles are input. Note that TCK, not the Clock pin(K), is used as the clock input while K is ignored during INTEST. After one or more clock cycles of TCK, the TAP controller would then be moved to the Shift-DR state where the sampled values would be shifted out of TDO (and new values would be shifted in TDI). These values would normally be compared to expected values to test for device functionality. THE INTEST TAP INSTRUCTION The INTEST instruction is intended to be used to assist in testing internal device functionality. When the INTEST instruction is loaded the boundary-scan register is placed between TDI and TDO in the Shift-DR state of the TAP controller (Table 2). While in the Shift-DR state, all input pins would be preloaded via the boundary scan register to set up the desired mode (i.e., read, write, reload, etc.). The TAP controller would then be moved to the Run-Test/Idle state. In this state one or more cycles of TCK would cause the preloaded data in the boundary-scan register to be driven while the values of Q0 - Q7 would be sampled (Q0 - Q7 will be active only if G is preloaded with a zero, however the values of Q0 - Q7 will be sampled regardless of G). Only one action will be performed in the Run-Test/Idle state no matter how many clock cycles are input. Note that TCK, not the Clock pin(K), is used as the clock input while K is ignored during INTEST. After one or more clock cycles of TCK, the TAP controller would then be moved to the Shift-DR state where the sampled values would be shifted out of TDO (and new values would be shifted in TDI). These values would normally be compared to expected values to test for device functionality. Since device functionality can only be verified through sampling the outputs of the device, the most likely use of INTEST would be to first load up the boundary-scan register for a Write Reload and execute the reload in the Run-Test/Idle state. Then a write of the first address would be performed again using the boundary scan register to load up the input registers and executing the write in the Run-Test/Idle state. Lastly, a Read Reload would be executed in the same manner so that the data that had just been written in the first address would be read from the memory array and written into the output registers which would then be shifted out of TDO in the Shift-DR state. The values of the roll-over flags (RRF and WRF) would also be sampled and shifted out at the same time for comparison to expected values. There are easier ways to serially read and write the memory array. See the EZREAD and EZWRITE TAP instruction explanation. CLAMP TAP INSTRUCTION The CLAMP instruction is provided to allow the state of the signals driven from the output pins to be determined from the boundary-scan register while the bypass register is selected as the serial path between TDI and TDO. The signals driven from the output pins will not change while the CLAMP instruction is selected. EXTEST could also be used for this purpose but CLAMP shortens the board scan path by inserting only the
bypass register between TDI and TDO. To use CLAMP, the SAMPLE/PRELOAD instruction would be used first to scan in the values to be driven on the output pins when the CLAMP instruction is active. Q0 - Q7 will be active only if G is preloaded with a zero. HIGH-Z TAP INSTRUCTION The High-Z instruction is provided to allow all the outputs (except TDO) to be placed in an inactive drive state (High-Z), including the Read Roll-Over Flag and the Write Roll-Over Flag outputs. During the High-Z instruction the bypass register is connected between TDI and TDO. BYPASS TAP INSTRUCTION The Bypass instruction is the default instruction loaded in at power up. This instruction will place a single shift register between TDI and TDO during the Shift-DR state of the TAP controller. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Table 2. Boundary Scan Register Bit Definitions
Bit Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name RRF RR RE G Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 WRF WRR D7 D6 D5 D4 D3 D2 D1 D0 K WE WR RRR Pin Type Output Input Input Input Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input Input Input Input Input Input
NOTE: K is a sample-only scan bit. It cannot be pre-loaded for control purposes.
MCM62Y308 10
MOTOROLA FAST SRAM
DEVICE SPECIFIC (PUBLIC) INSTRUCTIONS
LDCONT TAP INSTRUCTION The Control Register is an eight bit register that contains the control bits for the Address Registers and Counters and the Output Enable pin. When the LDCONT TAP instruction is loaded into the Instruction Register, the Control Register is placed between TDI and TDO when the TAP controller is in the Shift-DR state (see Figure 2 and Table 10). The power-up/ preload state and function of the Control bits are found in Table 3. The Expand ID bits provide system depth expansion. These three bits are compared to the upper three bits in the address counters. As long as the three Expand-ID bits match the three upper bits in the address counters the port will stay active. If they do not match, the port will deactivate (i.e., outputs will High-Z or write will be disabled); however, the counters will continue counting as long as RE and WE remain asserted (i.e., high) at the rising edge of Clock. The Reload Control bits (3 and 5) are used to control either reloading the Read and Write Address Counters from the Reload Registers or clearing the counter when RR or WR is asserted. If these bits are set low the counters they control will be cleared to all zeroes if the appropriate reload signal (RR or WR) is asserted and any value in the Reload Register is ignored. This means that if the initial address value desired is address 0000 (or FFFF when counting down) then there is no need to load the Address Reload Registers using the LDRREG, LDWREG, or the LDBREG instructions in the following description. If these bits are set high the counters are loaded up with the values in the Reload Registers when the appropriate reload signal (RR or WR) is asserted. The Up/Down count bits (4 and 6) determine the direction in which the respective Address Counter will count; if the bit is set low the counter will count up and if set high the counter will count down. If the counters are set to count down and the Reload control is set to the clear counter mode, then the initial value in the counters will be FFFF. To ensure that the counter will function properly, a reload (using RR or WR) is required after the count direction is switched. The Output Enable control bit (7) determines the functionality of the Output Enable pin, G. When the bit is low, G functions asynchronously. When set high, G functions synchronously and must meet the specified setup and hold times to the Clock K. The Control Register will also be preloaded. When the instruction 0010 (LDCONT) is in the Instruction Register and the controller is in the Capture-DR state the above preload values (all zeroes) will be loaded into the Control Register. All zeroes will also be loaded in the Control Register at power-up. While new values are shifted in from TDI in the Shift-DR state, all zeroes will be output on TDO for the first eight bits. LDRREG, LDWREG, AND LDBREG TAP INSTRUCTIONS There are three instructions that may be used to load the 16 bit address reload registers: LDRREG (Load Read Address Reload Register), LDWREG (Load Write Address Reload Register), and LDBREG (Load both Address Reload Registers, Write followed by Read). Figure 2 illustrates how the Reload registers are placed between TDI and TDO. Tables 7, 8, and 9 describe each register. These instructions would be used only if the user needed to load the Reload Registers with a non-zero value. If the Address Counters are to always be reset to zeroes (or all 1s if counting down) then only the Control Register need be loaded to affect a reset of the counters. The TAP controller has been set up to make it easier for the user to serially load the Reload Registers. When the TAP controller is clocked into the Capture-IR state (see state diagram) the instruction for loading both registers (0101) will be preloaded into the shift register. This allows the user to go directly to the Update-IR instead of having to serially shift this instruction in through the TDI port. Once the load instruction has been entered the user can then clock over to the Capture-DR state where the value for the reload register(s) is serially loaded (see Figure 2). RDCOUNT TAP INSTRUCTION The RDCOUNT scan register is accessible after the RDCOUNT instruction is loaded into the TAP instruction register in the Shift-IR state and the TAP controller is then moved to the Shift-DR state. This scan register can then be used to shift out the values of the Read and Write Address Counters The RDCOUNT scan-register is a sample only register and can not be used to load values into the counters. See Table 4. EZWRITE TAP INSTRUCTION AND SCAN PATH The EZWRITE TAP instruction is provided to allow the user to more easily and quickly write a large number of bytes to the device serially through the TDI port. EZWRITE shortens the scan path for a serial write to just the 8 bit Data in register (see Table 5). The most likely use of this instruction is as follows: the user would first load the Control Register using the LDCONT instruction. This would initialize the Expand ID bits and the Write Counter. The Write Reload Register will need to be
Table 3. Control Register Bit Description
Bit No. 0-2 3 4 5 6 7 Power Up and Preload State 000 0 0 0 0 0 Function Expand ID bits for comparison with the upper 3 bits of the Read and Write Address counters Reload Control of Write Address Counter (0 = clear counter, 1 = reload) Up/Down count bit for Write Address Counter (0 = count up, 1 = count down) Reload Control of Read Address Counter (0 = clear counter, 1 = reload) Up/Down count bit for Read Address Counter (0 = count up, 1 = count down) G Control (0 = asynchronous, 1 = synchronous)
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MCM62Y308 11
loaded using the LDWREG instruction if a non-zero starting address is desired. If 0000 was the first desired count, setting up the Control Register to "clear" the Write counter is all that is required (Bit 3 set to zero). A reload cycle using SAMPLE/ PRELOAD (WR preloaded low) and INTEST would also have to be run in order to initialize the counter. While still in the INTEST instruction at the Shift-DR state, the proper values of WE and WR would then need to be preloaded for proper operation of EZWRITE (WE high and WR high). After all this initializing is done, the EZWRITE instruction would be loaded into the TAP instruction register in the Shift-IR state. When the TAP controller is then moved to the Shift-DR state the EZWRITE scan path would be inserted between TDI and TDO. This scan path is composed of the 8 bit Data In register (see Table 5). The 8 bits to be written into the first address would be scanned in (sampled values from the Data In pins would be streaming out of TDO at the same time), then the TAP controller would be moved to the Run-Test/Idle state where one cycle of TCK would write the 8 bits into the address and increment the counter. The TAP controller would then move back to the Shift-DR state so that the next byte to be written can be serially loaded and the process would be repeated until all desired bytes were written. During EZWRITE the Q0 - Q7 pins will be in a High-Z state. EZREAD TAP INSTRUCTION AND SCAN PATH The EZREAD TAP instruction is provided to allow the user to more easily and quickly read a large number of bytes from the device serially through the TDO port. EZREAD shortens the scan path for a serial read to just the 8 bit Data Out register (see Table 6). To serially read the device the following would occur: initialization would be much like EZWRITE except that the Read Address Counter should be reladed with the count BEFORE the first one desired. So, if the first read needed to be address 0000 (and the counter is counting up), the Read Reload Register would have to be preloaded with FFFF using the LDRREG instruction. Again, SAMPLE/PRELOAD and INTEST instructions would need to be run to perform a reload cycle followed
by another Boundary-scan that set RE and RR high in anticipation of the EZREAD instruction. Also, WE should be set low to prevent any unintended writes while reading. After this initializing, the EZREAD instruction would be loaded into the TAP instruction register in the Shift-IR state. The TAP controller would move to the Run-Test/Idle state where one cycle of TCK would increment the counter, read the 8 bits from that address, and load them into the Data Output register. The TAP controller would then move to the Shift-DR state and the EZREAD scan path would be inserted between TDI and TDO. This scan path is composed of the 8 bit Data Out register (see Table 6). In the Shift-DR state the Data Out register would be serially scanned out of the TDO port. This sequence through the TAP state machine would then be repeated until all desired bytes were read. EZREAD keeps the Q0 - Q7 pins active (if G is preloaded low) to allow parallel reading of the data out if desired. EZREADZ TAP INSTRUCTION AND SCAN PATH The EZREADZ TAP instruction behaves exactly like the EZREAD instruction except that the all outputs are held in a High-Z mode once the instruction is loaded.
DISABLING THE TEST ACCESS PORT AND BOUNDARY SCAN
It is possible to use this device without utilizing the four pins used for the IEEE 1149.1 Test Access Port. To circuit disable the TAP controller without interfering with normal operation of the device TCK must be tied to VSS to preclude midlevel inputs. Although TDI and TMS are designed in such a way that an undriven input will produce a response identical to the application of a logic 1, it is still advisable to tie these inputs to VDD through a 1 k resistor. TDO should remain unconnected. With the four Test Access Port pins disabled, the device can only be used in its default power-up state. At power up, the device is configured to count up starting at address 0, the reload pins (RR and WR) will clear the counters, the Expand ID bits are set to 000, and the Output Enable pin (G) is configured as an asynchronous input.
MCM62Y308 12
MOTOROLA FAST SRAM
Table 4. RDCOUNT Scan Register Bit Definitions
Bit Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit/Pin Name* RAC0 RAC1 RAC2 RAC3 RAC4 RAC5 RAC6 RAC7 RAC8 RAC9 RAC10 RAC11 RAC12 RAC13# RAC14# RAC15# WAC0 WAC1 WAC2 WAC3 WAC4 WAC5 WAC6 WAC7 WAC8 WAC9 WAC10 WAC11 WAC12 WAC13# WAC14# WAC15# Bit/Pin Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input
Table 5. EZWRITE Scan Path Bit Definitions
Bit Number 0 1 2 3 4 5 6 7 Pin Name D7 D6 D5 D4 D3 D2 D1 D0 Pin Type Input Input Input Input Input Input Input Input
Table 6. EZREAD and EZREADZ Scan Path Bit Definitions
Bit Number 0 1 2 3 4 5 6 7 Bit/Pin Name Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Bit/Pin Type Output Output Output Output Output Output Output Output
Table 7. LDRREG Scan Path Bit Definitions
Bit Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit/Pin Name* RRR0 RRR1 RRR2 RRR3 RRR4 RRR5 RRR6 RRR7 RRR8 RRR9 RRR10 RRR11 RRR12 RRR13 RRR14 RRR15 Bit/Pin Type Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit
* RAC = Read Address Counter WAC = Write Address Counter # These register bits are compared to the three Expand ID bits in the Control Register. (EX0 - 2). Only when there is a match is the read or write allowed to occur. NOTE: Bit 0 closest to TDO.
* RRR = Read Reload Register
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Table 8. LDBREG Scan Path Bit Definitions
Bit Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit/Pin Name* RRR0 RRR1 RRR2 RRR3 RRR4 RRR5 RRR6 RRR7 RRR8 RRR9 RRR10 RRR11 RRR12 RRR13 RRR14 RRR15 WRR0 WRR1 WRR2 WRR3 WRR4 WRR5 WRR6 WRR7 WRR8 WRR9 WRR10 WRR11 WRR12 WRR13 WRR14 WRR15 Bit/Pin Type Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit
Table 9. LDWREG Scan Path Bit Definitions
Bit Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit/Pin Name* WRR0 WRR1 WRR2 WRR3 WRR4 WRR5 WRR6 WRR7 WRR8 WRR9 WRR10 WRR11 WRR12 WRR13 WRR14 WRR15 Bit/Pin Type Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit
* WRR = Write Reload Register
Table 10. LDCONT Scan Path Bit Definitions
Bit Number 0 1 2 3 4 5 6 7 Bit/Pin Name EX0 EX1 EX2 WCC UDW RCC UDR G CONT Bit/Pin Type Register bit Register bit Register bit Register bit Register bit Register bit Register bit Register bit
* RRR = Read Reload Register WRR = Write Reload Register NOTE: Bit number zero is closest to TDO.
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MOTOROLA FAST SRAM
LDRREG LDRREG 12 A READ RELOAD REGISTER TDI WRITE RELOAD REGISTER (MSB) SHIFT CONTROL (LSB) SHIFT CONTROL B (MSB) (LSB) LDBREG
LDBREG
LDWREG LDCONT 12 3 A B C TDO
CONTROL REGISTER (MSB) SHIFT CONTROL THE LEFT MOST CONTROL SIGNAL ENTERING THE MUX FROM THE TOP(1) SELECTS THE UPPER MOST INPUT ON THE LEFT SIDE OF THE MUX(A). THE RIGHT MOST CONTROL SIGNAL SELECTS THE BOTTOM MOST INPUT. (LSB)
Figure 3. Register Load Paths
HIGH-Z, BYPASS, CLAMP EZWRITE EZREAD WRITE ADD. COUNTER MSB LSB READ ADD. COUNTER MSB LSB SAMPLE/PRELOAD, EXTEST, INTEST RDCOUNT
TDI 12 RRR WR WE K A B D0 - D7 WRR WRF 12 A B Q7 - Q0 G RE RR RRF
12 34 5 A B C D E BYPASS REG TDO
THE LEFT MOST CONTROL SIGNAL ENTERING THE MUX FROM THE TOP(1) SELECTS THE UPPER MOST INPUT ON THE LEFT SIDE OF THE MUX(A). THE RIGHT MOST CONTROL SIGNAL SELECTS THE BOTTOM MOST INPUT.
Figure 4. Boundary Scan Paths
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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MCM62Y308 15
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
62Y308
X
XX
Speed (17 = 17 ns) Package (J = SOJ)
Full Part Numbers -- MCM62Y308J17
PACKAGE DIMENSIONS
J PACKAGE 300 MIL SOJ CASE 857-02
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DATUM PLANE -X- LOCATED AT TOP OF MOLD PARTING LINE AND COINCIDENT WITH TOP OF LEAD, WHERE LEAD EXITS BODY. 4. TO BE DETERMINED AT PLANE -X-. 5. TO BE DETERMINED AT PLANE -T-. 6. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 7. 857-01 IS OBSOLETE, NEW STANDARD 857-02. DIM A B C D E F G K L N P R S MILLIMETERS MIN MAX 20.83 21.08 7.74 7.50 3.75 3.26 0.50 0.41 2.48 2.24 0.81 0.67 1.27 BSC 1.14 0.89 0.64 BSC 1.14 0.76 8.64 8.38 6.86 6.60 1.01 0.77 INCHES MIN MAX 0.820 0.830 0.295 0.305 0.128 0.148 0.016 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.035 0.045 0.025 BSC 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040
F 32 PL 0.17 (0.007)
32 1 17
S
A
S
M
NOTE 4
16
-AL G -XDETAIL Z NOTE 3
D 32 PL 0.17 (0.007) P 0.17 (0.007) S B -B-
NOTE 5 S S
A
S
EC R 0.25 (0.010)
S
0.10 (0.004) -TSEATING PLANE
K
S RADIUS B
S NOTE 5
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM62Y308 16
CODELINE TO BE PLACED HERE
*MCM62Y308/D*
MCM62Y308/D MOTOROLA FAST SRAM

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