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19-3386; Rev 2; 6/07
Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier
General Description
The MAX3746 multirate limiting amplifier functions as a data quantizer for SONET, Fibre-Channel, and Gigabit Ethernet optical receivers. The amplifier accepts a wide range of input voltages and provides selectable-level, current-mode logic (CML) output voltages with controlled edge speeds. A received-signal-strength indicator (RSSI) is available when the MAX3746 is DC-coupled to the MAX3744/MAX3724 SFP transimpedance amplifier (TIA). A receiver consisting of the MAX3744/MAX3724 and the MAX3746 can provide up to 19dB RSSI dynamic range. Additional features include a programmable loss-of-signal (LOS) detect, an optional disable function (DISABLE), and an output-signal polarity reversal (OUTPOL). Output disable can be used to implement squelch. The combination of the MAX3746 and the MAX3744/ MAX3724 allows for the implementation of all the smallform-factor SFF-8472 digital diagnostic specifications using a standard 4-pin TO-46 header. The MAX3746 is pin-for-pin compatible with the MAX3748A limiting amplifier and consumes 30% less power. The MAX3746 is packaged in a 3mm x 3mm, 16-pin QFN package. SFP Reference Design Available Low 115mW Power Consumption 16-Pin QFN Package with 3mm x 3mm Footprint 70ps Rise and Fall Time Loss-of-Signal with Programmable Threshold RSSI Interface (with MAX3744/MAX3724 TIA) Output Disable Polarity Select 8.4psP-P Deterministic Jitter (3.2Gbps) Improved EMI Performance Selectable CML Output levels Pin Compatible with MAX3748A
Features
MAX3746
Ordering Information
PART MAX3746ETE MAX3746HETE* TEMP RANGE PINPACKAGE PKG CODE T1633F-3 T1633F-3
-40C to +85C 16 Thin QFN -40C to +85C 16 Thin QFN
Applications
Gigabit Ethernet SFF/SFP Transceiver Modules Fibre-Channel SFF/SFP Transceiver Modules Multirate OC-12 to OC48-FEC SFF/SFP Transceiver Modules
*The MAX3746HETE is a hybrid lead-free package. See the Detailed Description section for more information.
Pin Configuration appears at end of data sheet. Typical Operating Circuits continued at end of data sheet.
Typical Operating Circuits
SFP OPTICAL RECEIVER SUPPLY FILTER 4-PIN TO HEADER OUTPOL VCC HOST BOARD HOST FILTER VCC_RX
0.1F IN+
MAX3744 TIA
OUT+ 0.1F
50 SERDES 50
IN-
OUT-
MAX3746
RSSI TH RTH = 14k GND DISABLE LOS 4.7k TO 10k 2.97V TO 3.6V LOS R1 3k C1 0.1F DS1859 3-INPUT DIAGNOSTIC MONITOR
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier MAX3746
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCC) .................................-0.5V to +4.5V Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V) Voltage at DISABLE, OUTPOL, RSSI, LOS, TH ...................................................-0.5V to (VCC + 0.5V) Current into LOS.....................................................1mA to +9mA Differential Input Voltage (IN+ - IN-) .....................................2.5V Continuous Current at CML Outputs (OUT+, OUT-) ................................................-25mA to +25mA Continuous Power Dissipation (TA = + 70C) 16-Pin QFN (derate 17.7mW above +70C) .....................1.4W Operating Junction Temperature Range (TJ) ....-55C to +150C Storage Ambient Temperature Range (Ts) .......-55C to +150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +3.63V, CML output load is 50 to VCC, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise specified. The data input transition time is controlled by 4th-order Bessel filter with f-3dB = 0.75 x 2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB = 0.75 x 3.2GHz for a data rate of 3.2Gbps.)
PARAMETER Single-Ended Input Resistance Input Return Loss Input Sensitivity Input Overload Single-Ended Output Resistance Output Return Loss SYMBOL RIN se S11 diff S11 VIN-MIN VIN-MAX ROUT diff S22 CONDITIONS Single ended to VCC Single ended, f < 3GHz, DUT is powered on Differential, f < 3GHz, DUT is powered on (Note 1) (Note 1) Single ended to VCC Differential, f < 3GHz, DUT is powered on 4mVP-P < VIN < 1200mVP-P, OUTPOL connected to VCC or GND 4mVP-P < VIN < 1200mVP-P, OUTPOL open or connected to 30k Outputs AC-coupled, VIN-MAX applied to input (Note 2) K28.5 pattern at 3.2Gbps (Note 2) K28.5 pattern at 3.2Gbps at TA = +100C 223 - 1 PRBS equivalent at 2.7Gbps (Note 2) 223 Deterministic Jitter (Note 3) DJ - 1 PRBS equivalent pattern at 2.7Gbps at TA = +100C 8.4 10.2 11.6 13.1 8 9.7 42.5 47.8 69 20 psP-P 23 600 400 1200 42 50 20 800 500 1000 mVP-P 600 10 18 mVP-P 58 MIN 42 TYP 50 14 15 2 4 MAX 58 UNITS dB mVP-P mVP-P dB
CML Differential Output Voltage
Differential Output Signal when Disabled
K28.5 pattern at 2.1Gbps K28.5 pattern at 2.1Gbps at TA = +100C 223 - 1 PRBS equivalent pattern at 622Mbps (Note 2) 223 - 1 PRBS equivalent pattern at 622Mbps at TA = +100C
2
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Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.97V to +3.63V, CML output load is 50 to VCC, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25C, unless otherwise specified. The data input transition time is controlled by 4th-order Bessel filter with f-3dB = 0.75 x 2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB = 0.75 x 3.2GHz for a data rate of 3.2Gbps.)
PARAMETER Random Jitter Data Output Transition Time Input-ReferredNoise Low-Frequency Cutoff Includes the CML output current; OUTPOL connected to VCC or GND Power-Supply Current ICC Includes the CML output current; OUTPOL open or connected to 30k to GND Excludes the CML output current and the CM_RSSI circuitry; OUTPOL connected to VCC or GND (Note 5) Power-Supply Noise Rejection LOSS-OF-SIGNAL (Notes 2, 6) LOS Hysteresis LOS Assert/Deassert Time Low LOS Assert Level Low LOS Deassert Level Medium LOS Assert Level Medium LOS Deassert Level High LOS Assert Level High LOS Deassert Level CM_RSSI SPECIFICATION RSSI Current Gain VCM to IRSSI 3dB Bandwidth Input-Referred RSSI Current Stability RSSI Output Compliance Voltage TTL/CMOS I/O LOS Output High Voltage LOS Output Low Voltage VOH VOL RLOS = 4.7k to 10k to Vcc_host (3V) RLOS = 4.7k to 10k to Vcc_host (3.6V) 2.4 0.4 V V IRSSI ARSSI VRSSI Input < 6.6mA, 0V VRSSI 2.5V (Note 9) -40 0 ARSSI IRSSI / ICM_RSSI (Note 8) 0.031 40 +36 2.0 kHz A V 10 log (VDEASSERT / VASSERT) (Note 7) RTH = 2k RTH = 2k RTH = 14k RTH = 14k RTH = 25k RTH = 25k 36 19.6 1.25 2.3 2.6 4 6 28 42 50 84 2.2 50 6.4 9.6 31.8 54.7 54.3 114 dB s mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P PSNR f < 2MHz SYMBOL CONDITIONS Input = 4mVP-P (Notes 2, 4) 4mVP-P < VINP-P < 1200mVP-P, 20% to 80% (Note 2) (Note 2) 20 35 29 41.5 35 MIN TYP 3 70 MAX 7 114 150 UNITS psRMS ps VRMS kHz
MAX3746
mA
20 40
25 dB
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Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier MAX3746
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.97V to +3.63V, CML output load is 50 to VCC, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise specified. The data input transition time is controlled by 4th-order Bessel filter with f-3dB = 0.75 x 2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB = 0.75 x 3.2GHz for a data rate of 3.2Gbps.)
PARAMETER DISABLE Input High DISABLE Input Low DISABLE Input Current SYMBOL VIH VIL RLOS = 4.7k to 10k to Vcc_host CONDITIONS MIN 2.0 0.8 10 TYP MAX UNITS V V A
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
Between sensitivity and overload, all AC specifications are met. Guaranteed by design and characterization. The deterministic jitter caused by the filter is not included in the DJ generation specification. Random jitter was measured without using a filter at the input. The supply current measurement excludes the CML output currents by connecting the CML outputs to a separate VCC. (See Figure 1.) Hysteresis is calculated as 10 log (VDEASSERT / VASSERT). Unless otherwise specified, the data rate for all LOS detect specifications varies from 622Mbps up to 3.2Gbps, and the patterns are 1010 or 223 - 1 PRBS. The signal is switched between two amplitudes, Signal_On and Signal _Off as shown in Figure 2. ICM_RSSI is the input common-mode current. IRSSI is the current at the RSSI output. Stability is defined as the variation over temperature and power supply with respect to the typical gain of the part.
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3746 toc01
TRANSFER FUNCTION
MAX3746 toc02
RANDOM JITTER vs. TEMPERATURE (INPUT LEVEL 10mVP-P)
9 8 RANDOM JITTER (psRMS) 7 6 5 4 3 2 1 0
MAX3746 toc03
100 90 80 70 CURRENT (mA) 60 50 40 30 20 10 0 CML OUTPUTS NOT INCLUDED CML OUTPUTS INCLUDED OUTPOL = VCC
900 800 DIFFERENTIAL OUTPUT (mVP-P) 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 OUTPOL = VCC
10
-40 -30-20 -10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
-40 -30-20 -10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
DIFFERENTIAL INPUT (mVP-P)
4
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Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
DETERMINISTIC JITTER vs. INPUT COMMON-MODE VOLTAGE (2.7Gbps, K28.5)
MAX3746 toc05
MAX3746
RANDOM JITTER vs. INPUT AMPLITUDE
MAX3746 toc04
BIT-ERROR RATIO vs. INPUT VOLTAGE
1200 1000 BIT-ERROR RATIO (10-12) 800 600 400 200 0 24 DETERMINISTIC JITTER (psP-P) 22 20 18 16 14 12 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (mVP-P)
9 8 RANDOM JITTER (psRMS) 7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35
40
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 COMMON-MODE VOLTAGE (VCC + X)
DIFFERENTIAL INPUT (mVP-P)
OUTPUT EYE DIAGRAM (MINIMUM INPUT)
MAX3746 toc07
OUTPUT EYE DIAGRAM (MAXIMUM INPUT)
MAX3746 toc08
OUTPUT EYE DIAGRAM (MINIMUM INPUT)
MAX3746 toc09
3.2Gbps, K28.5, 4mVP-P
3.2Gbps, K28.5, 1200mVP-P
2.7Gbps, 223 - 1 PRBS, 4mVP-P
100mV/div
100mV/div
100mV/div
50ps/div
50ps/div
100ps/div
OUTPUT EYE DIAGRAM (MAXIMUM INPUT)
MAX3746 toc10
OUTPUT EYE DIAGRAM AT +100C (MINIMUM INPUT)
MAX3746 toc11
ASSERT/DEASSERT LEVELS vs. RTH
MAX3726 toc12
120 LOS ASSERT/DEASSERT (mVP-P) 100 80 60 40 20 0 DEASSERT
2.7Gbps, 223 - 1 PRBS, 1200mVP-P
2.7Gbps, 223 - 1 PRBS, 4mVP-P
100mV/div
100mV/div
ASSERT
50ps/div
50ps/div
0
10 RTH (k)
20
30
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MAX3746 toc06
10
5
Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier MAX3746
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
INPUT RETURN GAIN (SDD11) (INPUT SIGNAL LEVEL = -50dBm) (OUTPUT DISABLED)
MAX3746 toc13
OUTPUT RETURN GAIN (SDD22) (INPUT SIGNAL LEVEL = -50dBm) (WITH INPUT DC OFFSET)
MAX3746 toc14
DETERMINISTIC JITTER vs. INPUT OFFSET VOLTAGE (2.667Gbps, K28.5)
18 DETERMINISTIC JITTER (psP-P) 16 14 12 10 8 6 4 2 0
MAX3746 toc15
30 20 10 GAIN (dB) 0 -10 -20 -30 -40 100M
30 20 10 GAIN (dB) 0 -10 -20 -30 -40 100M
20
1G FREQUENCY (Hz)
10G
1G FREQUENCY (MHz)
10G
-6 -5 -4 -3 -2 -1 0
1
2
3
4
5
6
INPUT OFFSET VOLTAGE (mVP-P)
LOS HYSTERESIS vs. TEMPERATURE (2.667Gbps, 223 - 1 PRBS)
MAX3746 toc16
RSSI CURRENT vs. INPUT TIA CURRENT (MAX3744 and MAX3746)
MAX3746 toc17
6 10 log (DEASSERT/ASSERT) (dB) 5 4 3 2 1 0 RTH = 2.00k
700 600 OUTPUT RSSI CURRENT (A) 500 400 300 200 100 0
RTH = 25k
RTH = 14k
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
0 100 200 300 400 500 600 700 800 900 1000 INPUT TIA CURRENT (A)
SINGLE-ENDED OUTPUT SIGNAL
MAX3746 toc18
RSSI CURRENT vs. OPTICAL POWER (MAX3744 and MAX3746)
MAX3746 toc19
2.7Gbps, 27 - 1, 1000mVP-P OUTPUT RSSI CURRENT (A) 200ps/div
700 600 500 400 300 200 100 0 -30 -25 -20 -15 -10 -5 0 OPTICAL POWER (dBm)
6
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50mV/div
Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier
Pin Description
PIN 1, 4 2 3 5 NAME VCC1 IN+ INTH Supply Voltage Noninverted Input Signal, CML Inverted Input Signal, CML Loss-of-Signal Threshold Pin. Resistor to ground (RTH) sets the LOS threshold. Connecting this pin to VCC disables the LOS circuitry and reduces power consumption. Disable Input, CMOS/TTL. The data outputs are held static when this pin is asserted high. The data outputs are enabled when this pin is asserted low. The LOS function remains active when the outputs are disabled. Noninverted Loss-of-Signal Output. LOS is asserted high when the signal drops below the assert threshold set by the TH input. The output is open collector. Supply Ground Output Polarity Control. Connect to GND for an inversion of polarity through the limiting amplifier and connect to VCC for normal operation. See Table 1 for all settings. Inverted Data Output, CML Noninverted Data Output, CML Output Supply Received-Signal-Strength Indicator. This current output can be used to obtain a ground-referenced voltage proportional to the photodiode current with the MAX3744 by connecting an external resistor between this pin and GND. No Connection. Leave open. Connect the exposed pad to board ground for optimal electrical and thermal performance. FUNCTION
MAX3746
6
DISABLE
7 8, 16 9 10 11 12 13 14,15 EP
LOS GND OUTPOL OUTOUT+ VCC2 RSSI N.C. EXPOSED PAD
Detailed Description
The MAX3746 limiting amplifier consists of an input buffer, a multistage amplifier, offset-correction circuitry, an output buffer, power-detection circuitry, and signaldetect circuitry (see the Functional Diagram).
Offset Correction Loop
The MAX3746 is susceptible to DC offsets in the signal path because it has high gain. In communication systems using NRZ data with a 50% duty cycle, pulsewidth distortion present in the signal, or generated in the transimpedance amplifier, appears as an input offset and is reduced by the offset correction loop.
Input Buffer
The input buffer is shown in Figure 3. It provides 50 termination for each input signal IN+ and IN-. The MAX3746 can be DC- or AC-coupled to a TIA (TIA output offset degrades receiver performance if DC-coupled). The CML input buffer is optimized for the MAX3744/ MAX3724 TIA.
CML Output Buffer
The MAX3746 limiting amplifier's CML output provides high tolerance to impedance mismatches and inductive connectors. The OUTPOL setting programs the output current. Connecting the DISABLE pin to VCC disables the output. If the LOS pin is connected to the DISABLE pin, the outputs OUT+ and OUT- are at a static voltage (squelch) whenever the input signal level drops below the LOS threshold. The output common mode remains constant when the part is disabled. The output buffer can be AC- or DC-coupled to the load (Figure 4).
Gain Stage
The high-bandwidth multistage amplifier provides approximately 60dB of gain.
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Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier MAX3746
VCC
VIN
ICC (SUPPLY CURRENT) IOUT (CML OUTPUT CURRENT)
SIGNAL ON 1dB MAX DEASSERT LEVEL
50
50
6dB
POWER-DETECT WINDOW
MIN ASSERT LEVEL
MAX3746
RTH
SIGNAL OFF 0V TIME
Figure 1. Power-Supply Current Measurement
Figure 2. LOS Assert Threshold Set 1dB Below the Minimum by Receiver Sensitivity for Selected RTH
VCC
VCC
0.25pF IN+
50
50
50
50 OUT+ OUT-
Q3
Q4
Q1
Q2 ESD STRUCTURES
IN0.25pF
DISABLE
DATA
ESD STRUCTURES
I1 = f (OUTPOL, DISABLE)
I2 = f (OUTPOL, DISABLE)
Figure 3. CML Input Buffer
Figure 4. CML Output Buffer
Power Detect and Loss-of-Signal Indicator
The MAX3746 is equipped with multirate LOS circuitry that indicates when the input signal is below a programmable threshold, set by resistor RTH at the TH pin (see the Typical Operating Characteristics for appropriate resistor sizing). An averaging RMS power detector compares the input signal amplitude with this threshold and feeds the signal-detect information to the open-collector LOS output. To prevent LOS chatter in the region of the programmed threshold, approximately 2dB of hysteresis is built into the LOS assert/deassert function. Once
8
asserted, the LOS is not deasserted until the input amplitude rises to the required level (VDEASSERT). (See Figures 2 and 5.)
Hybrid Lead-Free Package
The MAX3746HETE is a MAX3746 in a hybrid lead-free package. It is a hybrid part, which contains high-lead bumps inside a lead-free thin QFN package. The part is not 100% lead free; however, the high-lead solder in the internal portion of the part does meet the RoHS exemption for high-lead solders. For more information, visit www.maxim-ic.com/emmi.
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Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier
VCC
The advantage of this implementation is that it allows the TIA to be packaged in a low-cost, conventional 4pin TO-46 header. The MAX3746 RSSI output is connected to an analog input channel of the DS1858/DS1859 SFP controller to convert the analog information into a 16-bit word. The DS1858/DS1859 provide the receive-power information to the host board of the optical receiver through a 2wire interface. The DS1859 allows for internal calibration of the receive power monitor. The MAX3744/MAX3724 and the MAX3746 have been optimized to achieve RSSI stability of 2.5dB within the 6A to 500A range of average input photodiode current. To achieve the best accuracy, MAXIM recommends receive-power calibration at the low end (6A) and the high end (500A) of the required range. See the RSSI Current Gain graph in the Typical Operating Characteristics.
MAX3746
LOS
ESD STRUCTURE
GND
Figure 5. LOS Output Circuit
Design Procedure
Program the LOS Assert Threshold
External resistor, R TH, programs the loss-of-signal threshold. See the LOS Threshold vs. RTH graph in the Typical Operating Characteristics to select the appropriate resistor.
Connecting to the Dallas DS1858/DS1859
For best use of the RSSI monitor, capacitor C1 and resistor R1 shown in the first Typical Application Circuit need to be placed as close as possible to the Dallas diagnostic monitor with the ground of C1 and R1 the same as the DS1858/DS1859 ground. Capacitor C1 suppresses system noise on the RSSI signal. R1 = 3k and C1 = 0.1F is recommended.
Select the Coupling Capacitor
When AC coupling is desired, coupling capacitors CIN and COUT should be selected to minimize the receiver's deterministic jitter. Jitter is decreased as the input low-frequency cutoff (fIN) is decreased. fIN = 1 / [2(50)(CIN)] For ATM/SONET or other applications using scrambled NRZ data, select (CIN, COUT) 0.1F, which provides fIN < 32kHz. For Fibre Channel, Gigabit Ethernet, or other applications using 8B/10B data coding, select (CIN, COUT) 0.01F, which provides fIN < 320kHz. Refer to Application Note HFAN-1.1, Choosing ACCoupling Capacitors.
EMI Performance
The MAX3746 has been designed for better EMI performance. To help reduce EMI, special care has been taken to produce symmetrical signal outputs. See the eye diagram of the single-ended output in the Typical Operating Characteristics.
Table 1. Logic Table for Polarity and CML Output-Level Settings
OUTPOL VCC Open 30k to GND GND DESCRIPTION Noninverting output with full CML output level Noninverting output with reduced CML output level Inverting output with reduced CML output level Inverting output with full CML output level
RSSI Implementation
The SFF-8472 Digital Diagnostic specification requires monitoring of input receive power. The MAX3746 and MAX3744 receiver chipset allows for the monitoring of the average receive power by measuring the average DC current of the photodiode. The MAX3744/MAX3724 preamp measures the average photodiode current and provides the information to the output common mode. The MAX3746 RSSI detect block senses the common-mode DC level of input signals. IN+ and IN- provide a ground-referenced output signal (RSSI) proportional to the photodiode current.
Chip Information
TRANSISTOR COUNT: 1385 PROCESS: SiGe Bipolar
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Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier MAX3746
Functional Diagram
VCC VCC
50
50 OFFSET CORRECTION
MAX3746
50
50
OUTOUT+
IN+ INOUTPOL DECODE RSSI DETECT RSSI TH POWER DETECT LOS OUTPOL
DISABLE
Typical Operating Circuits (continued)
SFP OPTICAL RECEIVER VCC (+3.3V OR APD REFERENCE VOLTAGE) VCC (+3.3V) 5-PIN TO HEADER OUTPOL VCC SUPPLY FILTER HOST BOARD HOST FILTER VCC_RX
PIN OR APD
MAX3744 TIA
0.1F IN+ OUT+ 0.1F INMAX3746 RSSI TH GND DISABLE LOS 4.7k TO 10k RTH = 14k 2.97V TO 3.6V LOS C1 0.1F OUT50 50 SERDES
DS1859 3-INPUT DIAGNOSTIC MONITOR
R1 3.01k
10
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Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier MAX3746
Typical Operating Circuits (continued)
SFP OPTICAL RECEIVER VCC (+3.3V OR APD REFERENCE VOLTAGE) MAX4004 5-PIN TO HEADER OUTPOL CIN 0.1F IN+
MAX3744 TIA
HOST BOARD
VCC (+3.3V) SUPPLY FILTER HOST FILTER VCC_RX VCC COUT 0.1F OUT+ 50 SERDES INCIN 0.1F MAX3746 RSSI TH GND RTH = 14k DISABLE LOS 4.7k TO 10k 2.97V TO 3.6V LOS OUTCOUT 0.1F 50
PIN OR APD
DS1859 3-INPUT DIAGNOSTIC MONITOR
Pin Configuration
GND 16 VCC1 IN+ INVCC1 1 2 3 4 5 6 7 8 GND MAX3746 N.C. 15 N.C. 14 RSSI 13 12 VCC2 11 OUT+ 10 OUT9 OUTPOL
TH DISABLE LOS
3mm x 3mm QFN
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Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier MAX3746
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MARKING
E E/2
(ND - 1) X e
(NE - 1) X e
D2/2
D/2 D
AAAA
C L
e D2
k
b E2/2
0.10 M C A B
C L
L
E2
0.10 C
0.08 C A A2 A1 L
C L
C L
L
e
e
PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm
21-0136
I
1 2
12
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12x16L QFN THIN.EPS
Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX3746
PKG REF. A b D E e L N ND NE A1 A2 k 0.25 0 0.35
8L 3x3 MIN. NOM. MAX. 0.70 0.25 2.90 2.90 0.75 0.30 3.00 3.00 0.55 8 2 2 0.02 0.20 REF 0.25 0.05 0 0.80 0.35 3.10 3.10 0.75
12L 3x3 MIN. NOM. MAX. 0.70 0.20 2.90 2.90 0.45 0.75 0.25 3.00 3.00 0.55 12 3 3 0.02 0.20 REF 0.25 0.05 0 0.80 0.30 3.10 3.10 0.65
16L 3x3 MIN. NOM. MAX. 0.70 0.20 2.90 2.90 0.30 0.75 0.25 3.00 3.00 0.40 16 4 4 0.02 0.20 REF 0.05 0.80 0.30 3.10 3.10 0.50 PKG. CODES TQ833-1 T1233-1 T1233-3 T1233-4 T1633-2 T1633F-3 T1633FH-3 T1633-4 T1633-5
EXPOSED PAD VARIATIONS
D2 MIN. 0.25 0.95 0.95 0.95 0.95 0.65 0.65 0.95 0.95 NOM. 0.70 1.10 1.10 1.10 1.10 0.80 0.80 1.10 1.10 MAX. 1.25 1.25 1.25 1.25 1.25 0.95 0.95 1.25 1.25 MIN. 0.25 0.95 0.95 0.95 0.95 0.65 0.65 0.95 0.95 E2 NOM. 0.70 1.10 1.10 1.10 1.10 0.80 0.80 1.10 1.10 MAX. 1.25 1.25 1.25 1.25 1.25 0.95 0.95 1.25 1.25 PIN ID 0.35 x 45 0.35 x 45 0.35 x 45 0.35 x 45 0.35 x 45 0.225 x 45 0.225 x 45 0.35 x 45 0.35 x 45 JEDEC WEEC WEED-1 WEED-1 WEED-1 WEED-2 WEED-2 WEED-2 WEED-2 WEED-2
0.65 BSC.
0.50 BSC.
0.50 BSC.
NOTES: 1. 2. 3. 4. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. N IS THE TOTAL NUMBER OF TERMINALS. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. DRAWING CONFORMS TO JEDEC MO220 REVISION C. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. WARPAGE NOT TO EXCEED 0.10mm.
5. 6. 7. 8. 9. 10. 11. 12.
PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm
21-0136
I
2 2
Revision History
Pages changed at Rev 1: 1, 8, 12. Pages changed at Rev 2: 7, 12, 13.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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