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M76DW52003TA M76DW52003BA
32Mbit (4Mb x8/ 2Mb x16, Dual Bank, Boot Block) Flash Memory and 4Mbit (256Kb x16) SRAM, Multiple Memory Product
PRELIMINARY DATA
FEATURES SUMMARY MULTIPLE MEMORY PRODUCT - 32 Mbit (4Mb x8 or 2Mb x16), Dual Bank, Boot Block, Flash Memory - 4 Mbit (256Kb x 16) SRAM SUPPLY VOLTAGE - VCCF = 2.7V to 3.3V - VCCS = 2.7V to 3.3V - VPPF = 12V for Fast Program (optional)

Figure 1. Package
FBGA
ACCESS TIME: 70, 90ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE - Manufacturer Code: 0020h - Top Device Code, M76DW52003TA: 225Eh - Bottom Device Code, M76DW52003BA: 225Fh
LFBGA73 (ZA) 8 x 11.6 mm
FLASH MEMORY PROGRAMMING TIME - 10s per Byte/Word typical - Double Word/ Quadruple Byte Program
EXTENDED MEMORY BLOCK - Extra block used as security block or to store additional information
MEMORY BLOCKS - Dual Bank Memory Array: 8Mbit+24Mbit - Parameter Blocks (Top or Bottom Location)
100,000 PROGRAM/ERASE CYCLES per BLOCK
DUAL OPERATIONS - Read in one bank while Program or Erase in other
SRAM 4 Mbit (256Kb x 16)

ACCESS TIME: 70ns LOW VCCS DATA RETENTION: 1.5V POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS
ERASE SUSPEND and RESUME MODES - Read and Program another Block during Erase Suspend
UNLOCK BYPASS PROGRAM COMMAND - Faster Production/Batch Programming VPP/WP PIN for FAST PROGRAM and WRITE PROTECT TEMPORARY BLOCK UNPROTECTION MODE COMMON FLASH INTERFACE - 64 bit Security Code
September 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A18-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input/Output or Address Input (DQ15A-1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Reset/Block Temporary Unprotect (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCCF Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCCS Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operation Modes, BYTE = VIH(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SRAM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read . . . . . . . . . . . . . . . . . . . . . . . Write . . . . . . . . . . . . . . . . . . . . . . . Standby/Power-Down . . . . . . . . . . Data Retention. . . . . . . . . . . . . . . . Output Disable . . . . . . . . . . . . . . . . ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 11 . . . . 11 . . . . 11 . . . . 11 . . . . 11
FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Flash DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. SRAM Read Mode AC Waveforms, Address Controlled . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. SRAM Read AC Waveforms, G Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. SRAM Write AC Waveforms, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13. SRAM Write AC Waveforms, W Controlled with G Low . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 14. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low . . . . . . . . . . . . . . . . . 20 Table 9. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 15. SRAM Low V CCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled. . . . . . 22 Table 10. SRAM Low VCCS Data Retention Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SRAM Read Mode AC Waveforms, Address Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 16. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline 23 Table 11. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data. . 24 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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SUMMARY DESCRIPTION The M76DW52003TA and M76DW52003BA are low voltage Multiple Memory Products that combine two memory devices; a 32 Mbit Dual Bank, boot block Flash memory (M29DW323D(T/B)) and a 4Mbit SRAM. This document should be read in conjunction with the M29DW323D datasheet. Recommended operating conditions do not allow both the Flash and SRAM devices to be active at the same time. The memory is offered in an LFBGA73 (8 x 11.6mm, 0.8 mm pitch) package and is supplied with all the bits erased (set to `1'). Figure 2. Logic Diagram
VCCF Flash Power Supply VPP/Write Protect Ground SRAM Power Supply SRAM Ground Not Connected Internally
Table 1. Signal Names
A0-A17 A18-A20 DQ0-DQ7 DQ8-DQ14 DQ15A-1 G W Address Inputs common to the Flash Memory and SRAM Address Inputs for Flash Memory only Data Inputs/Outputs Data Inputs/Outputs Data Input/Output or Address Input Output Enable Input Write Enable Input
VPP/WP VCCF 21 A0-A20 EF G W RPF BYTE E1S E2S UBS LBS M76DW52003TA M76DW52003BA 15 DQ0-DQ14 DQ15A-1 VCCS
VPP/WP
VSS VCCS VSSS NC
Flash Memory Control Functions EF RPF Chip Enable Input Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Select
RB
RB BYTE
SRAM Control Functions E1S, E2S UBS LBS Chip Enable Inputs Upper Byte Enable Input Lower Byte Enable Input
VSS
AI08712
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Figure 3. LFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
9
10
A
NC
NC
B
NC
NC
NC
NC
C
NC
A7
LBS
VPP /WP
W
A8
A11
D
A3
A6
UBS
RPF
E2S
A19
A12
A15
E
A2
A5
A18
RB
A20
A9
A13
NC
F
NC
A1
A4
A17
A10
A14
NC
NC
G
NC
A0
VSS
DQ1
DQ6
NC
A16
NC
H
EF
G
DQ9
DQ3
DQ4
DQ13
DQ15 /A-1
BYTE
J
E1S
DQ0
DQ10
VCCF
VCCS
DQ12
DQ7
VSS
K
DQ8
DQ2
DQ11
NC
DQ5
DQ14
M
NC
NC
NC
NC
N
NC
NC
AI08713
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SIGNAL DESCRIPTION See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A17). Addresses A0-A17 are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (W) signals, while the SRAM is accessed through two Chip Enable signals (E1S and E2S) and the Write Enable signal (W). Address Inputs (A18-A20). Addresses A18-A20 are inputs for the Flash component only. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (W) signals Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A- 1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A-1 Low will select the LSB of the addressed Word, DQ15A-1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. Flash Chip Enable (EF). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand RPF is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the device. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the device.
VPP/Write Protect (VPP/WP). The VPP/Write Protect pin provides two functions. The VPP function allows the Flash memory to use an external high voltage power supply to reduce the time required for Program operations. This is achieved by bypassing the unlock cycles and/or using the Double Word or Quadruple Byte Program commands. The Write Protect function provides a hardware method of protecting the two outermost boot blocks in the Flash memory. When V PP/Write Protect is Low, VIL, the memory protects the two outermost boot blocks; Program and Erase operations in these blocks are ignored while VPP/Write Protect is Low, even when RPF is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the two outermost boot blocks. Program and Erase operations can now modify the data in these blocks unless the blocks are protected using Block Protection. When V PP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. When V PP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the M29DW323D datasheet for more details. Reset/Block Temporary Unprotect (RPF). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if V PP/WP is at VIL, then the two outermost boot blocks will remain protected even if RPF is at VID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the M29DW323D datasheet for more details. Holding RPF at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the Flash memory is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode.
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After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the Flash memory. When Byte/Word Organization Select is Low, V IL, the Flash memory is in x8 mode, when it is High, V IH, the Flash memory is in x16 mode. SRAM Chip Enable (E1S, E2S). The Chip Enable inputs activate the SRAM memory control logic, input buffers and decoders. E1 S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S and E2S can also be used to control writing to the SRAM memory array, while W remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. SRAM Upper Byte Enable (UBS). The Upper Byte Enable enables the upper bytes for SRAM (DQ8-DQ15). UBS is active low. SRAM Lower Byte Enable (LBS). The Lower Byte Enable enables the lower bytes for SRAM (DQ0-DQ7). LBS is active low. VCCF Supply Voltage (2.7V to 3.3V). VCCF provides the power supply to the internal core of the Flash Memory device. It is the main power supply for all operations (Read, Program and Erase). VCCS Supply Voltage (2.7V to 3.3V). VCCS provides the power supply for the SRAM control pins. VSS Ground. VSS is the ground reference for all voltage measurements in the Flash and SRAM chips.
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FUNCTIONAL DESCRIPTION The Flash and SRAM components have separate power supplies. They are distinguished by three chip enable inputs: EF for the Flash memory and, E1S and E2S for the SRAM. Recommended operating conditions do not allow both the Flash and the SRAM to be in active mode at the same time. The most common example is Figure 4. Functional Block Diagram
VCCF VPP/WP
simultaneous read operations on the Flash and the SRAM which would result in a data bus contention. Therefore it is recommended to put the SRAM in the high impedance state when reading the Flash and vice versa (see Table 2 Main Operation Modes for details).
EF RPF BYTE Flash Memory 32 Mbit (x16) A18-A20 A0-A17 G W VCCS DQ0-DQ15/A-1 RB
E1S E2S UBS LBS
SRAM 4 Mbit (x16)
VSS
AI08714
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Table 2. Main Operation Modes, BYTE = VIH(2)
Operation Mode Read Flash Memory Write Standby Output Disable Reset EF VIL VIL VIH X X RPF VIH VIH VCC 0.3 VIH VIL G VIL VIH X VIH X VIL Read Flash must be disabled VIL VIL X Write SRAM Flash must be disabled X X Standby/ Power Down X Any Flash mode is allowable X X VIH Output Disable Any Flash mode is allowable VIH VIH W VIH VIL X VIH X VIH VIH VIH VIL VIL VIL X X X VIH VIH VIH E1S E2S UBS LBS DQ15-DQ8 DQ7-DQ0
SRAM must be disabled SRAM must be disabled Any SRAM mode is allowed Any SRAM mode is allowed Any SRAM mode is allowed VIL VIL VIL VIL VIL VIL VIH X X VIL VIL VIL VIH VIH VIH VIH VIH VIH X X VIL VIH VIH VIH VIL VIL VIH VIL VIH VIL X VIH X VIL VIL VIH VIL VIH VIL VIL VIL VIH X VIH X VIL VIH VIL
Data Output Data Input Hi-Z Hi-Z Hi-Z Data out Word Read Data out Hi-Z Hi-Z Data out
Data in Word Write Data in Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Data in
Note: 1. X = Don't Care = VIL or VIH. 2. This table is also valid when BYTE = V IL, with the only difference that DQ15-DQ8 are always high impedance in this case. 3. For the Block Protect and Unprotect features, see the M29DW323D datasheet. Only the In-System Technique is available in the stacked product. 4. The Read Manufacturer Code and Read Device Code operations are not available in the stacked product (see the ""Bus Operations" Tables in M29DW323D datasheet for details). See the "Auto Select Command" in the M29DW323D to read the Manufacturer and Device Codes.
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FLASH MEMORY DEVICE The M76DW52003TA and M76DW52003BA contain one 32 Mbit Flash memory. For detailed information on how to use the Flash memory see the
M29DW323D datasheet, which is available on the STMicroelectronics web site, www.st.com.
SRAM DEVICE The SRAM is a 4Mbit asynchronous random access memory which features a super low voltage operation and low current consumption with an access time of 70ns under all conditions. The memFigure 5. SRAM Logic Diagram
DATA IN DRIVERS
ory operations can be performed using a single low voltage supply, 2.7V to 3.3V, which is the same as the Flash voltage supply.
ROW DECODER
A0-A10
256Kb x 16 RAM Array 2048 x 2048
SENSE AMPS
DQ0-DQ7 DQ8-DQ15
COLUMN DECODER
A11-A17
UBS WS GS LBS
POWER-DOWN CIRCUIT
UBS LBS
E1S E2S
AI07939
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SRAM OPERATIONS There are five standard operations that control the SRAM component. These are Bus Read, Bus Write, Standby/Power-down, Data Retention and Output Disable. A summary is shown in Table 2, Main Operation Modes Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read mode whenever Write Enable, WS, is at VIH, Output Enable, GS, is at VIL, Chip Enable, E1 S, is at VIL, Chip Enable, E2S, is at VIH, and Byte Enable inputs, UBS and LBS are at V IL. Valid data will be available on the output pins after a time of tAVQV after the last stable address. If the Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tE1LQV, tE2HQV, or tGLQV) rather than the address. Data out may be indeterminate at tE1LQX, tE2HQX and tGLQX, but data lines will always be valid at tAVQV (see Table 8, Table 8, Figures 8 and 9, SRAM Read AC Characteristics). Write. Write operations are used to write data to the SRAM. The SRAM is in Write mode whenever W and E1S are at VIL, and E2S is at VIH. Either the Chip Enable inputs, E1 S and E2S, or the Write Enable input, WS, must be deasserted during address transitions for subsequent write cycles. A Write operation is initiated when E1S is at VIL, E2S is at V IH and W is at VIL. The data is latched on the falling edge of E1S, the rising edge of E2S or the falling edge of W S, whichever occurs last. The Write cycle is terminated on the rising edge of E1S, the rising edge of W or the falling edge of E2S, whichever occurs first.
If the Output is enabled (E1S=VIL, E2S=VIH and GS=VIL), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. The Data input must be valid for t DVWH before the rising edge of Write Enable, for t DVE1H before the rising edge of E1S or for tDVE2L before the falling edge of E2S, whichever occurs first, and remain valid for tWHDX, tE1HAX or tE2LAX (see Table 9, SRAM Write AC Characteristics, Figures 11, 12, 13 and 14). Standby/Power-Down. The SRAM component has a chip enabled power-down feature which invokes an automatic standby mode (see Table 8, SRAM Read AC Characteristics, Figure 10, SRAM Standby AC Waveforms). The SRAM is in Standby mode whenever either Chip Enable is deasserted, E1S at V IH or E2S at VIL. It is also possible when UBS and LB S are at VIH. Data Retention. The SRAM data retention performance as VCCS goes down to VDR are described in Table 10, SRAM Low VCCS Data Retention Characteristic, and Figure 15, SRAM Low V CCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled. In E1S controlled data retention mode, the minimum standby current mode is entered when E1S VCCS - 0.2V and E2S 0.2V or E2S VCCS - 0.2V. In E2S controlled data retention mode, minimum standby current mode is entered when E2S 0.2V. Output Disable. The data outputs are high impedance when the Output Enable, GS, is at VIH with Write Enable, W S, at VIH.
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 3. Absolute Maximum Ratings
Value Symbol TA TBIAS TSTG VIO VCCF VPPF VCCS Parameter Min Ambient Operating Temperature (1) Temperature Under Bias Storage Temperature Input or Output Voltage Flash Supply Voltage Program Voltage SRAM Supply Voltage -40 -50 -65 -0.5 -0.6 -0.6 -0.5 Max 85 125 150 VCCF +0.3 4 13.5 3.8 C C C V V V V Unit
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Depends on range.
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DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4, Operating and AC Measurement Conditions. Designers should check that the operating conditions
in their circuit match the measurement conditions when relying on the quoted parameters. The operating and AC measurement parameters given in this section (see Table 4 below) correspond to those of the stand-alone Flash and SRAM devices. For compatibility purposes, the M29DW323D voltage range is restricted to VCCS in the stacked product.
Table 4. Operating and AC Measurement Conditions
Flash Memory Parameter Min VCCF Supply Voltage VCCS Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 to VCCF VCCF/2 2.7 - -40 30 10 0 to VCCF VCCF/2 Max 3.6 - 85 Min - 2.7 -40 30 3.3 Max - 3.3 85 V V C pF ns V V SRAM Units
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
VCCF
VCCF VCCF/2 0V
AI08186
VPP VCCF 25k DEVICE UNDER TEST 0.1F 0.1F CL 25k
CL includes JIG capacitance
AI08187
Table 5. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V, f=1 MHz VOUT = 0V, f=1 MHz Typ Max 12 15 Unit pF pF
Note: Sampled only, not 100% tested.
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Table 6. Flash DC Characteristics
Symbol ILI ILO ICC1(2) ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) Test Condition 0V VIN VCC 0V VOUT VCC EF = VIL, G = VIH, f = 6MHz EF = VCC 0.2V, RPF = VCC 0.2V Program/Erase Controller active VPP/WP = VIL or VIH VPP/WP = VPP VIL VIH VPP IPP VOL VOH VID VLKO Input Low Voltage Input High Voltage Voltage for VPP/WP Program Acceleration Current for VPP/WP Program Acceleration Output Low Voltage Output High Voltage Identification Voltage Program/Erase Lockout Supply Voltage VCC = 3.0V 10% VCC = 3.0V 10% IOL = 1.8mA IOH = -100A VCC -0.4 11.5 1.8 12.5 2.3 -0.5 0.7VCC 11.5 Min Max 1 1 10 100 20 20 0.8 VCC +0.3 12.5 15 0.45 Unit
A A
mA
A
mA mA V V V mA V V V V
ICC3
(1,2)
Supply Current (Program/ Erase)
Note: 1. Sampled only, not 100% tested. 2. In Dual operations the Supply Current will be the sum of I CC1(read) and I CC3 (program/erase).
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Table 7. SRAM DC Characteristics
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0V VIN VCCS 0V VOUT VCCS, SRAM Outputs Hi-Z E1S VCCS - 0.2V VIN VCCS - 0.2V or VIN 0.2V f = fmax (A0-A17 and DQ0-DQ15 only) f = 0 (GS, WS, UBS and LBS) E1S VCCS - 0.2V VIN VCCS - 0.2V or VIN 0.2V, f = 0 f = fmax = 1/AVAV, VCCS = 3.3V, IOUT = 0 mA f = 1MHz, VCCS = 3.3V, IOUT = 0 mA VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCCS = VCC min IOL = 2.1mA VCCS = VCC min IOH = -1.0mA 2.4 -0.3 2.2 Min Typ Max 1 1 Unit A A
7
15
A
ICCS
VCC Standby Current
7 5.5 1.5
15 12 3 0.8 VCCS +0.3 0.4
A mA mA V V V V
ICC
Supply Current
Note: 1. Sampled only, not 100% tested.
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Figure 8. SRAM Read Mode AC Waveforms, Address Controlled
tAVAV A0-A17 tAVQV tAXQX DQ0-DQ15 DATA VALID DATA VALID VALID
AI07942
Note: E1S = Low, E2S = High, G = Low, UBS and/or LBS = High, W = High.
Figure 9. SRAM Read AC Waveforms, G Controlled
tAVAV A0-A17 tE1LQV E1S tE1LQX tE2HQV E2S tE2HQX tBLQV UBS, LBS tBLQX tGLQV G tGLQX DQ0-DQ15 DATA VALID
AI07943b
VALID tE1HQZ
tE2LQZ
tBHQZ
tGHQZ
Note: Write Enable (W) = High. Address Valid prior to or at the same time as E1S, UBS and LB S going Low.
Figure 10. SRAM Standby AC Waveforms
E1S
E2S ICC tPU 50% tPD
AI07913b
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Table 8. SRAM Read AC Characteristics
SRAM Symbol tAVAV tAVQV tAXQX tBHQZ tBLQV tBLQX tE1LQV tE2HQV tE1LQX tE2HQX tE1HQZ tE2LQZ tGHQZ tGLQV tGLQX tPD (1) tPU (1) Alt tRC tACC tOH tBHZ tAB tBLZ tACS1 tCLZ1 tHZCE tOHZ tOE tOLZ Read Cycle Time Address Valid to Output Valid Address Transition to Output Transition UBS, LBS Disable to Hi-Z Output UBS, LBS Access Time UBS, LBS Enable to Low-Z Output Chip Enable 1 Low or Chip Enable 2 High to Output Valid Chip Enable 1 Low or Chip Enable 2 High to Output Transition Chip Enable High or Chip Enable 2 Low to Output Hi-Z Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable 1 High or Chip Enable 2 Low to Power Down Chip Enable 1 Low or Chip Enable 2 High to Power Up 0 5 70 10 25 25 35 5 70 10 25 70 Parameter Min 70 70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only. Not 100% tested.
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Figure 11. SRAM Write AC Waveforms, W Controlled
tAVAV A0-A17 VALID tAVWH tE1LWH E1S tWHAX
E2S tE2HWH tAVWL W tBLWH UBS, LBS tWLWH
G tGHQZ DQ0-DQ15 tDVWH tWHDZ
Note 2
INPUT VALID
AI07944b
Note: 1. W, E1S, E2S, UBS and/or LBS must be asserted to initiate a write cycle. Output Enable (G) = Low (otherwise, DQ0-DQ15 are high impedance). If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 2. The I/O pins are in output mode and input signals must not be applied.
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Figure 12. SRAM Write AC Waveforms, E1S Controlled
tAVAV A0-A17 VALID tAVE1H tAVE2L tAVE1L E1S tE1LE1H tE1HAX
E2S tAVE2H tE2HE2L tWLE1H tWLE2L W tBLE1H tBLE2L UBS, LBS tE2LAX
G tGHQZ DQ0-DQ15 tDVE1H tDVE2L tE1HDZ tE2LDZ
Note 3
INPUT VALID
AI07945b
Note: 1. WS, E1S, E2S, UBS and/or LBS must be asserted to initiate a write cycle. Output Enable (GS) = Low (otherwise, DQ0-DQ15 are high impedance). If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 2. If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance. 3. The I/O pins are in output mode and input signals must not be applied.
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Figure 13. SRAM Write AC Waveforms, W Controlled with G Low
tAVAV A0-A17 VALID tAVWH tE1LWH tE2HWH E1S tWHAX
E2S
tBLWH UBS, LBS tAVWL W tWHQX tWLQZ DQ0-DQ15 tDVWH INPUT VALID
AI07946b
tWLWH
tWHDZ
Note: 1. If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
Figure 14. SRAM Write Cycle Waveform, UBS and LB S Controlled, G Low
tAVAV A0-A17 VALID tAVBH tE1LBH tE2HBH E1S
E2S tAVBL UBS, LBS tWLBH W tDVBH DQ0-DQ15 INPUT VALID
AI07947b
tBLBH
tBHAX
tBHDZ
Note: 1. If E1S, E2S and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
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Table 9. SRAM Write AC Characteristics
SRAM Symbol tAVAV tAVE1L, tAVE2H, tAVWL, tAVBL tAVE1H, tAVE2L tAVWH tBLWH tBLE1H tBLE2L tAVBH tBLBH tDVE1H, tDVE2L, tDVWH tDVBH tE1HAX, tE2LAX, tWHAX tBHAX tE1HDZ , tE2LDZ, tWHDZ tBHDZ tE1LE1H, tE1LBH tE1LWH tE2HE2L, tE2HBH, tE2HWH tGHQZ tWHQX tWLBH tWLQZ tWLWH tWLE1H tWLE2L Alt tWC Write Cycle Time Parameter Min 70 Max ns Unit
tAS
Address Valid to Beginning of Write
0
ns
tAW tAW
Address Valid to Chip Enable 1 Low or Chip Enable 2 High Address Valid to Write Enable High
60 60
ns ns
tBW
UBS, LBS Valid to End of Write
60
ns
tBW
UBS, LBS Low to UBS, LBS High
60
ns
tDW
Input Valid to End of Write
30
ns
tWR
End of Write to Address Change
0
ns
tHD
Address Transition to End of Write
0
ns
tCW1
Chip Enable 1 Low to End of Write
60
ns
tCW2 tGHZ tDH tWP tWHZ tWP
Chip Enable 2 High to End of Write Output Enable High to Output Hi-Z Write Enable High to Input Transition Write Enable Low to UBS, LBS High Write Enable Low to Output Hi-Z Write Enable Pulse Width
60 25 5 50 25 50
ns ns ns ns ns ns
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Figure 15. SRAM Low VCCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled
DATA RETENTION MODE VCCS VCCS (min) tCDR tR VCCS (min)
E1S or UBS, LBS
AI07918b
Table 10. SRAM Low VCCS Data Retention Characteristic
Symbol ICCDR VDR tCDR tR Parameter Supply Current (Data Retention) Supply Voltage (Data Retention) Chip Disable to Power Down Operation Recovery Time Test Condition VCCS = 1.5V, E1S VCCS - 0.2V, VIN VCCS - 0.2V or VIN 0.2V 1.5 0 70 Min Typ 3 Max 10 3.3 Unit A V ns ns
2. Sampled only. Not 100% tested.
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PACKAGE MECHANICAL Figure 16. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline
D FD FE SD D1
E
E1
SE
BALL "A1" e A A1 b A2 ddd
BGA-Z50
Note: Drawing is not to scale.
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Table 11. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 11.600 8.800 0.800 0.400 1.400 0.400 0.400 - - - - - - 11.500 0.910 0.400 8.000 7.200 0.100 11.700 0.4567 0.3465 0.0315 0.0157 0.0551 0.0157 0.0157 - - - - - - 0.4528 0.350 7.900 0.450 8.100 0.250 0.0358 0.0157 0.3150 0.2835 0.0039 0.4606 0.0138 0.3110 0.0177 0.3189 Min Max 1.400 0.0098 Typ Min Max 0.0551 inches
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PART NUMBERING Table 12. Ordering Information Scheme
Example: Device Type M76 = MMP (Flash + SRAM) Architecture D = Dual Operation Operating Voltage W = VCCF = VCCS = 2.7V to 3.3V Flash Device Size (Die1 Density) 5 = 32 Mbit SRAM Device Size (Die2 Density) 2 = 4 Mbit Die3 0 = Die3 Density Die4 0 = Die4 Density Flash Specification Details 3T = 1/4 & 3/4 partitioning, Top boot block 3B = 1/4 & 3/4 partitioning, Bottom boot block Stacked Specification Details A = 0.15m Flash & SRAM Speed 70 = 70ns 90 = 90ns Package and Temperature Range Z = LFBGA73: 8 x 11.6mm, 0.8mm pitch Option T = Tape & Reel packing
M76DW 5 2 0 0 3T A
70
ZT
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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REVISION HISTORY Table 13. Document Revision History
Date 07-Jul-2003 23-Sep-2003 Version 1.0 1.1 First Issue Voltage supply range extended 2.7V working at all speed options Revision Details
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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