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| DRAM MODULE M466F0804DT1-L M466F0804DT1-L EDO Mode 8M x 64 DRAM SODIMM Using 4Mx16, 4K Refresh 3.3V, Low power/Self-Refresh GENERAL DESCRIPTION The Samsung M466F0804DT1-L is a 8Mx64bits Dynamic RAM high density memory module. The Samsung 8-pin M466F0804DT1-L consists of eight CMOS 4Mx16bits DRAMs in TSOP 400mil packages and a 2K EEPROM in TSSOP package mounted on a 144-pin glass-epoxy substrate. A 0.1uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M466F0804DT1-L is a Small Out-line Dual in-line Memory Module and is intended for mounting into 144 pin edge connector sockets. FEATURES * Part Identification - M466F0804DT1-L(4096 cycles/128ms, TSOP, L-ver) * Extended Data Out Mode Operation * New JEDEC standard proposal with EEPROM * Serial Presense Detect with EEPROM * CAS-before-RAS Refresh capability * Self -refresh capability * RAS-only and Hidden refresh capability * LVTTL compatible inputs and outputs * Single +3.3V0.3V power supply * PCB : Height(1000mil), double sided component PERFORMANCE RANGE Speed -L50 -L60 tRAC 50ns 60ns tCAC 13ns 15ns tRC 84ns 104ns tHPC 20ns 25ns PIN CONFIGURATIONS Pin Front 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS CAS0 CAS1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 Back VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS CAS4 CAS5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 Pin 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 Front DQ13 DQ14 DQ15 VSS RSVD RSVD RFU VCC RFU W RAS0 RAS1 OE VSS RSVD RSVD VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 Pin 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 Back DQ45 DQ46 DQ47 VSS RSVD RSVD RFU VCC RFU RFU RFU RFU RFU VSS RSVD RSVD VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 Pin 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Front DQ22 DQ23 VCC A6 A8 VSS A9 A10 VCC CAS2 CAS3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC Pin 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Back DQ54 DQ55 VCC A7 A11 VSS NC NC VCC CAS6 CAS7 Vss DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 Vss SCL VCC PIN NAMES Pin Name A0 to DQ0 - DQ63 W OE RAS0, RAS1 CAS0 - CAS7 VCC VSS NC SDA SCL RSVD RFU Function Address Inputs Data In/Out Read/Write Enable Output Enable Row Address Strobe Column Address Strobe Power(+3.3V) Ground No Connection Serial Address / Data I/O Serial Clock Reserved Use Reserved for Future Use REV. 0.1 Oct. 2000 DRAM MODULE FUNCTIONAL BLOCK DIAGRAM RAS0 RAS1 W OE A0-A11 DQ0~15 CAS0 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U0 M466F0804DT1-L DQ32~47 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U4 U2 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ48~63 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U6 CAS4 CAS1 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16~31 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UCAS CAS5 CAS2 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U1 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U5 U3 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U7 CAS6 CAS3 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UCAS CAS7 VCC 0.1uF Capacitor for each DRAM Vss To all DRAMs SCL Serial PD A0 A1 A2 SDA Vss REV. 0.1 Oct. 2000 DRAM MODULE ABSOLUTE MAXIMUM RATINGS * M466F0804DT1-L Item Symbol Rating Unit Voltage on any pin relative VSS VIN, VOUT -0.5 to +4.6 V Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 V Storage Temperature Tstg -55 to +125 C Power Dissipation PD 8 W Short Circuit Output Current IOS 50 mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3*2 Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Unit V V V V *1 : VCC+1.3V at pulse width15ns, which is measured at VCC. *2 : -1.3V at pulse width15ns, which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICCS II(L) IO(L) VOH VOL ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 Speed -50 -60 Dont care -50 -60 -50 -60 Dont care -50 -60 Dont care Dont care Dont care M466F0804DT1-L Min - Max 484 444 8 484 444 364 324 1.6 484 444 2.8 2.8 10 10 0.4 Unit mA mA mA mA mA mA mA mA mA mA mA mA uA uA V V -10 -10 2.4 - ICCS I(IL) I(OL) VOH VOL : Operating Current * (RAS, CAS, Address cycling @tRC=min) : Standby Current (RAS=CAS=W=VIH) : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) : Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min) : Standby Current (RAS=CAS=W=VCC-0.2V) : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) : Battery back-up current. Average power supply, Battery back-up mode. Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS,LCAS=0.2V, DQ=Dont care, tRC=31.25us, tRAS=tRASmin~300ns : Self Refresh Current, RAS=UCAS=LCAS=VIL, W=OE=A0~A11=VCC-0.2V or 0.2V, DQ~DQ63=VCC-0.2V or Open : Input Leakage Current (Any input 0VINVcc+0.3V, all other pins not under test=0 V) : Output Leakage Current(Data Out is disabled, 0VVOUTVCC) : Output High Voltage Level (IOH = -2mA) : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC. REV. 0.1 Oct. 2000 DRAM MODULE CAPACITANCE (TA = 25C, VCC=3.3V, f = 1MHz) Item Input capacitance[A0-A11] Input capacitance[W, OE] Input capacitance[RAS0, RAS1] Input capacitance[CAS0 - CAS7] Input/Output capacitance[DQ0 - 63] Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min - M466F0804DT1-L Max 50 66 38 24 24 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, VCC=3.3V0.3V. See notes 1,2.) Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z OE to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command set-up time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period CAS to W dealy time RAS to W dealy time Symbol Min -50 Max Min 104 153 50 13 25 3 3 3 1 30 50 8 38 8 17 12 5 0 7 0 7 25 0 0 0 0 7 7 8 7 0 7 128 33 70 38 84 10K 37 25 10K 13 50 3 3 3 1 40 60 10 40 10 20 15 5 0 10 0 10 30 0 0 0 0 10 10 10 10 0 10 128 10K 45 30 10K 13 50 60 15 30 84 128 -60 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 6,14 6 15 8,18 8,18 7 7 6 6 12 12 4 9 3,4,9 3,4,5 3,9 3 3 3,11 2 Unit Note tRC tRWC tRAC tCAC tAA tCLZ tOLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tRWL tCWL tDS tDH tREF tCWD tRWD REV. 0.1 Oct. 2000 DRAM MODULE AC CHARACTERISTICS (0CTA70C, VCC=3.3V0.3V. See notes 1,2.) Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Column address to W delay time CAS precharge to W delay time CAS setup time (CAS-before-RAS refresh) CAS hold time (CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper page mode cycle time Hyper page mode read-modify write cycle time CAS precharge time (Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width(Hyper page cycle) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Symbol Min -50 Max Min 53 58 5 10 5 28 20 67 7 50 30 10 10 13 10 3 5 5 3 3 15 5 5 5 5 100 90 -50 13 13 13 13 3 5 5 3 3 15 5 5 5 5 100 110 -50 200K 25 73 10 60 35 10 10 45 47 5 10 5 M466F0804DT1-L -60 Max Unit ns ns ns ns ns 35 ns ns ns ns 200K ns ns ns ns 15 13 ns ns ns ns ns 15 15 ns ns ns ns ns ns ns us ns ns Note 6 6 16 17 3 10 10 13 tAWD tCPWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tWRP tWRH tOEA tOED tOEZ tOEH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE tRASS tRPS tCHS 3 11 19,20,21 19,20,21 19,20,21 REV. 0.1 Oct. 2000 DRAM MODULE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. tWCS, tRWD, tCWD, tAWD and tCPWD are non-restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tRWDtRWD(min), tCWDtCWD(min), tAWDtAWD(min) and tCPWDtCPWD(min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. 7. Either tRCH or tRRH must be satisfied for a read cycle. 8. These parameters are referenced to the CAS leading edge in early write cycles. 9. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit access time is controlled by tAA. M466F0804DT1-L 10. tASC6ns, Assume tT=2.0ns 11. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going , the open circuit condition of the output is achieved by RAS going. 12. tASC is referenced to the earlier CAS falling edge and tCAH is referenced to the later CAS falling edge. 13. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. 14. tCWD is referenced to the later CAS falling edge at word readmodify-write cycle. 15. tCWL is specified from W falling edge to the earlier CAS rising edge. 16. tCSR is referenced to earlier CAS falling edge to the RAS falling edge. 17. tCHR is referenced to the later CAS rising from RAS falling edge. 18. tDS, tDH is specified by the earlier CAS falling edge. 19. If tRASS100us, then RAS precharge time must use tRPS instead of tRP. 20. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096 cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 21. For distributed CAS-before-RAS with 15.6us interval CASbefore-RAS should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. REV. 0.1 Oct. 2000 DRAM MODULE READ CYCLE M466F0804DT1-L tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tWEZ tAA OE VIH VIL - tCEZ tOEZ tOEA DQ VOH VOL - tRAC OPEN tOLZ tCAC tCLZ tREZ DATA-OUT Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN M466F0804DT1-L tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRAD tRSH tCAS tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN M466F0804DT1-L tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tRAL tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ VIH VIL - Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE READ - MODIFY - WRITE CYCLE M466F0804DT1-L tRAS RAS VIH VIL - tRWC tRP tCRP CAS VIH VIL - tRCD tRAD tRAH tRSH tCAS tASR VIH VIL - tASC tCAH tCSH A ROW ADDR COLUMN ADDRESS tAWD tCWD W VIH VIL - tRWL tCWL tWP tRWD OE VIH VIL - tOEA tOLZ tCLZ tCAC tAA tRAC VALID DATA-OUT tOED tOEZ tDS tDH VALID DATA-IN DQ VI/OH VI/OL - Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE READ CYCLE M466F0804DT1-L tRASP RAS VIH VIL o tRP tCSH tCRP CAS VIH VIL - tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS tRCD tCAS tRAD tASR A VIH VIL - tRAH tASC tCAH tASC tCAH tASC tCAH COLUMN ADDR tASC tCAH tREZ ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tCPA tCAC tAA tCPA tCAC tOEA tCAC tAA tCPA tOCH tOEA tOEP tDOH VALID DATA-OUT tCAC tAA tCHO tOEP tAA OE VIH VIL - tCAC tRAC DQ VOH VOL - tOEA tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ tOEZ tOLZ tCLZ VALID DATA-OUT Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN M466F0804DT1-L tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS o tHPC tCP tRSH tCAS tASR A VIH VIL - tRAH tCAH tASC tCAH o o tASC tCAH ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP tCWL o o o tWCS tWCH tWP tCWL tRWL tWP tCWL OE VIH VIL - tDS DQ VIH VIL - tDH VALID DATA-IN tDS tDH o VALID DATA-IN tDS tDH o VALID DATA-IN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE READ-MODIFY-WRITE CYCLE M466F0804DT1-L RAS VIH VIL - tRASP tCSH tCRP tRSH tHPRWC tRCD tCAS tRAD tRAH tASR tASC COL. ADDR tRP tCP tCAS tRAL tCRP CAS VIH VIL - tCAH tASC COL. ADDR tCAH A VIH VIL - ROW ADDR tRCS W VIH VIL - tCWL tWP tCWD tAWD tCPWD tOEA tOED tRWL tCWL tWP tCWD tAWD tRWD tOEA tCAC tAA tRAC tCAC OE VIH VIL - tOED tDH tDS tAA tDH tOEZ tDS tOEZ DQ VI/OH VI/OL - tCLZ tOLZ VALID DATA-OUT tCLZ VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HYPER PAGE READ AND WRITE MIXED CYCLE M466F0804DT1-L tRASP RAS VIH VIL READ(tCAC) READ(tCPA) WRITE READ(tAA) tRP tHPC tCP CAS VIH VIL - tHPC tCP tCP tCAS tASC COL. ADDR tHPC tCAS tASC tCAH COL. ADDR tRAD tASR tRAH tASC tCAS tCAH tCAS tCAH tCAH tASC COLUMN ADDRESS A VIH VIL - ROW ADDR COLUMN ADDRESS tRCS W VIH VIL - tRCH tRCS tRCH tWCS tWCH tRCH tWPE tCLZ tCPA OE VIH VIL - tWED DQ VI/OH VI/OL - tOEA tCAC tAA tRAC tWEZ tDH tWEZ VALID DATA-OUT tDS VALID DATA-IN tAA VALID DATA-OUT tREZ VALID DATA-OUT Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC RAS VIH VIL - M466F0804DT1-L tRP tRAS tCRP tRPC tCRP CAS VIH VIL - tASR A VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Dont care tRP RAS VIH VIL - tRC tRAS tRP tRPC tCP tCSR tCHR tRPC CAS VIH VIL - tWRP W VIH VIL - tWRH tCEZ DQ VOH VOL - OPEN Dont care Undefined * In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. REV. 0.1 Oct. 2000 DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) M466F0804DT1-L tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRRH tWRH tWRP tAA OE VIH VIL - tOEA tOLZ tCAC tCLZ tRAC tOEZ DATA-OUT tCEZ tREZ tWEZ DQ VOH VOL - OPEN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN M466F0804DT1-L tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP tRCD tRSH tCHR CAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWCS W VIH VIL - tWRP tWCH tWP tWRH OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE M466F0804DT1-L tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W OE VIH VIL VIH VIL - tWRP tWRH tRCS tAA tCAC tRRH tRCH DQ VOH VOL - tCLZ tOEA tOEZ DATA-OUT tCEZ tREZ tWEZ WRITE CYCLE W VIH VIL VIH VIL - tWRP tWRH tWCS tRWL tCWL tWCH tWP OE tDS DQ VIH VIL - tDH DATA-IN READ-MODIFY-WRITE tWRP W VIH VIL - tWRH tRCS tAWD tCWD tCAC tWP tCWL tRWL tAA tOEA OE VIH VIL - tOED tCLZ tOEZ tDS tDH DQ VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Dont care Undefined NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. REV. 0.1 Oct. 2000 DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care M466F0804DT1-L tRP RAS VIH VIL - tRASS tRPS tRPC tCP tCSR tCHS tRPC CAS VIH VIL - tCEZ DQ VOH VOL - OPEN W VIH VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Dont care tRC tRAS tRPC tCP CAS VIH VIL - tRP RAS VIH VIL - tRP tRPC tCSR tCHR tWTS W VIH VIL - tWTH tCEZ DQ VOH VOL - OPEN Dont care Undefined REV. 0.1 Oct. 2000 DRAM MODULE PACKAGE DIMENSIONS M466F0804DT1-L Units : Inches (millimeters) 2.66(67.60) 0.160.039 (4.000.1) 2.50(63.60) 2-R 0.078 Min (2.00 Min) 0.13(3.30) 0.91(23.20) 1.29(32.80) 0.18 (4.60) 0.083 (2.10) 0.79 (20.00) 0.10 (2.50) ( Front view ) Z Y 0.24 (6.0) 1.15 (3.70) 1.01 (25.654) 2- 0.07 (1.80) 0.150Max (3.81Max) ( Back view ) 0.040.0039 (1.000.10) 0.162 Min (4.11 Min) 0.060.0039 (1.500.1) 0.1600.0039 (4.000.1) 0.0240.001 (0.600.05) Detail Y (2.25 Min) 0.10 Min 0.0080.006 (0.2000.150) 0.03 TYP (0.80 TYP) Detail Z Tolerances : .005(.13) unless otherwise specified The used device is 4Mx16 DRAM with EDO mode, TSOP II DRAM Part No. : K4E641612D-T REV. 0.1 Oct. 2000 |
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