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| Filtronic Solid State FEATURES LPV1500 1 W Power PHEMT DRAIN DRAIN * * * * * * +31.5 dBm Typical Power at 18 GHz 8.5 dB Typical Power Gain at 18 GHz +27 dBm at 3.3V Battery Voltage +45 dBm Typical Intercept Point 50% Power-Added-Efficiency at 18 GHz Plated Source Thru-Vias SOURCE GATE DIE SIZE: 16.5 x 16.1 mils (420 x 410 m) DIE THICKNESS: 3.0 mils (75 m typ.) BONDING PADS: 1.9 x 2.4 mils (50 x 60 m typ.) DESCRIPTION AND APPLICATIONS The LPV1500 is an Aluminum Gallium Arsenide / Indium Gallium Arsenide (AlGaAs/InGaAs) Pseudomorphic High Electron Mobility Transistor (PHEMT), utilizing an Electron-Beam direct-write 0.25 m by 1500 m Schottky barrier gate. The recessed "mushroom" gate structure minimizes parasitic gate-source and gate resistances. The epitaxial structure and processing have been optimized for reliable high-power applications. The LP1V500 also features Si3N4 passivation and is available in a flanged ceramic package (P100). The LPV1500 features plated source thru-vias for improved performance. Typical applications include commercial and military high-performance power amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, and medium-haul digital radio transmitters. The LP1500 may be procured in a variety of grades, depending upon specific user requirements. Standard lot screening is patterned after MIL-STD-19500, JANC grade. Space-level screening to FSS JANS grade is also available. PERFORMANCE SPECIFICATIONS (TA = 25C) SYMBOLS IDSS P1dB G1dB IP3 ADD IMAX GM VP IGSO BVGS BVGD J PARAMETERS Saturated Drain-Source Current VDS = 2V VGS = 0V Output Power at 1dB Gain Compression f = 18 GHz VDS = 8.0V, IDS = 50% IDSS Power Gain at 1dB Gain Compression f = 18 GHz VDS = 8.0V, IDS = 50% IDSS Output 3rd-Order Intercept Pt. VDS = 8V, IDS = 40% IDSS, Power-Added Efficiency Maximum Drain-Source Current VDS = 2V VGS = +1V Transconductance VDS = 2V VGS = 0V Pinch-Off Voltage VDS = 2V IDS = 5mA Gate-Source Leakage Current VGS = -5V Gate-Source Breakdown Voltage IGS = 8mA Gate-Drain Breakdown Voltage IGD = 8mA Thermal Resistivity MIN 375 TYP 490 MAX 600 UNITS mA 30.0 6.5 31.5 8.5 45 50 925 450 -1.2 10 -15 -16 45 dBm dB dBm % mA mS V A V V C/W 350 -0.25 -12 -12 -2.0 75 DSS-041 WA Phone: (408) 988-1845 Internet: http://www.filtronicsolidstate.com Fax: (408) 970-9950 Filtronic Solid State ABSOLUTE MAXIMUM RATINGS (25C) 1 SYMBOL PARAMETER RATING VDS Drain-Source Voltage +12V VGS Gate-Source Voltage -5V IDS Drain-Source Current 2 x IDSS IG Gate Current 70 mA PIN RF Input Power 750 mW TCH Channel Temperature +175C TSTG Storage Temperature -65/175C 3,4 PT Power Dissipation 3.33W LPV1500 1 W Power PHEMT RECOMMENDED CONTINUOUS OPERATING LIMITS 2 SYMBOL PARAMETER RATING VDS Drain-Source Voltage +8V VGS Gate-Source Voltage -1V IDS Drain-Source Current 0.8 x IDSS IG Gate Current 15 mA PIN RF Input Power 300 mW TCH Channel Temperature +150C TSTG Storage Temperature -20/50C 3,4 PT Power Dissipation 3.0 W GXdB Gain Compression 8 dB NOTES: 1. Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device. 2. Recommended Continuous Operating Limits should be observed for reliable device operation. 3. Power Dissipation defined as: PT (PDC + PIN) - POUT, where: PDC = DC bias power, POUT = RF output power, and PIN = RF input power. PT(W) 4. Power Dissipation to be de-rated as follows: 5. Specifications subject to change without notice. o 3.33 3.0 -24 mW/ C o Example #1: VDS = 8V, IDS = 315 mA PIN = POUT = 0 dBm (quiescent condition): PT = PDC = 2.52W Max. continuous T HS = 37C Example #2: VDS = 8V, IDS = 315 mA PIN = 23 dBm POUT = 31 dBm PT = (2.52+0.2) - 1.26 = 1.46W Max. continuous T HS = 84C -22-22 mW/ C o mW/ C 25 150 HANDLING PRECAUTIONS: PHEMT chips should be stored in a dry nitrogen environment until assembly. Care should be exercised during handling to avoid damage to the devices. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A (0-500V), and further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. ASSEMBLY INSTRUCTIONS: The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280290C; maximum time at temperature is 1 min. The recommended wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm) gold wire. Stage temperature should be 250-260C. APPLICATIONS NOTES AND DESIGN DATA: Applications Notes are available from your local FSS Sales Representative, or directly from the factory. Complete design data, including S-parameters, Noise data, and Large-Signal models, is available on 3.5" diskette, or may be down-loaded from our Web Page. 175THS( C) 175 o DSS-041 WA Phone: (408) 988-1845 Internet: http://www.filtronicsolidstate.com Fax: (408) 970-9950 |
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