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Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
* 16 differential 3.3V LVPECL outputs * CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency up to 500MHz * Translates any single-ended input signal to 3.3V LVPECL levels with a resistor bias on nCLK input * Output skew: 75ps (maximum) * Part-to-part skew: 250ps (maximum) * 3.3V output operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8530-01 is a low skew, 1-to-16 Differential-to-3.3V LVPECL Fanout Buffer and a memHiPerClockSTM ber of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The high gain differential amplifier accepts peak-topeak input voltages as small as 150mV as long as the common mode voltage is within the specified minimum and maximum range.
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Guaranteed output and part-to-part skew characteristics make the ICS8530-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK nCLK
PIN ASSIGNMENT
nCLK VCCO Q15 nQ15 Q14 nQ14 VEE Q13 nQ13 Q12 nQ12 VCCO
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7
Q15 nQ15 Q14 nQ14 Q13 nQ13 Q12 nQ12 Q11 nQ11 Q10 nQ10 Q9 nQ9 Q8 nQ8
VCCO Q11 nQ11 Q10 nQ10 VEE Q9 nQ9 Q8 nQ8 VCCO VCC
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8530-01
CLK VCCO nQ0 Q0 nQ1 Q1 VEE nQ2 Q2 nQ3 Q3 Vcco
48-Pin LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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VCCO nQ4 Q4 nQ5 Q5 VEE nQ6 Q6 nQ7 Q7 VCCO VCC
REV. B AUGUST 8, 2001
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Power Output Output Power Output Output Power Output Output Output Output Output Output Description Output supply pins. Connect to 3.3V. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pins. Connect to ground. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Positive supply pins. Connect to 3.3V. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 11, 14, 24, 25, 35, 38, 48 2, 3 4, 5 6, 19, 30, 43 7, 8 9, 10 12, 13 15, 16 17, 18 20, 21 22, 23 26, 27 28, 29 36 37 39, 40 41, 42 44, 45 46, 47 NOTE: Pullup and Name VCCO Q11, nQ11 Q10, nQ10 VEE Q9, nQ9 Q8, nQ8 VCC Q7, nQ7 Q6, nQ6 Q5, nQ5 Q4, nQ4 Q3, nQ3 Q2, nQ2 CLK nCLK Q15, nQ15 Q14, nQ14 Q13, nQ13 Q12, nQ12 Pulldown refers
Input Pulldown Non-inver ting differential clock input. Input Pullup Inver ting differential clock input. Output Differential output pair. LVPECL interface levels. Output Differential output pair. LVPECL interface levels. Output Differential output pair. LVPECL interface levels. Output Differential output pair. LVPECL interface levels. to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
CLK, nCLK
Test Conditions
Minimum
Typical 51 51
Maximum 4
Units pF K K
TABLE 3. FUNCTION TABLE
Inputs CLK 0 1 0 1 Biased; NOTE 1 nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 LOW HIGH LOW HIGH HIGH Outputs Q0 thru Q15 nQ0 thru nQ15 HIGH LOW HIGH LOW LOW Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting
Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 7, Figure 8, which discusses wiring the differential input to accept single ended levels.
ICS8530DY-01
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REV. B AUGUST 8, 2001
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V -0.5V to VCCO + 0.5V 47.9C/W -65C to 150C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCO IEE Parameter Input/core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 120 Units V V mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 0.85 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO-2V.
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REV. B AUGUST 8, 2001
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD Parameter Maximum Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 88 500MHz 1 Test Conditions Minimum Typical Maximum 500 2 75 250 700 700 53 Units MHz ns ps ps ps ps %
tsk(o) tsk(pp)
tR tF
odc Output Duty Cycle 47 50 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS8530DY-01
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REV. B AUGUST 8, 2001
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCCO VCC
SCOPE
Qx
LVPECL
VCC = 2V 5% VCCO = 2V 5%
nQx
VEE = -1.3V 0.135V
FIGURE 1 - OUTPUT LOAD TEST CIRCUIT
V CC
CLK
V
nCLK
PP
Cross Points
V
CMR
VEE
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
Qx
nQx
Qy
nQy
tsk(o)
FIGURE 3 - OUTPUT SKEW
ICS8530DY-01
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REV. B AUGUST 8, 2001
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Qx PART 1 nQx
Qy PART 2 nQy
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
80%
80% V
SWING
20% Clock Inputs and Outputs t t
20%
R
F
FIGURE 5 - INPUT
AND
OUTPUT RISE
AND
FALL TIME
CLK
nCLK
Q0 - Q15 nQ0 - nQ15
t
PD
FIGURE 6 - PROPAGATION DELAY
CLK, Qx nCLK, nQx
Pulse Width t t odc = t
PW PERIOD
PERIOD
FIGURE 7 - odc & tPERIOD
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ICS8530DY-01
REV. B AUGUST 8, 2001
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K CLK_IN + V_REF C1 0.1uF R2 1K
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
ICS8530DY-01
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REV. B AUGUST 8, 2001
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8530-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8530-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 415.8mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 16 * 30.2mW = 483.2mW
Total Power_MAX (3.465V, with all outputs switching) = 415.8mW + 483.2mW = 899mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 47.9C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.899W * 47.9C/W = 113.1C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance qJA for 48-pin LQFP, Forced Convection
qJA by Velocity (Linear Feet per Minute) 0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS8530DY-01
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REV. B AUGUST 8, 2001
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 9.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 9 - LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ]*(V
L CC_MAX
-V
OH_MAX
) )
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ]*(V
L CC_MAX
-V
OL_MAX
*
For logic high, V
OUT
=V
OH_MAX
=V
CC_MAX
- 1.0V = 1.625V
OH_MAX
Using V
CC_MAX
= 2.625, this results in V =V
OL_MAX
*
For logic low, V
OUT
=V
CC_MAX
- 1.7V = 0.925V
OL_MAX
Using V
CC_MAX
= 2.625, this results in V
Pd_H = [(1.625V - (2.625V - 2V))/50 ]*(1V) = 20mW Pd_L = [(0.925V - (2.625V - 2V))/50 ]*(1.7) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. B AUGUST 8, 2001
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute) 0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8530-01 is: 930
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REV. B AUGUST 8, 2001
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. B AUGUST 8, 2001
Integrated Circuit Systems, Inc.
ICS8530-01
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Marking ICS8530DY-01 ICS8530DY-01 Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8530DY-01 ICS8530DY-01T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8530DY-01
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