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HV461
Initial Release
HV461FG Ring Generator Controller IC
Features
3.3V operation, logic inputs 3.3V & 5V compatible Digital control of ring frequency, amplitude, and offset Control via 8-bit bus or via individual inputs 8 built-in ring frequencies: 162/3, 20, 25, 331/3, 40, 50, 60Hz External ring frequency input Low distortion sine wave synthesizer AC-only, AC+DC, or DC-only ringer output Adjustable over-current protection Internal precision voltage references Power-on reset and undervoltage lockout for hotswap capability Sync output with adjustable lead time for synchronizing ringing relays Fault output for problem detection Open or closed loop operation Efficient 4-quadrant operation Zero-cross turn-on with zero-cross turn-off option
Description
The HV461FG is a highly integrated Ring Generator controller IC designed to work with a patented four-quadrant inverter topology, with Synchronous Rectifiers on the secondary side to achieve higher efficiencies. The inverter delivers the desired ring voltage from a standard -48V Telecom power supply. HV461 consists of a sine wave synthesizer that can provide eight different ring frequencies for universal applications. Any other frequency in the 12 to 63 Hz range can be obtained by applying an external logic signal to the IC. A transparent latch permits control of the ringer output through the 8-bit bus or individually. The output amplitude and DC offset can be digitally controlled providing high flexibility to the designers. The patented inverter topology using the HV461 controller IC is capable of achieving higher efficiencies, typically over 80%, and drive up to a 40 REN load. The controller allows ring generators to provide a floating 94VAC (rms) waveform that can be referenced to either the -48V or any other offset level by using the programmable offset pins of the IC. Output offset may be achieved by directly generating the offset within the power stage, or by floating the output stage on a DC source, or both. HV461 also has an internal Boost Converter that can be used to provide the gate drive voltages for the two MOSFETS on the primary side and the two secondary rectifiers on the secondary side.
Applications
PBX DLC Key Systems Remote Terminal Wireless Loop Systems
Typical Application
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV461
Absolute Maximum Ratings
VDD Digital Inputs Analog Inputs Storage Temperature Operating Temperature +4.0V -0.5V to +7.0V -0.5V to +7.0V -65C to +150C -40C to +85C
Ordering Information
Package Option 48 lead TQFP Order Number HV461FG
Specifications
External Supply
Symbol VDD IDD Parameter
(unless otherwise specified: VDD = +3.3V, TA = -40C to +85C)
Min 3.0
Typ 3.3 7
Max 3.6 30
Unit V mA
Conditions fPWM=100kHz fosc=19.6608MHz SW outputs NC Open loop config External VGD
Supply Voltage Supply Current (AVDD + DVDD)
Gate Drive Supply
Symbol VGD IGD VDR(lo) VDR(hi) tRISE tFALL fGD DGD Parameter Boost circuit voltage Gate drive supply current Drive voltage, low Drive voltage, hi Rise time Fall time Converter frequency Duty cycle 45 50 VDD-0.4 100 100 same as PWM 55 % Min 9.0 Typ 9.6 Max 10.2 5 10 0.2 Unit V mA mA V V ns ns VDD=2.97-3.63V, SW outputs unloaded VDD=2.50-2.93V, SW outputs unloaded IOUT=-10A IOUT=10A CL=200pF CL=200pF Conditions
Voltage Reference
Symbol VREF1 TCREF1 Vref1 VREF2 TCREF2 Vref2 Parameter Reference voltage 1 Temperature coefficient Output regulation Reference voltage 2 Temperature coefficient Output regulation -12.5 -6.25 2.475 2.500 500 0 Min 1.237 Typ 1.250 200 +6.25 2.525 Max 1.263 Unit V V/C mV V V/C mV Iout=0-100A source Iout=100A Ta=25C Conditions Ta=25C
2
HV461
Logic Inputs
Symbol VIN(lo) VIN(hi) IIN(lo) IIN(hi) CIN tS tH Parameter Input voltage low Input voltage high Input current low Input current high Input capacitance Set-up time Hold time 0.7*VDD -1 1 10 100 100 Min Typ Max 0.3*VDD Unit V V A A pF ns ns VIN=0V VIN=5.0V Conditions
RESET
Symbol VRESET(ON) VRESET(OFF) VRESET (HYS) IP-UP Parameter RESET on voltage RESET off voltage RESET hysteresis RESET pull-up current Min 1.200 1.000 0.150 7.0 Typ 1.325 1.125 0.200 10.0 Max 1.450 1.250 0.250 13.0 Unit V V V A Conditions
Undervoltage Lockout
Symbol VDD(ON) VDD(OFF) VDD(HYS) VGD(ON) VGD(OFF) VGD(HYS) Parameter VDD on voltage VDD off voltage VDD hysteresis VGD on voltage VGD off voltage VGD hysteresis 7.0 0.20 Min 2.75 2.60 0.10 same as VGD regulation point Typ 2.85 Max 2.95 Unit V V V V V V Conditions
Fault Output
Symbol VOUT(lo) KFAULT(on) KFAULT(off) tFAULT(hold) Parameter Output voltage low FAULT on threshold FAULT off threshold FAULT hold time 6 1 50 8 2 Min Typ Max 0.2 10 3 Unit V %* %* mS Conditions IOUT=1mA CFAULT=10F CFAULT=10F CFAULT=10F
* Percent of time PWM overrange or overcurrent is active.
Amplifiers
Symbol VIN IIN VOFFSET VOUT(min) VOUT(max) AVOL CMRR Parameter Input Range Input Bias Current Input Offset Voltage Min output Max output Open Loop Gain Common mode rejection ratio VDD -0.2 60 -40 3 Min 0.25 -500 -5 0.1 VDD -0.1 80 -60 dB dB Typ Max 2.50 500 5 0.2 Unit V nA mV V IOUT=100uA IOUT=100uA VIN=0.5V to VDD-0.5 Conditions
HV461 GBW SL PSRR Gain-Bandwidth Product Slew Rate Power supply rejection ratio 1 0.1 -30 MHz V/s dB f<10kHz
Sinewave Synthesizer
Symbol VDC A f0 f1 f2 f3 f4 f5 f6 f7 f THD ROUT Parameter DC level Amplitude Frequency Frequency Frequency Frequency Frequency Frequency Frequency Frequency Frequency accuracy Harmonic distortion Output resistance 14.4 72.0 16.0 80.0 Min 1.237 1.940 Typ 1.250 2.000 16 2/3 20 25 30 33 /3 40 50 60 0.1 3 17.6 88.0
1
Max 1.263 2.060 0
Unit V VP-P VP-P Hz Hz Hz Hz Hz Hz Hz Hz % % k k
Conditions AMP00 AMP=00 FREQ=000, fOSC=19.6608MHz FREQ=001, fOSC=19.6608MHz FREQ=010, fOSC=19.6608MHz FREQ=011, fOSC=19.6608MHz FREQ=100, fOSC=19.6608MHz FREQ=101, fOSC=19.6608MHz FREQ=110, fOSC=19.6608MHz FREQ=111, fOSC=19.6608MHz fosc=19.6608MHz CSINE=33nF fring=16 2/3 to 60Hz AMP00 AMP=00
External Ring Frequency
Symbol fCAP(lo) fCAP(hi) VIN(lo) VIN(hi) Parameter Capture frequency low* Capture frequency high* Input low Input high 0.7*VDD
-5 +5
Min
Typ 12 63
Max
Unit Hz Hz
Conditions
loop filter=(33F+10k)||4.7F loop filter=(33F+10k)||4.7F
0.3*VDD
V V
deg loop filter=(33F+10k)||4.7F
Phase jitter, sine ref out RING * Lock range is the same as capture range
Sine Reference Attenuator
Symbol VDC AOFF ALO AMED AHI VIN Parameter DC level Attenuation Attenuation Attenuation Attenuation Input range 0.495 0.742 0.990 0.2 0.500 0.750 1.000 Min 1.237 Typ 1.250 Max 1.263 0.010 0.505 0.758 1.010 VDD-0.2V Unit V V/V V/V V/V V/V V Conditions VIN(DC)=1.250V AMP=00 AMP=01 AMP=10 AMP=11
DC REF Multiplexer
Symbol VIN IIN IOFF Parameter Input range Input bias current Off leakage current 4 Min 0.0 -500 Typ Max VDD +500 1.0 Unit V nA A VIN = 0.5 to VDD-0.5V Conditions
HV461
ENABLE and SYNC
Symbol VOUT(lo) VOUT(hi) tON tOFF SYNC(ON) Parameter SYNC output voltage low SYNC output voltage high ENABLE delay, on ENABLE delay, off 0 SYNC on lead time 4.5 5 VDD - 0.2 5 60 1 5.5 Min Typ Max 0.2 Unit V V s s ring cycle ms SYNCMODE=0 SYNCMODE=1 CSINE=0 RSYNC=154k CSYNC=47nF
CSINE=10nF
Conditions IOUT = 1mA sink IOUT = 1mA source
SYNC(OFF) tSYNC(rise) tSYNC(fall)
SYNC off delay SYNC rise time SYNC fall time
-250
0
+250 300 300
s ns ns
CL=50pF CL=50pF
PWM Controller
Symbol fPWM tPWMSYNC(OUT) tPWMSYNC(IN) fPWMSYNC(IN) VPWMSYNC(lo) IPWMSYNC Parameter PWM frequency PWM sync output pulse width PWM sync input pulse width PWM sync input frequency range PWM sync output low voltage PWM sync pull-up current 100 Min 21.25 127.5 30 25 25 150 0.2 Typ 25.00 150.0 50 Max 28.75 172.5 70 Unit kHz kHz ns ns kHz V A 0.2 VGD-0.2 50 50 23 48 73 12 72 22 62 0 0.95 0 0.95 25 50 75 20 80 30 70 100 1.00 100 1.00 27 52 77 28 88 38 78 1 150 1.05 150 1.05 V V ns ns % % % % % % % A ns s ns s IOUT=20mA sink IOUT=20mA source CL=4nF CL=4nF PWMin=0.625V PWMin=1.250V PWMin=1.875V VDCL=0V VDCL = 0.50V, PWMIN=0V VDCL = 0.50V, PWMIN=2.5V VDCL = 0.75V, PWMIN=0V VDCL = 0.75V, PWMIN=2.5V VDCL=0-1V CDB=0pF RDB=14k, CDB=100pF CDLY=0pF RDLY=14k, CDLY=100pF IOUT=1mA sink Conditions RPWM=500k RPWM=83k PWM Frequency
Switch Driver Outputs
VOUT(lo) VOUT(hi) tRISE tFALL Output voltage, low Output voltage, high Rise time Fall time Duty cycle
Timing
D
Dlimit
Duty cycle limit
IDCL tDB tDLY
VDCL input current Primary switch deadband Secondary switch delay
5
HV461
Switch Outputs
ENABLE 0 0 1 AMP 00 00 XX OFF XX XX XX SW1 Off Off Switching SW2 Off Off Switching SW3 Off Switching Switching SW4 Off Switching Switching
X = don't care, 00 = 01,10, or 11
Switch Timing
tDLY tDB tDB
SW1
On
Off
SW2
Off
On
SW3
On
Off
SW4
Off tDLY
On
Figure 1: Switch Timing Diagram
6
HV461
ENABLE and SYNC Timing: SYNCMODE=0
ENABLE
SYNC tON
SYNC(ON)
tOFF
SINE REF Decay time dependent on value of cap connected to SINEREF. ErrAmp Siezed Free Siezed
Figure 2: ENABLE and SYNC Timing - SYNCMODE=0 ENABLE and SYNC Timing: SYNCMODE=1
ENABLE
SYNC tON(delay)
SYNC(ON) SYNC(OFF)
sync at 0 or 180 Filtered SINE REF
ErrAmp
Siezed
Free
Siezed
Figure 3: ENABLE and SYNC Timing - SYNCMODE=1
7
HV461
AMP Timing
AMP AMP 00 AMP 00 AMP 00 AMP 00
SYNC tSYNC(delay)
SYNC(ON)
amplitude changes sync'd to zero crossings
SINE REF
Figure 4: AMP Timing
Typical Application
Figures 5 and 6 on pages 9 and 10 show the schematic of a typical 15 REN ring generator application. The basic design equations for elements connected to different pins are given in the Pin Descriptions Table beginning on page 11.
8
HV461
Block Diagram and Typical Application
CDC 100nF RDC1 RDC2 RDC3 RDC4 RFB1 30.1k
COM P2 D IFFAMPO DIFFAMPDIFFAMP+ Error Amplifier Differential Amplifier
RTSYNC and CTSYNC selected for desired ring sync lead time RTSYNC 3.3k
VREF2
RDC1 - RDC4 selected for the desired DC Offsets.
RCOMP 2.7k
CCOMP2 1nF
CSINE 47nF
VREF1
CTSYNC 100nF
TSYNC SYNC SINEREF DCREF1-3 Offset Mux VREF1 +1
sync clk Sine Wave freq
CCOMP1 47nF
COMP1
RFB2 4.02M RFB4 4.02M
Y1 19.6608MHz
XTAL
Sync OSC 20k 20k 20k 40k VREF1 Latch
Transparent Latch
freq am p offset 2 2
VREF1
2
20k 10k
RFB3 30.1k
VREF1
ringer output output reference
refer to power stage schematic
Synthesizer
reset 3
external ring frequency
RPLL PLL filter only required for 10k external ring frequency C PLL2 33F
VGD
FRING PLLFLT
Amplitude Mux +1 10k
PLL
PWM Controller
switch drivers PWM in
SW1 SW2 SW3 SW4
CPLL1 4.7F
FREQ0 FREQ1 FREQ2 AMP0 AMP1 OFF0 OFF1 ENABLE LE
referto power stage schematic
HV461FG
enable
curren t limit
CL+ CLCLCOMP VREF1 PWMSYNC R OSC
to host controller
osc
enable
Enable Control
overrange overcurrent pri deadband sec delay dutycyclelimit
VDC L TD B TD LY
R OSC 267k
VDD
RDCL1 100 k RDCL2 33 k
VDD
RDB 4.7 k CDB 120pF
VDD
VDD
SYNCMODE
RDLY 4.7 k
1.25V 2.50V
VREF1 VREF2
Precision Reference
undervoltage
Deglitcher
CFAULT
CDLY selected for desired Fault response time
CFAULT 10F
VDD
CDLY 120pF
CREF1 100nF
CREF2 100nF
VDD 10 A
Undervoltage D etector FAULT Boost C onverter AVD D DVD D VDR VGD AGND DD GN PGND
RFAULT 100 k
RESET
to host controller
CRESET 4.7F
LGD 330H
VD D
DGD 4148 CGD 6.8F
CDD1 10F
CDD2 100nF
QGD TN 2504
Figure 5: Block Diagram and Typical Application
9
HV461
Typical Power Stage for 15 REN Ring Generator
RCL4 6.8k
CLCOMP CL+
CCL2 68nF RCL1 10k CCL1 10nF
VREF1
PWR GND
CSW3a 100nF
SW3
TSW3 1:1
RCL3 39k
CL-
RSENSE 0.18 RCL2 10k CSW3b 100nF RSW3a 220 QSW2 IRF9540 CPRI3 100F RPR1 100k RPRI2 100k CPRI1 100F CPRI2 470nF DSW4 MMBD4148 CSW4a 100nF
SW4
CSW2 100nF
SW2
ZSW2a,b 12V
DSW3 MMBD4148 RSW3b 10k COUT1 1F ROUT1 1.0M ROUT2 1.0M Output Reference
RSW2a 220 DSW2 MMBD4148
RSW2b 100k
CPRI4 470nF
T MAIN 1:6.5:6.5
QSW3 IRFR320
CIN1 470F RSW1b 100k
CIN2 470nF QSW1 IRF530
52 H QSW4 IRFR320 RSW4a 10k
SW 1
CSW1 100nF
ZSWa,b 12V
RSW1a 220 DSW2 MMBD4148
COUT2 1F
Ringer Output
LIN Ferrite bead -48V
RSW4b 220 CSW4b 100nF
TSW4 1:1
Figure 6: Typical Power Stage for 15 REN Ring Generator
10
HV461
Pin Descriptions
DCREF2 DCREF1 VDCL AGND SINEREF COMP1 COMP2 DIFFAMPO DIFFAMPDIFFAMP+ CLCOMP CL-
DCREF3 VREF1 VREF2 AVDD TSYNC XTAL FRING PLLFLT ROSC RESET PWMSYNC CFAULT
HV461
CL+ DVDD VDR VGD PGND SW1 SW2 SW3 SW4 DGND TDB TDLY
Pin Name
1 2 3 4 5 6 DCREF3 VREF1 VREF2 AVDD TSYNC XTAL
Description
See DCREF1 and DCREF2 (pins 47 & 48). Outputs a 1.25V nominal reference voltage. Bypass with a 100nF capacitor to ground. Outputs a 2.50V nominal reference voltage. Bypass with a 100nF capacitor to ground. Supply for the analog section. 3.0 to 3.6V Must be from the same source as DVDD. Bypass with a 100nF capacitor to ground as close as possible to the IC. An RC network connected to this pin determines the SYNC pulse lead time (see SYNC pin 14). tLEAD = 0.48RC If unused, this pin should be left unconnected. A crystal from this pin to ground provides the frequency reference for the internal sine wave synthesizer. A 19.6608MHz baud rate crystal provides the 8 most common ring frequencies. The crystal is operated in the series mode. A loading capacitor is not necessary. See also FREQ0-2 (pins 21-23) and FRING (pin 7). Ring frequency is normally selected from the 8 built-in frequencies using control inputs FREQ0-2. Other arbitrary frequencies in the range of 12 to 70Hz may be obtained by applying an external signal to FRING. This external signal sets the ring frequency at a 1:1 ratio. The ring signal remains a sine wave, with amplitude and offset still controlled via AMPx and OFFx. The ring signal, while frequency locked to the FRING signal, is not phase-synchronized to it. This allows the ring signal to immediately start at 0 when enabled via ENABLE or AMP00. When unused, this input must be connected to VGD. Phase locked loop filter. An RC network connected to this pin stabilizes the PLL that locks on to the optional external ring frequency signal. (See FRING, pin 7) The RC network determines the lock time of the PLL. Due to the low frequencies involved, it may take a couple seconds to lock to the external signal. See the typical application schematic for typical values. When unused, this pin should be left unconnected. A resistor from this pin to VDD sets the PWM frequency. fPWM 12.5GHz / ROSC (valid for 20-150kHz) A capacitor from this pin to ground provides a power-on reset interval. It has an internal 10A pull-up to charge the external reset capacitor. Alternatively, an external logic-level or open-drain signal may be applied to implement the reset function. During the reset interval when VRESET<1.325V, the ringer output is disabled regardless of the state of the ENABLE input, allowing time for the host controller to assume control. Use a low leakage tantalum or ceramic capacitor. tRESET = 1.325V * CRESET / 10A This pin functions as both an input and an output. It is open-drain with an internal 100A pull-up. As an output, it provides a short, low-going pulse at the internal PWM frequency. As an input, it synchronizes internal PWM frequency to the externally applied signal, provided the external signal is at a higher frequency. The lowgoing applied sync pulse should be between 25ns and less than the PWM period in duration. The external source should be open drain. If the PWMSYNC pins of multiple HV461s are tied together, their PWM frequencies will be phase-locked to the HV461 with the highest free-running frequency. A maximum of 10 HV461s may be tied together. If unused, this pin should be left unconnected.
7
FRING
8
PLLFLT
9 10
ROSC RESET
11
PWMSYNC
SYNCMODE SYNC FAULT ENABLE OFF0 OFF1 AMP0 AMP1 FREQ0 FREQ1 FREQ2 LE
11
HV461 12 CFAULT A capacitor from this pin to ground sets the integration time of the FAULT detection circuitry. A larger capacitor provides less suseptability to transient problems, while a smaller capacitor provides quicker response. Values in the range of 1F to 100F are appropriate. If the FAULT output is not used, this pin should be grounded. See also FAULT (pin 15). With SYNCMODE low, ringer output ceases the instant ENABLE goes low. When high, ringer output ceases at the next ring signal phase crossing (0/180) after ENABLE goes low. Outputs a pulse indicating sine reference 0 and 180 phase crossing (not to be confused with zero-voltage crossing). The rising edge precedes phase crossing by a user-adjustable time period (see TSYNC pin 44). Falling edge coincides with sine reference phase crossing. SYNC is digitally derived, therefore phase shifts caused by the external filter capacitor at SINEREF will not be reflected at the SYNC output. Indicates abnormal operating conditions of output overcurrent, supply undervoltage (VDD & VGD), or PWM overrange (duty cycle limit - see VDCL, pin 3). Together, these 3 conditions catch most any problem. When an overcurrent or overrange condition exists for more than 8% of the time, this output becomes active. It is cleared when the problem occurs less than 2% of the time. Undervoltage conditions immediately activate the FAULT output. It is active low and open drain to allow wire-ORing. See CFAULT (pin 15) for additional information. Ringer output enable. Active high. When enabled, the ring signal always starts immediately at 0 degrees. If AMP00, SW1 and SW2 are held off when ENABLE=0 but SW3 and SW4 continue switching. If AMP=00, SW3 and SW4 are held off as well. When disabled, the error amplifier is set at unity gain to prevent saturation, reducing turn-on glitches when re-enabled. See SYNCMODE (pin 13) for additional information. Sets ring DC offset. Offset changes are effected at the next phase crossing (0/180) of the ring signal. Except for 00, offsets are set by the voltages at DCREF1-3. (OFF0 is LSB) Offset = 1/2 x Gain x (VDCREFx - VREF1) 00 = 0V 01 = DCREF1 10 = DCREF2 11 = DCREF3
13 14
SYNCMODE SYNC
15
FAULT
16
ENABLE
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
OFF0 OFF1 AMP0 AMP1 FREQ0 FREQ1 FREQ2 LE TDLY TDB DGND SW4 SW3 SW2 SW1 PGND VGD
Sets ring amplitude. Amplitude changes are effected at the next phase crossing (0/180) of the ring signal. Amplitudes, as a percentage of full scale, are: (AMP0 is LSB) Full scale amplitude = 0.707VRMS x Gain 00 = 0% 01 = 50% 10 = 75% 11 = 100% Sets ring frequency. Frequency changes are effected at the next phase crossing (0/180) of the ring signal. Frequencies when using a 19.6608MHz crystal are: (FREQ0 is LSB) 000 = 16.7Hz 100 = 33.3Hz 001 = 20Hz 101 = 40Hz 010 = 25Hz 110 = 50Hz 011 = 30Hz 111 = 60Hz
Latch enable. The latch gates control inputs FREQ0-2, AMP0-1, OFF0-1, and ENABLE. When LE is high, latch outputs follow inputs. On a low-going transition, outputs are latched. An RC network on this pin sets the primary to secondary switch delay. This prevents the secondary-side switches (SW3&4) from turning on prematurely. tDLY=0.48RC An RC network on this pin sets the deadband (break-before-make time) on the primary-side switches (SW1&2). Deadband prevents both switches from conducting simultaneously. tDB=0.48RC Digital ground. Connect to AGND and PGND close to the IC. Secondary-side switch driver output. Secondary-side switch driver output. Primary-side N-channel switch driver output. Primary-side P-channel switch driver output. Power ground. Connect to AGND and DGND close to the IC. Supply for the SW1-4 drivers. An external boost converter controlled by VDR provides 9.6V for driving the power stage MOSFETs. An undervoltage condition on this supply pin disables ringer output and activates the FAULT output. Gate drive for the external boost converter circuit. Outputs a fixed 50% duty cycle at the ringer PWM frequency (see ROSC, pin 9). Output voltage regulation is via burp-mode operation. This output is boostrapped to VGD, thus during startup VDR amplitude is VDD and after startup is VGD. (See VGD, pin 33) Supply for the digital section. 3.0V to 3.6V input. Undervoltage disables ringer output. Must be from the same source as AVDD. Bypass with a 100nF capacitor to ground as close as possible to the IC. An undervoltage condition on this supply pin disables ringer output and activates the FAULT output. Current limit amplifier non-inverting input. 12
34
VDR
35
DVDD
36
CL+
HV461 37 38 39 40 41 42 43 44 CLCLCOMP DIFFAMP+ DIFFAMPDIFFAMPO COMP2 COMP1 SINEREF Current limit amplifier inverting input. Current limit compensation. An RC network connected between this pin and CL- establishes current limit reaction time and stability. Differential amplifier non-inverting input. Differential amplifier inverting input. Differential amplifier output. The differential amplifier sets gain, establishing output amplitude and DC offset in conjunction with AMPx and OFFx. Gain = RFB2/RFB1 (RFB3=RFB1 and RFB4=RFB2, see schematic)
Error amplifier compensation. An RC network connected between these pins establishes loop stability. COMP1 is the error amp inverting input. COMP2 is the error amp output. Sine wave reference. Amplitude is 2VP-P nominal. Output impedance is approximately 16k. An external 33nF capacitor from this pin to ground should be employed to remove high frequency synthesizer ripple. Synthesizer ripple is at a frequency of 215 * fRING Analog ground. Connect to AGND and DGND close to the IC. Voltage applied to this pin sets the min/max duty cycle limits. If the PWM controller hits these limits, clipping of the ringer output will occur and the FAULT output will be activated. DMIN=0.4VDCL DMAX=1-0.4VDCL In conjunction with the OFFx control inputs, voltages applied to these inputs set the output DC offset. Output offset is the selected DCREFx voltage multiplied by gain. See also OFF0 & OFF1 (pins 17 & 18)
45 46 47 48
AGND VDCL DCREF1 DCREF2
10/3/03
13
2003 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94809 TEL: (408) 222-8888 / FAX: (408) 222-4895 www.supertex.com
Package Outlines 48-Lead TQFP Package (FG)
D, E
0.354 0.010 (8.992 0.254)
0.024 0.008 (0.610 0.2032)
L
0.354 0.010 (8.992 0.254) 0.275 0.004 (6.985 0.102)
B
0.008 0.003 (0.2032 0.0762)
D1, E1
Pin #1
0 - 7
0.275 0.004 (6.985 0.1016) 0.059 0.004 (1.4986 0.102)
A
A2
0.055 0.004 (1.397 0.102)
0.020 BSC (0.508)
0.039 TYP. (0.991)
Note: Circle (e.g. B ) indicates JEDEC Reference.
Measurement Legend =
Dimensions in Inches (Dimensions in Millimeters)
03/18/02
(c)2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com

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