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| HTG12G0 Microcontroller Features * * * * * * * * * * Operating voltage: 2.4V~3.3V Eight input lines Two output lines Five working registers RC oscillator for system clock Crystal oscillator for RTC and LCD clock 8Kx8 program ROM 156x4 data RAM 50x8 segment LCD driver, 1/5 bias, 1/8 duty 8-bit programmable timer with built-in frequency source * * * * * * * Internal timer overflow and RTC interrupt 16 kinds of programmable sound effects Halt function and wake-up feature reduce power consumption One-level subroutine nesting 8-bit table read instruction Up to 4.0s instruction cycle with 1.0MHz system clock at VDD=3V 95 powerful instructions General Description The HTG12G0 is a 4-bit single chip microcontroller specially designed for LCD product applications. It is ideally suited for applications requiring low power consumption, with many LCD segments such as calculator, scale, subsystem controller, hand-held LCD products and electronic appliances. 1 14th May '99 HTG12G0 Block Diagram Notes: ACC: Accumulator R0~R4: Working registers PP, PS: Input ports PA2: LCD on/off switch PC: Program counter PA0~PA1: Output ports PA3: ROM bank control bit 2 14th May '99 HTG12G0 Pad Assignment Chip size: 3070 x 4440 (m)2 * The IC substrate should be connected to VSS in the PCB layout artwork. 3 14th May '99 HTG12G0 Pad Coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Unit: m X -1403.50 -1403.50 -1403.50 -1403.50 -1304.00 -1304.00 -1358.50 -1409.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1403.50 -1409.50 -1342.00 -1071.50 -871.50 -640.00 -500.00 -360.00 -220.00 -80.00 60.00 200.00 340.00 1412.00 1412.00 1412.00 1412.00 1412.00 Y 2012.75 1872.75 1741.75 1610.75 1431.75 1276.25 1104.25 929.25 377.75 249.75 121.75 -6.25 -134.25 -262.25 -390.25 -518.25 -646.25 -774.25 -902.25 -1030.25 -1158.25 -1286.25 -1414.25 -1542.25 -1680.75 -1926.25 -1920.25 -1920.25 -1994.75 -1994.75 -1994.75 -1994.75 -1994.75 -1994.75 -1994.75 -1994.75 -2034.75 -1877.25 -1712.25 -1542.25 -1406.25 Pad No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 X 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1412.00 1071.50 490.00 358.00 228.00 105.00 -18.00 -141.00 -264.00 -387.00 -510.00 -633.00 -756.00 -879.00 -1002.00 -1129.50 Y -1270.25 -1134.25 -998.25 -862.25 -726.25 -590.25 -454.25 -318.25 -182.25 -46.25 89.75 225.75 361.75 497.75 633.75 769.75 905.75 1041.75 1177.75 1313.75 1449.75 1585.25 1720.75 1865.25 2034.75 2037.25 2034.75 2034.75 2034.75 2034.75 2034.75 2034.75 2034.75 2034.75 2034.75 2034.75 2034.75 2034.75 2034.75 2034.75 4 14th May '99 HTG12G0 Pad Description Pad No. 1~4, 36~81 5 6 7 8 9 10 19 20 26 11~18 21~24 25 27 28 29 30 31~34 Pad name SEG3~SEG0 SEG49~SEG4 BZ BZ VDD OSCI OSCO T512 TEST1 TEST2 T1D COM7~COM0 PS3~PS0 VSS PA1 PA0 XIN XOUT PP0~PP3 I/O O O I I O O I I O O I I O I O I Mask Option -- * -- -- Description LCD driver outputs for LCD panel segment Sound effect output Positive power supply An external resistor between OSCI and OSCO is needed for internal system clock. For test mode only TEST1 and TEST2 must be open when the HTG12G0 is in normal operation (with an internal pull high resistor) Output for LCD panel common plate 4-bit port for input only Negative power supply, GND 2-bit latch port for output only -- -- Pull-high or None ** -- CMOS or NMOS Open Drain -- Pull-high or None ** -- 32768Hz crystal oscillator for time base 4-bit port for input only Input for reset LSI inside Reset is active at logical low level 35 RES I *: 6 internal sources deriving from the system clock can be selected as sound effect clock by mask option. If Holtek's sound library is invoked, only 128K and 64K is accepted. **: Each bit of input ports PS, PP can be a trigger source of HALT interrupt. That can be specified by mask option. Absolute Maximum Ratings Supply Voltage .........................VSS-0.3V to 13V Input Voltage.......................VSS-0.3 to VDD+0.3 Operating Temperature................... 0C to 70C Storage Temperature................. -50C to 125C Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. 5 14th May '99 HTG12G0 D.C. Characteristics Symbol VDD IDD ISTB VIL1 VIH1 VIL2 VIH2 IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 RPH1 RPH2 Ta=25C Parameter VDD Operating Voltage Operating Current Standby Current (RTC OSC ON) and LCD ON Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Port A, BZ and BZ Output Sink Current Port A, BZ and BZ Output Source Current Segment 0~7 Output Sink Current Segment 0~7 Output Source Current Segment 8~49 Output Sink Current Segment 8~49 Output Source Current Common Output Sink Current Common Output Source Current Pull-high Resistance Pull-high Resistance -- 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V Test Conditions Conditions -- No load, fSYS=500kHz System halt PS, PP PS, PP RES RES VDD=3V, VOL=0.3V VDD=3V, VOH=2.7V VLCD=3V, VOL=0.3V VLCD=3V, VOH=2.7V VLCD=3V, VOL=0.3V VLCD=3V, VOH=2.7V VLCD=3V, VOL=0.3V VLCD=3V, VOH=2.7V PS, PP RES Min. 2.4 -- -- 0 2.1 0 2.5 1.5 -0.5 80 -50 40 -20 100 -100 15 100 Typ. -- 100 10 -- -- -- -- 3.0 -1.5 100 -70 60 -40 120 -130 -- -- Max. 3.3 500 20 0.6 3.0 0.6 3.0 -- -- -- -- -- -- -- -- 200 300 Uint V A A V V V V mA mA A A A A A A k k 6 14th May '99 HTG12G0 A.C. Characteristics Symbol fSYS fLCD tCOM tCY tRES fSOUND Ta=25C Parameter System Clock LCD Clock LCD Common Period Cycle Time Reset Pulse Width Sound Effect Clock Test Conditions VDD 3V 3V -- -- -- -- Min. 100 -- -- -- 5 -- Typ. -- 512 (1/fLCD)x8 4.0 -- 64 or 128* Max. 1000 -- -- -- -- -- Unit kHz Hz sec s Conditions R:620k~51k -- 1/8 duty fSYS=1.0MHz -- -- ms kHz *: Only these two clock signal frequencies are supported by Holtek sound library. 7 14th May '99 HTG12G0 Functional Description Program counter - PC The 12-bit program counter is controlled by PA3 which can change the ROM bank of the program memory. There are two program memory banks which are selected by PA3, each bank is 4KB ROM. The instruction"OUT PA, A" is used to change the value of PA3. Then, low or high 4K ROM is selected accordingly. All instructions are not effective on the crossing bank, unless the value of PA3 is changed in advance. The 12-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a max. of 4096 address. After accessing a memory word to fetch an instruction code, the contents of the program counter are incremented by one or two, then the program counter will point to the memory word containing the next instruction code. When executing the jump instruction (JMP, JNZ, JC, JTMR...), subroutine call, internal interrupt, RTC interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. Program memory - ROM The program memory is used to store program instruction which is to be executed. It is organized into 8192x8 bits and addressed by the program counter and PA3. Certain locations in bank 0 of the program memory are reserved for specific usage: * Location 0004H This area is reserved for TIMER interrupt service program. A timer interrupt results from TIMER overflow, if interrupt is enabled, the CPU begins execution at location 0004H. Mode Initial reset Internal interrupt External interrupt Jump, call instruction Conditional branch Return from subroutine 1 PA3 PA3 0 0 0 0 0 0 0 0 0 0 0 0 Program Counter PA3 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 PC2 PC1 PC0 0 1 0 PC2 PC2 S2 0 0 0 0 0 0 PA3 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PA3 PA3 @ S11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 S10 S9 S8 S7 S6 S5 S4 S3 PC1 PC0 PC1 PC0 S1 S0 Notes: PC11~PC0: Instruction code bits S11~S0: Stack register bits @: PC11 keeps current value PA3: Bank value bits 8 14th May '99 HTG12G0 * Location 0008H This area is reserved for RTC interrupt service program. * Location 0n00H~0nFFH (n=current number) and 0F00H~0FFFH. The last 256 bytes of each page in the program memory, addressed from 0n00H to 0nFFH and 0F00H to 0FFFH can be used as a look-up table. The instructions READ R4A, READ MR0A, READF R4A, READF MR0A can read the table and transfer the contents of the table to ACC and R4 or transfer to ACC and data memory addressed by register pair "R1, R0". These areas may function as a normal program memory depending on the requirements. Certain locations in bank 1 of the program memory are reserved for specific usage: * Location 1000H This area is reserved for the initialization program. After reset, the CPU always begins execution at location 1000H. * Location 1004H Program memory In the execution of an instruction, the program counter is added before the executing phase. So a careful manipulation of READ MR0A and READ R4A is needed in the page margin. Stack register This area is reserved for TIMER interrupt service program. A timer interrupt results from TIMER overflow, if interrupt is enabled, the CPU begins execution at location 1004H. * Location 1008H This area is reserved for RTC interrupt service program. * Location 1n00H~1nFFH (n=current number) and 1F00H~1FFFH. The last 256 bytes of each page in the program memory, addressed from 1n00H to 1nFFH and 1F00H to 1FFFH can be used as a look-up table. The instructions READ R4A, READ MR0A, READF R4A, READF MR0A can read the table and transfer the contents of the table to ACC and R4 or transfer to ACC and data memory addressed by register pair "R1, R0". These areas may function as a normal program memory depending on the requirements. The program memory (ROM) mapping is shown below: This is a special group of register which is used to save the contents of the program counter (PC) and is organized with 13 bitsx1 level. One bit is used to store the carry flag. An interrupt will force the contents of the PC and the carry flag onto the stack register. A subroutine call will also cause the PC contents to be pushed onto the stack; however the carry flag will not be stored. At the end of a subroutine or interrupt routine which is signaled by a return instruction, RET or RETI restores the program counter to its previous value from stack register. Executing "RETI" instruction will restore the carry flag from the stack register, but "RET" does not. 9 14th May '99 HTG12G0 Working registers - R0, R1, R2, R3, R4 Arithmetic and logic unit - ALU These five registers are usually used to store the frequently accessed data. The working register can be incremented (+1) or decremented (-1). The JNZ Rn,address (n=0,1,4) instruction makes very efficient use of the working register as program loop counter. The register pairs of R1, R0 and R3, R2 can also be used as the data memory pointer, when the data memory transfer instruction is executed. Data memory - RAM This circuit performs arithmetic and logic operation. The ALU provides the following functions: * * * * * Arithmetic operation (ADD, ADC, SUB, SBC, DAA) Logic operation (AND, OR, XOR) Rotation (RL, RR, RLC, RRC) Increment and Decrement (INC, DEC) Branch decision (JZ, JNZ, JC, JNC...) The data memory is a static RAM organized with 256 x 4 bits and is used to store temporary data and display data. All of the data memory locations are indirectly addressable through the register pair "R1, R0" or "R3, R2". There are two areas in the data memory, temporary data area and display data area. Access to temporary data memory is made through 00H~9BH address, and access to display data memory is made in 9CH~FFH address. When data is written in the display area, the LCD driver automatically reads it and generates an LCD driving signal. The ALU not only outputs the results of data operation but also sets the status of carry flag (C) in some instructions. Timer This is a programmable 8-bit count-up counter, internal frequency sources used to aid the user in counting and generating accurate time base. The Timer can be pre-set and read with software instructions. "TIMER XXH", "MOV TMRL, A" and "MOV TMRH, A" preload TIMER value. "MOV A, TMRL" and "MOV A, TMRH" read the contents of TIMER to ACC. The Timer is stopped by a hardware reset or "TIMER OFF" instruction and started by a TIMER ON instruction. Once the Timer is started, it will increment to its maximum count (FFH) and overflows to zero (00H). It will not stop until there is a "TIMER OFF" instruction or reset. When an overflow occurs, it will set the Timer Flag (TF) simultaneously. If interrupt is enabled, the Timer circuit supports TF for internal interrupt. The state of the TF can be tested with the conditional instruction JTMR. The Timer flag is cleared after the interrupt or JTMR instruction is executed. The frequency of the internal frequency source can be selected by mask option. 2n Where n=0,1,2......13 except 6, by mask option (the sixth stage is reserved for internal use). Frequency of TIMER clock = system clock Data memory Accumulator - ACC The register ACC plays the most important role in data manipulation and data transfer. It is not only one of the sources of input to the ALU but also the destination of the result due to ALU. Data transfer can be performed between ACC and other registers, data memory or I/O ports. 10 14th May '99 HTG12G0 RTC There is a real time clock (RTC) function implemented on the HTG12G0. The RTC function is used to generate an accurate time period. The clock source of the RTC circuit comes from the 32768Hz crystal oscillator. The block diagram is shown as follows: The interrupts are disabled by a hardware reset or a DI instruction. They remain disabled until the EI instruction is executed. Initial reset The HTG12G0 provides a RES pin for system initialization. Since the RES pin has internal pull high resistor, only an external 0.1~1 capacitor is needed. If the reset pulse is generated externally, it must be held low for at least 5 ms. When RES is active, the internal block will be initialized as shown below: The output of the RTC can be selected by mask option. Frequency of the RTC output = 256 2n n=0~7 PA3 and PC TIMER Timer flag SOUND Output port A LCD output 1000H Stop Reset (low) Sound off and one sing mode High (or floating state) Disabled High level The RTC output is used to generate an interrupt signal. Interrupt The HTG12G0 provides both TIMER and RTC interrupt modes. The DI and EI instructions are used to disable and enable the interrupts. When the RTC is activated during enable interrupt mode and the program is not within a CALL subroutine, this causes a subroutine call to location 8 and reset the interrupt latch. Likewise when the timer flag is set in the enable interrupt mode and the program is not within a CALL subroutine, the TIMER interrupt is activated. This cause a subroutine call to location 4 and resets the timer flag. If both TIMER and RTC interrupts arrive at the same time, the RTC will be serviced first. When running under a CALL subroutine or DI the interrupt acknowledge is on hold until the RET or EI instruction is invoked. The CALL instruction should not be used within an interrupt routine as unpredictable behaviors may occur. If within a CALL subroutine both TIMER and RTC interrupt occur, no matter what order they arrive in, the RTC interrupt will be serviced first after leaving the CALL subroutine. This also applies if the two interrupts arrive at the same time. BZ and BZ output HALT This is a special feature of HTG12G0. It will stop the chip's normal operation and reduces power consumption. When the instruction "HALT" is executed, then * System oscillator will be stopped * The contents of the on-chip RAM and registers remain unchanged * RTC oscillator still keeps running The system can escape HALT mode by ways of initial reset or RTC interrupt or wake-up from the following entry of program counter value. * Initial reset: 1000H Wake-up: next address of the HALT instruction When the halt status is terminated by the RTC interrupt, the following procedure takes place: * Case1: If the system is in an interrupt-dis- able state before entering the halt state: 11 14th May '99 HTG12G0 The system will be awakened and returns to the main program instruction following the HALT command. - The RTC interrupt will be held until the system receives an enable interrupt command by which the RTC interrupt will be serviced. * Case 2: If the system is in an interrupt enable state: - The RTC interrupt will awake the system and execute the RTC interrupt subroutine. - In the HALT mode, each bit of ports PP, PS, can be used as wake-up signal by mask option to wake-up the system. This signal is active in low-going transition. - LCD display memory The LCD display memory is embedded in the data memory. It can be read and written to as normal data memory. The figure shows the mapping between display memory and LCD pattern. To turn on/off the display, the programmer just writes 1/0 to the corresponding bit of the display memory. The LCD display module may have any form as long as the number of the common is no more than 8 and the segment is no more than 50. Sound effect HTG12G0 provides sound effect circuit which offers up to 16 sounds with 3 effects of tone, boom and noise. Holtek supports a sound library which have melody, alarm, machine gun shooting etc. Whenever the instruction "SOUND n" or "SOUND A" is executed, the specified sound begins playing. Whenever "SOUND OFF" is executed, it terminates the singing sound immediately. There are two singing modes, SONE mode and SLOOP mode, which is activated by "SOUND ONE" and "SOUND LOOP". In SONE mode, the sound that has been specified plays just once. In SLOOP mode, the sound being specified keeps playing repeatedly. Since sound 0~11 contain 32 notes, sound 12~15 contain 64 notes, the later possess better sound than the former. The frequency of the sound effect circuit can be selected by mask option. Frequency of sound effect circuit = Where m=0, 1, 2, 3, 4, 5 Holtek's sound library only supports sound clock frequency 128K or 64K. To utilize Holtek's sound library, select the proper system clock and mask option. system clock 2m LCD display memory LCD driver output The output number of the LCD driver is 50 x 8, directly driving a 1/8 duty cycle and 1/5 bias LCD. All LCD segments are at random during initial clear mode. The LCD has built-in bias voltage circuit. No external resistor is needed. The frequency of the LCD driving clock is fixed at about 512Hz. This is set by RTC OSC (32.768kHz). 12 14th May '99 HTG12G0 LCD driver output can be enabled or disabled by setting PA2 without the influence of the related memory condition. LCD driver output is enabled by setting PA2 as "1", and disabled by setting PA2 as "0". An example of an LCD driving waveform (1/8 duty and 1/5 bias) is shown below: Input ports - PS, PP Ports PS, PP are 4-bit input ports. These input ports are configured as shown below: All of these ports have internal pull-high resistor determined by mask option. Each bit of input ports PS, PP can be a trigger source of HALT interrupt. That is also specified by mask option. A transition from high to low will make HTG12G0 wake-up. Input ports PS, PP Oscillator circuit Only one external resistor is required for the HTG12G0 system clock. The system clock is also used as the sound effect clock, or internal frequency source of TIMER. Another crystal oscillator is needed to be used as the reference signal of LCD driving clock and RTC interrupt clock source. The HTG12G0 machine cycle consists of a sequence of 4 states numbered T1 to T4. Each state lasts for one oscillator period. The machine cycle is 4.0s, if the system frequency is up to 1.0MHz. RC and RTC oscillator 13 14th May '99 HTG12G0 Output port - PA Mask option Port A is a 2-bit output port (PA0~PA1), and configured as shown below: HTG12G0 provides six kinds of mask option for different applications. * Each bit of input ports PS, PP with pull-high resistor * Each bit of input ports PS, PP function as HALT wake-up trigger * Each bit of output port PA0~PA1 with CMOS or open drain NMOS * 8 bit programmable TIMER with internal fre- quency sources. There are 13 (the sixth stage is reserved for internal use) internal frequency sources which can be selected as a clocking signal. Output port PA The mask option available for selecting the output configuration is either normal CMOS output type or open drain NMOS output type. At the initial clear mode, the output ports are at high state (in CMOS output type) or at floating state (in NMOS output type). Note: PA3 controls the bit 12 of the program counter. When the instruction "OUT PA, A" is operated, port A is changed as well. PA2 controls the ON/OFF state of the LCD. Without the influence of the memory condition, "1" turns the LCD on, and "0" off. * Six kinds of sound clock frequencies: fSYS/2m, m= 0, 1, 2, 3, 4, 5 * There are eight kinds of RTC interrupt frequen- cies. RTC interrupt frequency= 256/2nHz, n=0~7 14 14th May '99 HTG12G0 Application Circuits R*: depends on the required system clock frequency (R=51k~620k, at VDD=3V) 15 14th May '99 HTG12G0 Instruction Set Summary Mnemonic Arithmetic ADD A,[R1R0] ADC A,[R1R0] SUB A,[R1R0] SBC A,[R1R0] ADD A,XH SUB A,XH DAA Logic Operation AND A,[R1R0] OR A,[R1R0] XOR A,[R1R0] AND [R1R0],A OR [R1R0],A XOR [R1R0],A AND A,XH OR A,XH XOR A,XH Increment and Decrement INC A INC Rn INC [R1R0] INC [R3R2] DEC A DEC Rn DEC [R1R0] DEC [R3R2] Data Move MOV A,Rn MOV Rn,A MOV A,[R1R0] MOV A,[R3R2] MOV [R1R0],A MOV [R3R2],A MOV A,XH MOV R1R0,XXH MOV R3R2,XXH MOV R4,XH Move register to ACC Move ACC to register Move data memory to ACC Move data memory to ACC Move ACC to data memory Move ACC to data memory Move immediate data to ACC Move immediate data to R1 and R0 Move immediate data to R3 and R2 Move immediate data to R4 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 2 2 2 -- -- -- -- -- -- -- -- -- -- Increment ACC Increment register Increment data memory Increment data memory Decrement ACC Decrement register Decrement data memory Decrement data memory 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 2 2 2 -- -- -- -- -- -- -- -- -- Add data memory to ACC Add data memory with carry to ACC Subtract data memory from ACC Subtract data memory from ACC with borrow Add immediate data to ACC Subtract immediate data from ACC Decimal adjust ACC for addition 1 1 1 1 2 2 1 1 1 1 1 2 2 1 Description Byte Cycle CF 16 14th May '99 HTG12G0 Mnemonic Rotate RL A RLC A RR A RRC A Input & Output IN A,Pi OUT PA,A Branch JMP addr JC addr JNC addr JTMR addr JAn addr JZ A,addr JNZ A,addr JNZ Rn,addr Subroutine CALL addr RET RETI Flag CLC STC EI DI NOP Timer TIMER XXH TIMER ON TIMER OFF MOV A,TMRL MOV A,TMRH MOV TMRL,A MOV TMRH,A Table Read READ R4A READ MR0A READF R4A READF MR0A Read ROM code of current page to R4 & ACC Read ROM code of current page to M(R1,R0), ACC Read ROM code of page F to R4 & ACC Read ROM code of page F to M(R1,R0), ACC 1 1 1 1 2 2 2 2 -- -- -- -- Set 8 bits immediate data to TIMER Set TIMER to start counting Set TIMER to stop counting Move low nibble of TIMER to ACC Move high nibble of TIMER to ACC Move ACC to low nibble of TIMER Move ACC to high nibble of TIMER 2 1 1 1 1 1 1 2 1 1 1 1 1 1 -- -- -- -- -- -- -- Clear carry flag Set carry flag Enable interrupt Disable interrupt No operation 1 1 1 1 1 1 1 1 1 1 0 1 -- -- -- Subroutine call Return from subroutine or interrupt Return from interrupt service routine 2 1 1 2 1 1 -- -- Jump unconditional Jump on carry=1 Jump on carry=0 Jump on timer out Jump on ACC bit n=1, n=0,1,2,3 Jump on ACC is zero Jump on ACC is not zero Jump on register Rn not zero, n=0,1,4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- -- -- -- -- -- -- -- Input port-i to ACC, port-i=PS, PP Output ACC to port-A 1 1 1 1 -- -- Rotate ACC left Rotate ACC left through the carry Rotate ACC right Rotate ACC right through the carry 1 1 1 1 1 1 1 1 Description Byte Cycle CF 17 14th May '99 HTG12G0 Mnemonic Sound Control SOUND n SOUND A SOUND ONE SOUND LOOP SOUND OFF Miscellaneous HALT Enter power down mode 2 2 -- Active SOUND channel n Active SOUND channel with Accumulator Turn on SOUND one mode Turn on SOUND repeat mode Turn off SOUND 2 1 1 1 1 2 1 1 1 1 -- -- -- -- -- Description Byte Cycle CF 18 14th May '99 HTG12G0 Instruction Definitions ADC A,[R1R0] Add data memory contents and carry to accumulator 00001000 The contents of the data memory addressed by the register pair "R1,R0" and the carry are added to the accumulator. Carry is affected. ACC ACC+M(R1,R0)+CF Add immediate data to accumulator 01000000 ACC ACC+XH Add data memory contents to accumulator 00001001 The contents of the data memory addressed by the register pair "R1,R0" is added to the accumulator. Carry is affected. ACC ACC+M(R1,R0) Logical AND immediate data to accumulator 01000010 0000dddd Data in the accumulator is logical AND with the immediate data specified by the code. ACC ACC "AND" XH Logical AND accumulator with data memory 00011010 Data in the accumulator is logical AND with the data memory addressed by the register pair "R1,R0". ACC ACC "AND" M(R1,R0) Logical AND data memory with accumulator 00011101 Data in the data memory addressed by the register pair "R1,R0" is logical AND with the accumulator M(R1,R0) M(R1,R0) "AND" ACC 0000dddd The specified data is added to the accumulator. Carry is affected. Machine code Description Operation ADD A,XH Machine code Description Operation ADD A,[R1R0] Machine code Description Operation AND A,XH Machine code Description Operation AND A,[R1R0] Machine code Description Operation AND [R1R0],A Machine code Description Operation 19 14th May '99 HTG12G0 CALL address Subroutine call 1111aaaa aaaaaaaa The program counter bits 0~11 are saved in the stack and the specified address loaded into the program counter. Stack PC+2 PC address Clear carry flag 00101010 The carry flag is reset to 0 CF 0 Decimal-Adjust accumulator 00110110 The accumulator value is adjusted to BCD (Binary Code Decimal), if the contents of the accumulator is greater than 9 or CF (Carry flag) is 1. If ACC>9 or CF=1 then ACC ACC+6, CF 1 else ACC ACC, CF CF Decrement accumulator 00111111 Data in the accumulator is decremented by 1. Carry flag is not affected. ACC ACC-1 Decrement register 0001nnn1 Data in the working register "Rn" is decremented by 1. Carry flag is not affected. Rn Rn-1; Rn=R0,R1,R2,R3,R4, for nnn=0,1,2,3,4 Decrement data memory 00001101 Data in the data memory specified by the register pair "R1,R0" is decremented by 1. Carry flag is not affected. M(R1,R0) M(R1,R0)-1 Machine code Description Operation CLC Machine code Description Operation DAA Machine code Description Operation DEC A Machine code Description Operation DEC Rn Machine code Description Operation DEC [R1R0] Machine code Description Operation 20 14th May '99 HTG12G0 DEC [R3R2] Decrement data memory 00001111 Data in the data memory specified by the register pair "R3,R2" is decremented by 1. Carry flag is not affected. M(R3,R2) M(R3,R2)-1 Disable interrupt 00101101 Internal time-out interrupt and external interrupt are disabled. Enable interrupt 00101100 Internal time-out interrupt and external interrupt are enabled. Halt system clock 00110111 PC PC+2 Input port to accumulator 00110011 00110100 PS PP 00111110 Turn off system clock, and enter power down mode. Machine code Description Operation DI Machine code Description EI Machine code Description HALT Machine code Description Operation IN A,Pi Machine code Description Operation INC A The data on port "Pi" is transferred to the accumulator. ACC Pi; Pi=PS or PP Increment accumulator 00110001 Data in the accumulator is incremented by 1. Carry flag is not affected. ACC ACC+1 Increment register 0001nnn0 Data in the working register "Rn" is incremented by 1. Carry flag is not affected. Rn Rn+1; Rn=R0~R4 for nnn=0~4 Increment data memory 00001100 Data in the data memory specified by the register pair "R1,R0" is incremented by 1. Carry flag is not affected. M(R1,R0) M(R1,R0)+1 Machine code Description Operation INC Rn Machine code Description Operation INC [R1R0] Machine code Description Operation 21 14th May '99 HTG12G0 INC [R3R2] Increment data memory 00001110 Data memory specified by the register pair "R3,R2" is incremented by 1. Carry flag is not affected. M(R3,R2) M(R3,R2)+1 Jump if accumulator bit n is set 100nnaaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if accumulator bit n is set to 1. PC (bit 0~10) address, if ACC bit n=1(n=0~3) PC PC+2, if ACC bit n=0 Jump if carry is set 11000aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the CF (Carry flag) is set to 1. PC (bit 0~10) address, if CF=1 PC PC+2, if CF=0 Direct jump 1110aaaa aaaaaaaa Bits 0~11 of the program counter are replaced with the directly-specified address. PC address Jump if carry is not set 11001aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address and bit 11 of the program counter is unaffected, if the CF (Carry flag) is set to 0. PC (bit 0~10) address, if CF=0 PC PC+2, if CF=1 Jump if accumulator is not 0 10111aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the accumulator is not 0. PC (bit 0~10) address, if ACC0 PC PC+2, if ACC=0 Machine code Description Operation JAn address Machine code Description Operation JC address Machine code Description Operation JMP address Machine code Description Operation JNC address Machine code Description Operation JNZ A,address Machine code Description Operation 22 14th May '99 HTG12G0 JNZ Rn,address Jump if register is not 0 10100aaa 10101aaa 11011aaa aaaaaaaa aaaaaaaa aaaaaaaa R0 R1 R4 Machine code Description Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the register is not 0. PC (bit 0~10) address, if Rn0; Rn=R0,R1,R4 PC PC+2, if Rn=0 Jump if time-out 11010aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the TF (Timer flag) is set to 1. PC (bit 0~10) address, if TF=1 PC PC+2, if TF=0 Jump if accumulator is 0 10110aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the accumulator is 0. PC (bit 0~10) address, if ACC=0 PC PC+2, if ACC0 Move register to accumulator 0010nnn1 Data in the working register "Rn" is moved to the accumulator. ACC Rn; Rn=R0~R4, for nnn=0~4 Move timer high nibble to accumulator 00111011 The high nibble data of the timer counter is loaded to the accumulator. ACC TIMER (high nibble) Move timer low nibble to accumulator 00111010 The low nibble data of the timer counter is loaded to the accumulator. ACC TIMER (low nibble) Operation JTMR address Machine code Description Operation JZ A,address Machine code Description Operation MOV A,Rn Machine code Description Operation MOV A,TMRH Machine code Description Operation MOV A,TMRL Machine code Description Operation 23 14th May '99 HTG12G0 MOV A,XH Move immediate data to accumulator 0111dddd The 4-bit data specified by the code is loaded to the accumulator. ACC XH Move data memory to accumulator 00000100 Data in the data memory specified by the register pair "R1,R0" is moved to the accumulator. ACC M(R1,R0) Move data memory to accumulator 00000110 Data in the data memory specified by the register pair "R3,R2" is moved to the accumulator. ACC M(R3,R2) Move immediate data to R1 and R0 0101dddd 0000dddd The 8-bit data specified by the code is loaded to the working registers R1 and R0, the high nibble of the data is loaded to R1, and the low nibble to R0. R1 XH (high nibble) R0 XH (low nibble) Move immediate data to R3 and R2 0110dddd 0000dddd The 8-bit data specified by the code is loaded to the working registers R3 and R2, the high nibble of the data is loaded to R3, and the low nibble to R2. R3 XH (high nibble) R2 XH (low nibble) Move immediate data to R4 01000110 R4 XH Move accumulator to register 0010nnn0 Data in the accumulator is moved to the working register "Rn". Rn ACC; Rn=R0~R4, for nnn=0~4 0000dddd The 4-bit data specified by the code is loaded to the working register R4. Machine code Description Operation MOV A,[R1R0] Machine code Description Operation MOV A,[R3R2] Machine code Description Operation MOV R1R0,XXH Machine code Description Operation MOV R3R2,XXH Machine code Description Operation MOV R4,XH Machine code Description Operation MOV Rn,A Machine code Description Operation 24 14th May '99 HTG12G0 MOV TMRH,A Move accumulator to timer high nibble 00111101 The contents of the accumulator is loaded to the high nibble of the timer counter. TIMER(high nibble) ACC Move accumulator to timer low nibble 00111100 The contents of the accumulator is loaded to the low nibble of the timer counter. TIMER(low nibble) ACC Move accumulator to data memory 00000101 Data in the accumulator is moved to the data memory specified by the register pair "R1,R0". M(R1,R0) ACC Move accumulator to data memory 00000111 Data in the accumulator is moved to the data memory specified by the register pair "R3,R2". M(R3,R2) ACC No operation 00111110 Do nothing, but one instruction cycle is delayed. Logical OR immediate data to accumulator 01000100 0000dddd Data in the accumulator is logical OR with the immediate data specified by the code. ACC ACC "OR" XH Logical OR accumulator with data memory 00011100 Data in the accumulator is logical OR with the data memory addressed by the register pair "R1,R0". ACC ACC "OR" M(R1,R0) Machine code Description Operation MOV TMRL,A Machine code Description Operation MOV [R1R0],A Machine code Description Operation MOV [R3R2],A Machine code Description Operation NOP Machine code Description OR A,XH Machine code Description Operation OR A,[R1R0] Machine code Description Operation 25 14th May '99 HTG12G0 OR [R1R0],A Logically OR data memory with accumulator 00011111 Data in the data memory addressed by the register pair "R1,R0" is logical OR with the accumulator. M(R1,R0) M(R1,R0) "OR" ACC Output accumulator data to port A 00110000 The data in the accumulator is transferred to port PA and latched. PA ACC Read ROM code of current page to M(R1,R0) and ACC 01001110 The 8-bit ROM code (current page) addressed by ACC and R4 is moved to the data memory M(R1,R0) and the accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to the accumulator. The address of the ROM code is specified below: Current page ROM code address bit 11~8 ACC ROM code address bit 7~4 R4 ROM code address bit 3~0 M(R1,R0) ROM code (high nibble) ACC ROM code (low nibble) Read ROM code of current page to R4 and accumulator 01001100 The 8-bit ROM code (current page) addressed by ACC and M(R1,R0) is moved to the working register R4 and the accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. The address of the ROM code is specified below: Current page ROM code address bit 11~8 ACC ROM code address bit 7~4 M(R1,R0) ROM code address bit 3~0 R4 ROM code (high nibble) ACC ROM code (low nibble) Machine code Description Operation OUT PA,A Machine code Description Operation READ MR0A Machine code Description Operation READ R4A Machine code Description Operation 26 14th May '99 HTG12G0 READF MR0A Read ROM Code of page F to M(R1,R0) and ACC 01001111 The 8-bit ROM code (page F) addressed by ACC and R4 is moved to the data memory M(R1,R0) and the accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to the accumulator. Page F ROM code address bit 11~8 are "1111" ACC ROM code address bit 7~4 R4 ROM code address bit 3~0 M(R1,R0) high nibble of ROM code (page F) ACC low nibble of ROM code (page F) Read ROM code of page F to R4 and accumulator 01001101 The 8-bit ROM code (page F) addressed by ACC and M(R1,R0) is moved to the working register R4 and the accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. Page F ROM code address bit 11~8 are "1111" ACC ROM code address bit 7~4 M(R1,R0) ROM code address bit 3~0 R4 high nibble of ROM code (page F) ACC low nibble of ROM code (page F) Return from subroutine or interrupt 00101110 The program counter bits 0~11 are restored from the stack. PC Stack Return from interrupt subroutine 00101111 The program counter bits 0~11 are restored from the stack. The carry flag is restored before entering the interrupt service routine. PC Stack CF CF (before interrupt service routine) Rotate accumulator left 00000001 The contents of the accumulator are rotated left by 1 bit. Bit 3 is rotated to both bit 0 and the carry flag. An+1 An, An: accumulator bit n (n=0,1,2) A0 A3 CF A3 Machine code Description Operation READF R4A Machine code Description Operation RET Machine code Description Operation RETI Machine code Description Operation RL A Machine code Description Operation 27 14th May '99 HTG12G0 RLC A Rotate accumulator left through carry 00000011 The contents of the accumulator are rotated left by 1 bit. Bit 3 replaces the carry bit, which is rotated into the bit 0 position. An+1 An, An: Accumulator bit n (n=0,1,2) A0 CF CF A3 Rotate accumulator right 00000000 The contents of the accumulator are rotated right by 1 bit. Bit 0 is rotated to both bit 3 and the carry flag. An An+1, An: Accumulator bit n (n=0,1,2) A3 A0 CF A0 Rotate accumulator right through carry 00000010 The contents of the accumulator are rotated right by 1 bit. Bit 0 replaces the carry bit, which is rotated into the bit 3 position. An An+1, An: Accumulator bit n (n=0,1,2) A3 CF CF A0 Subtract data memory contents and carry from ACC 00001010 The contents of the data memory addressed by the register pair "R1,R0" and the complement of the carry are subtracted from the accumulator. Carry is set if a borrow does not take place in subtraction; otherwise carry is cleared. ACC ACC+M(R1,R0)+CF Activate SOUND channel with accumulator 01001011 The activated sound begins playing in accordance with the contents of accumulator when the specified sound channel is matched. Turn on sound repeat cycle 01001001 The activated sound plays repeatedly. Machine code Description Operation RR A Machine code Description Operation RRC A Machine code Description Operation SBC A,[R1R0] Machine code Description Operation SOUND A Machine code Description SOUND LOOP Machine code Description 28 14th May '99 HTG12G0 SOUND OFF Turn off sound 01001010 The activated sound will terminate immediately. Turn on sound one cycle 01001000 The activated sound plays once. Activate SOUND channel n 01000101 0000nnnn The specified sound begins playing and overwrites the previous activated sound. (nnnn=0~15) Set carry flag 00101011 The carry flag is set to one. CF 1 Subtract immediate data from accumulator 01000001 0000dddd The specified data is subtracted from the accumulator. Carry is set if a borrow does not take place in subtraction; otherwise carry is cleared. ACC ACC+XH+1 Subtract data memory contents from accumulator 00001011 The contents of the data memory addressed by the register pair "R1,R0" is subtracted from the accumulator. Carry is set if a borrow does not take place in subtraction; otherwise carry is cleared. ACC ACC+M(R1,R0)+1 Set timer to stop counting 00111001 The timer stops counting, when the "TIMER OFF" instruction is executed. Set timer to start counting 00111000 The timer starts counting, when the "TIMER ON" instruction is executed. Machine code Description SOUND ONE Machine code Description SOUND n Machine code Description STC Machine code Description Operation SUB A,XH Machine code Description Operation SUB A,[R1R0] Machine code Description Operation TIMER OFF Machine code Description TIMER ON Machine code Description 29 14th May '99 HTG12G0 TIMER XXH Set immediate data to timer counter 01000111 TIMER XXH Logical XOR immediate data to accumulator 01000011 0000dddd Data in the accumulator is Exclusive-OR with the immediate data specified by the code. ACC ACC "XOR" XH Logical XOR accumulator with data memory 00011011 Data in the accumulator is Exclusive-OR with the data memory addressed by the register pair "R1,R0". ACC ACC "XOR" M(R1,R0) Logical XOR data memory with accumulator 00011110 Data in the data memory addressed by the register pair "R1,R0" is logical Exclusive-OR with the accumulator. M(R1,R0) M(R1,R0) "XOR" ACC dddddddd The 8-bit data specified by the code is loaded to the timer counter. Machine code Description Operation XOR A,XH Machine code Description Operation XOR A,[R1R0] Machine code Description Operation XOR [R1R0],A Machine code Description Operation 30 14th May '99 HTG12G0 Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Microelectronics Enterprises Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright (c) 1999 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. 31 14th May '99 |
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