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HIP1015, HIP1016
Data Sheet March 2003 FN4778.5
Power Distribution Controllers
The HIP1015 and HIP1016 are hot swap power controllers. The HIP1015 is targeted for a +12V bus whereas the HIP1016 is targeted for +5V applications. Each has an undervoltage (UV) monitoring and reporting with a threshold level ~17% lower than the nominal +12V and +5V. The HIP1015 has an integrated charge pump allowing control of up to a +12V bus using an external N-channel MOSFET. The HIP1016 can also be used to control much higher positive or negative voltages in a low side controller configuration. Both the HIP1015 and HIP1016 feature programmable Overcurrent (OC) detection, current limiting regulation with time delay to latch off and soft start.
Features
* HOT SWAP Single Power Distribution Control (HIP1015 for 12V, HIP1016 for 5V and Low Side Switch) * Undervoltage Monitoring and Notification * Overcurrent Fault Isolation * Programmable Current Regulation Level * Programmable Current Limit Time to Latch-Off * Rail to Rail Common Mode Input Voltage Range (HIP1015) * Internal Charge Pump Allows the use of N-channel MOSFET (HIP1015) * Undervoltage and Overcurrent Latch Indicators * Adjustable Turn-On Ramp * Protection During Turn On * Two Levels of Overcurrent Detection Provide Fast Response to Varying Fault Conditions * Less Than 1s Response Time to Dead Short
Ordering Information
PART NUMBER HIP1015CB HIP1015CB-T HIP1016CB HIP1016CB-T TEMP. RANGE (oC) 0 to 85 0 to 85 0 to 85 0 to 85 PACKAGE 8 Lead SOIC 8 Lead SOIC Tape and Reel 8 Lead SOIC 8 Lead SOIC Tape and Reel PKG. NO. M8.15 M8.15 M8.15 M8.15
Applications
* Power Distribution Control * Hot Plug Components and Circuitry * High Side Low Voltage (< +15V) Switching * Low Side High Voltage (> +15V, Negative V) Switch
Pinout
HIP1015, HIP1016 (SOIC) TOP VIEW
ISET ISEN GATE VSS 1 2 3 4 8 7 6 5 PWRON PGOOD CTIM VDD
Application One - High Side Controller
+ LOAD -
Application Two - Low Side Controller
+VBUS LOAD
1 2 3 4 HIP1015 HIP1016
8 PWRON 7 6 OC 5 HIP1016 PWRON 5 6 7 8 PGOOD 4 3 2 1
12V REG +12V OC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HIP1015,HIP1016 Simplified Block Diagram
VDD
+
+ ISET 8V POR QN Q R R S PWRON
+ + UV VREF ENABLE
ISEN
12V PGOOD
10A CLIM OC +
-
7.5k + CTIM + 1.86V 20A RISING EDGE PULSE
GATE 10A
FALLING EDGE DELAY 18V ENABLE
+ WOCLIM
-
-
-
VSS
18V
VDD
Pin Descriptions
PIN # 1 SYMBOL ISET FUNCTION Current Set DESCRIPTION Connect to the low side of the current sense resistor through the current limiting set resistor. This pin functions as the current limit programming pin. Connect to the more positive end of sense resistor to measure the voltage drop across this resistor Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +5V (HIP1015) and to VDD (HIP1016) by a 10A current source.
2
ISEN
Current Sense
3
GATE
External FET Gate Drive Pin
4 5
VSS VDD CTIM
Chip Return Chip Supply 12V chip supply. This can be either connected directly to the +12V rail supplying the switched load voltage or to a dedicated VSS +12V supply. Connect a capacitor from this pin to ground. This capacitor determines the time delay between an overcurrent event and chip output shutdown (current limit time-out). The duration of current limit time-out (in seconds) = 93k x CTIM (Farads). Indicates that the voltage on ISEN pin is within specification. PGOOD is driven by an open drain N-Channel MOSFET and is pulled low when the output is not within specification. PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven high or is open. After a current limit time out, the chip is reset by a low level signal applied to this pin. This input has 20A pull up capability
6
Current Limit Timing Capacitor
7
PGOOD
Power Good Indicator
8
PWRON
Power ON
2
HIP1015,HIP1016
Absolute Maximum Ratings TA = 25oC
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+8V ISEN, PGOOD, PWRON, CTIM, ISET. . . . . . . . -0.3V to VDD + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . +12v+/-15% Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief, #TB379.1 for details.) 2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER ISET Current Source Current Limit Amp Offset Voltage
VDD = 12V, TA = TJ = 0oC to 85oC, Unless Otherwise Specified SYMBOL IISET VISET - VISEN CTIM_Vth pd_woc_amp pd_oc_amp IGATE OC_GATE_I_4V WOC_GATE_I_4V 12VUV_VTH 12VUV_VTH_dis 12VG 5VUV_VTH 5VUV_VTH_dis 5VG IVDD VDD_POR_L2H VDD_POR_H2L VDD_POR_HYS PWRN_V PWR_Vth PWR_hys PWRN_I CTIM_ichg0 VCTIM = 0V VDD Low to High VDD High to Low VDD_POR_L2H - VDD_POR_H2L PWRON Pin Open GATE Voltage GATE Voltage CTIM Voltage VGATE to 10.8V VGATE to 10.8V VGATE to = 6V Overcurrent Severe Overcurrent 8.4 45 0.5 9.2 TEST CONDITIONS MIN 18.5 -6 1.3 TYP 20 0 1.8 100 600 10 75 0.8 9.6 1.5 10 11.6 MAX UNITS 21.5 6 2.3 A mV V ns ns A mA A V V 4.5 V V V 5 9 8.7 0.6 2.0 250 25 23 23 88 170 V mA V V V V V mV A A mA A A
Current Limit Time-Out Threshold Voltage GATE Response Time To Severe Overcurrent GATE Response Time to Overcurrent GATE Turn-On Current GATE Pull down Current GATE Pull down Current HIP1015 Undervoltage Threshold HIP1015 Undervoltage Disabled HIP1015 GATE High Voltage HIP1016 Undervoltage Threshold HIP1016 Undervoltage Disabled HIP1016 GATE High Voltage VDD Supply Current VDD POR Rising Threshold VDD POR Falling Threshold VDD POR Threshold Hysteresis PWRON Pull-up Voltage PWRON Rising Threshold PWRON Hysteresis PWRON Pull-Up Current CTIM Charging Current CTIM Fault pull-up Current HIP1015 ISEN Current HIP1016 ISEN Current
VDD+1.9V VDD+2.5V VDD+4.5V 4.0 VDD-3V VDD-1.5V 7.8 7.5 0.1 2.7 1.4 130 9 16 16 VDD+5V 4.35 VDD-2.5V VDD 3 8.4 8.1 0.3 3.2 1.7 170 17 20 20 72 145
ISEN_5V_I ISEN_5V_I
41 100
3
HIP1015,HIP1016 HIP1015, HIP1016 Description and Operation
The HIP1015 and HIP1016 are single power supply distribution controllers for generic hot swap applications. The HIP1015 is targeted for +12V switching applications whereas the HIP1016 is targeted for +5V applications as each has an undervoltage (UV) threshold level ~17% lower than the nominal +12V and +5V, respectively. The HIP1015 and HIP1016 features include a highly accurate programmable Overcurrent (OC) detecting comparator, programmable current limiting regulation with programmable time delay to latch off and programmable soft start turn-on ramp all set with a minimum of external passive components. The HIP1015 and HIP1016 also include severe overcurrent protection that immediately shuts down the MOSFET switch should the load current cause the OC voltage threshold to exceed the programmed OC level by 150mV. Additionally the HIP1015 and HIP1016 have an UV indicator and an OC latch indicator. Upon initial power up, the HIP1015 or HIP1016 can either isolate the voltage supply from the load by holding the external N-Channel MOSFET switch off or apply the supply rail voltage directly to the load for true hot swap capability. In either case the HIP1015 and HIP1016 turns on in a soft start mode protecting the supply rail from sudden in-rush current. The PWRON pin must be pulled low for the device to isolate the power supply from the load by holding the external N-channel MOSFET off, otherwise with the PWRON pin held high or floating the HIP1015 and HIP1016 will be in true hot swap mode. At turn-on, the gate capacitor of the external N-Channel MOSFET is charged with a 10A current source resulting in a programmable ramp (soft start turn-on). The internal HIP1015 charge pump supplies the gate drive for the 12V supply switch driving that gate to VDD +5V. The HIP1016 gate drive is limited to the chip bias voltage. Load current passes through the external current sense resistor. When the voltage across the sense resistor exceeds the user programmed Overcurrent voltage threshold value, (See Table 1 for RISET programming resistor value and resulting nominal overcurrent threshold voltage, VOC) the controller enters current regulation. At this time, the time-out capacitor, on CTIM pin starts charging with a 20mA current source and the controller enters the current limit time to latch-off period. The length of the current limit time to latch-off period is set by the single external capacitor (See Table 2 for CTIM capacitor value and resulting nominal current limited time out to latch-off period.) placed from the CTIM pin (pin 6) to ground. The programmed current level is held until either the OC event passes or the time out period expires. If the former is the case then the N-Channel MOSFET is fully enhanced and the CTIM capacitor is discharged. Once CTIM charges to 1.87V, signaling that the time out period has expired an internal latch is set whereby the FET gate is quickly pulled to 0V turning off the NChannel MOSFET switch, isolating the faulty load.
TABLE 1. RISET RESISTOR 10k 4.99k 2.5k 750 NOTE: Nominal Vth = RISET x 20A. TABLE 2. CTIM CAPACITOR 0.022F 0.047F 0.1F NOMINAL CURRENT LIMITED PERIOD 2ms 4.4ms 9.3ms NOMINAL OC VTH 200mV 100mV 50mV 15mV
NOTE: Nominal time-out period in seconds = CTIM x 93k.
The HIP1015 and HIP1016 respond to a severe overcurrent load (defined as a voltage across the sense resistor >150mV over the OC Vth set point) by immediately, driving the NChannel MOSFET gate to 0V in less than 1s. The gate voltage is then slowly ramped up turning on the N-Channel MOSFET to the programmed current limit level, this is the start of the time out period. Upon an UV condition the PGOOD signal will pull low when tied high through a resistor to the logic supply. This pin is an UV fault indicator. For an OC latch off indication, monitor CTIM, pin 6. This pin will rise rapidly from 1.9V to 12V once the time out period expires. The HIP1015 and HIP1016 are reset after an OC latch-off condition by a low level on the PWRON pin and is turned on by the PWRON pin being driven high.
Application Considerations
During the Time-Out Delay Period with the HIP1015 and HIP1016 in current limit mode, the VGS of the external NChannel MOSFETs is reduced driving the N-Channel MOSFET switch into a high rDS(ON) state. Thus avoid extended time out periods as the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET manufacturers data sheet for SOA information. With the high levels of inrush current e.g., highly capacitive loads and motor start up currents, choosing the current limiting level is crucial to provide both protection and still allow for this inrush current without latching off. Consider this in addition to the time out delay when choosing MOSFETs for your design.
4
HIP1015,HIP1016
Physical layout of RSENSE resistor is critical to avoid the possibility of false overcurrent occurrences. Ideally trace routing between the RSENSE resistors and the HIP1015 and HIP1016 is direct and as short as possible with zero current in the sense lines. (See Figure 1.)
Biasing the HIP1016
Table 3 gives typical component values for biasing the HIP1016 in a 48V application. The formulas and calculations deriving these values are also shown below.
TABLE 3. TYPICAL VALUES FOR A -48V HOT SWAP APPLICATION
CORRECT
INCORRECT
SYMBOL RCL DD1 1.58k, 1W
PARAMETER
12V Zener Diode, 50mA Reverse Current
TO ISEN AND RISET
CURRENT SENSE RESISTOR
When using the HIP1016 to control -48V, a Zener diode may be used to provide the +12V bias to the chip. If a Zener is used then a current limit resistor should also be used. Several items must be taken into account when choosing values for the current limit resistor (RCL) and Zener Diode (DD1): * The variation of the VBUS (in this case, -48V)
FIGURE 1. SENSE RESISTOR PCB LAYOUT
* The chip supply current needs for all functional conditions * The power rating of RCL. * The current rating of DD1
Using the HIP1016 as a -48V Low Side Hot Swap Power Controller
To supply the required VDD, it is necessary to maintain the chip supply 12V above the -48V bus. This may be accomplished with a +12V Regulator between the voltage rail and pin 5 (VDD). By using a Regulator, the designer may ignore the bus voltage variations. However, a low-cost alternative is to use a Zener diode (See Figure 2 for typical 5A load control ) this option is detailed below. Note that in this configuration the PGOOD feature (pin 7) is not operational.
HUF7554S3S LOAD
Formulas
1. Sizing RCL: RCL = (VBUS,MIN - 12)/ICHIP 2. Power Rating of RCL: PRCL = IC(VBUS,MAX - 12) 3. DD1 Current Rating: IDD1 = (VBUS,MAX - 12)/RCL Example: A typical -48V supply may vary from -36 to -72V. Therefore, VBUS,MAX = -72V VBUS,MIN = -36V ICHIP = 15mA (max) Sizing RCL: RCL = (VBUS,MIN - 12)/IC RCL = (36 - 12)/0.015 RCL = 1.6k [Typical Value = 1.58k] Power Rating of RCL: PRCL = IC(VBUS,MAX - 12) PRCL = (0.015)(72 - 12) PRCL = 0.9W [Typical Value = 1W] DD1 Current Rating: IDD1 = (VBUS,MAX - 12)/RCL IDD1 = (72 - 12)/1.58k IDD1 = 38mA [Typical Value = 12V rating, 50mA reverse current]
0.005 1% 1.47k 1%
0.001F 2k
RCL 1.58k 1W
0.01F
4 5
HIP1016
3 6
NC
2 7
1 8
DD1
12V
0.047F
PWRON
VBUS
-48V
FIGURE 2.
5
HIP1015,HIP1016 Typical Performance Curves
5.0 4.5 SUPPLY CURRENT (mA) ISET CURRENT (A) 0 10 20 30 40 50 60 70 80 90 100 20.2 20.0 19.8 19.6
4.0 3.5 3.0 2.5 2.0 TEMPERATURE (oC)
19.4 19.2 19.0 0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE (oC)
FIGURE 3. VDD BIAS CURRENT
FIGURE 4. ISET SOURCE CURRENT
20.5 CTIM = 0V, CURRENT SOURCE (mA) CTIM OC VOLTAGE THRESHOLD (V) 20.32 CTIM - 0V
1.89 1.88 1.87 1.86 1.85 1.84 1.83 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (oC) TEMPERATURE (oC)
20.16 20.0 19.82 19.66 19.5
FIGURE 5. CTIM CURRENT SOURCE
9.67 HIP1015, 12V UV THRESHOLD (V) HIP1015
FIGURE 6. CTIM OC VOLTAGE THRESHOLD
4.5 HIP1016, 5V UV THRESHOLD (V) GATE CHARGE CURRENT (A)
10.2 10.1 10.0 9.9 9.8 9.7 9.6 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (oC)
9.66
4.25
HIP1016 9.65 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (oC) 4.0 100
FIGURE 7. UV THRESHOLD
FIGURE 8. GATE CHARGE CURRENT
6
HIP1015,HIP1016 Typical Performance Curves
17.200 HIP1015, GATE DRIVE (V) 17.183 17.166 17.150 17.133 17.116
(Continued)
12.00 11.99 11.98 11.97 11.96 11.95 11.94 90 100 HIP1016, GATE DRIVE (V)
8.5 VDD LO TO HI
POWER ON RESET (V)
8.4
8.3
8.2
8.1
VDD HI TO LO
17.100 0 10 20 30 40 50 60 70 80 TEMPERATURE (oC)
8.0 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (oC)
FIGURE 9. GATE DRIVE VOLTAGE, VDD = 12V
FIGURE 10. POWER ON RESET VOLTAGE THRESHOLD
VGATE 2V/DIV VOUT 1V/DIV
IOUT 2A/DIV
VGATE 5V/DIV
IOUT 2A/DIV
VOUT 5V/DIV
PWRON 5V/DIV 0V
PWRON 5V/DIV
0V
2ms/DIV
1.0ms/DIV
FIGURE 11.
HIP1015 HIGH SIDE +12V TURN-ON
FIGURE 12.
HIP1016 HIGH SIDE +5V TURN-ON
VDRAIN 10V/DIV +50V
IOUT 1A/DIV
VDRAIN 10V/DIV
0V
IOUT 1A/DIV
VGATE 5V/DIV VGATE 5V/DIV
PWRON 5V/DIV EN 5V/DIV
0V
0V
0V
-50V
5ms/DIV
5ms/DIV FIGURE 14. -50V LOW SIDE SWITCHING CGATE = 1000pF
FIGURE 13.
+50V LOW SIDE SWITCHING CGATE = 100pF
7
HIP1015,HIP1016 Typical Performance Curves
+350V VDRAIN 50V/DIV IOUT 1A/DIV VDRAIN 50V/DIV
(Continued)
+350V IOUT 1A/DIV
VGATE 5V/DIV
VGATE 5V/DIV
PWRON 5V/DIV
PWRON 5V/DIV
0V
0V
2ms/DIV FIGURE 15. +350V LOW SIDE SWITCHING CGATE = 100pF FIGURE 16.
2ms/DIV +350V LOW SIDE SWITCHING CGATE = 1000pF
8
HIP1015,HIP1016 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E

A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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