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HCF4099B
8 BIT ADDRESSABLE LATCH
s
s
s s
s
s
s s
SERIAL DATA INPUT - ACTIVE PARALLEL OUTPUT STORAGE REGISTER CAPABILITY MASTER CLEAR CAN FUNCTION AS DEMULTIPLEXER QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF4099BEY HCF4099BM1 T&R HCF4099M013TR
DESCRIPTION HCF4099B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4099B, an 8-bit addressable latch, is a serial-input, parallel output storage register that can perform a variety of functions. Data is input to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When
WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer ; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.
PIN CONNECTION
October 2002
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HCF4099B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 5, 6, 7 9, 10, 11, 12, 13, 14, 15, 1 3 2 4 8 16 SYMBOL A0 to A2 Q0 to Q7 DATA RESET WRITE DISABLE VSS VDD NAME AND FUNCTION Address Inputs Latch Outputs Data Inputs Reset Input Write Disable Input Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
TRUTH TABLE
SELECT INPUTS LATCH ADDRESSED C L L L L H H H H INPUTS WRITE DISABLE L L H H RESET L H L H B L L H H L L H H OUTPUTS OF ADDRESSED LATCH D Qi0 D L A L H L H L H L H EACH OTHER OUTPUT Qi0 Qi0 L L Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
FUNCTION ADDRESSABLE LATCH MEMORY DEMULTIPLEXER CLEAR ALL BITS TO "0"
D: The level at the data input ; Qi0 The level before the indicated steady state input conditions were established, (i=0, 1,...7)
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LOGIC DIAGRAM
TIMING CHART
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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DC SPECIFICATIONS
Test Conditions Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/18.5 0.5/4.5 9/1 1.5/18.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) IO VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
mA
mA
II
any input any input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 See Timing Chart (1) Min. Value (*) Typ. 200 75 50 200 80 60 225 100 75 175 80 65 100 50 40 100 50 40 200 100 65 75 40 25 50 25 20 75 40 25 Max. 400 150 100 400 160 120 450 200 150 350 160 130 200 100 80 ns Unit
tPLH tPHL Propagation Delay Time (Data to Output) tPLH tPHL Propagation Delay Time (Write Disable to Output) tPLH tPHL Propagation Delay Time (Address to Output) tPHL Propagation Delay Time (Reset to Output)
(2)
ns
(9)
ns
(3)
ns
tTHL tTLH Transition Time (any output) tW Pulse WIdth (Data)
ns
(4)
tW
Pulse WIdth (Address)
(8)
tW
Pulse WIdth (Reset)
(5)
tsetup
Setup Time (Data to Write Disable) Hold Time (Data to Write Disable)
(6)
thold
(7)
200 100 80 400 200 125 150 75 50 100 50 35 150 75 50
ns
ns
ns
ns
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
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HCF4099B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 2 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : MINIMUM PULSE WIDTH, SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 4 : MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle)
WAVEFORM 5 : SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 6 : INPUT WAVEFORMS (f=1MHz; 50% duty cycle)
TIPICAL APPLICATIONS
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TIPICAL APPLICATIONS
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Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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HCF4099B
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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