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Description
GM3255 products are 280 kHz switching regulators with a high efficiency, 1.5 A integrated switch. These parts operate over a wide input voltage range, from 2.7 V to 30 V. The flexibility of the design allows the chips to operate in most power supply configurations, including boost, flyback, forward, inverting, and SEPIC. The ICs utilize current mode architecture, which allows excellent load and line regulation, as well as a practical means for limiting current. Combining high frequency operation with a highly integrated regulator circuit results in an extremely compact power supply solution. The circuit design includes provisions for features such as frequency synchronization, shutdown, and feedback controls for either positive or negative voltage regulation.
Features
Integrated Power Switch: 1.5 A Guaranteed Input Voltage Range: 2.7 V to 30 V High Frequency Allows for Small Components Minimum External Components Easy External Synchronization Built in Overcurrent Protection Frequency Foldback Reduces Component Stress During an Overcurrent Condition Thermal Shutdown with Hysteresis Regulates Either Positive or Negative Output Voltages Shut Down Current: 50 A Maximum Wide Temperature Range Commercial Commercial Grade : 0 to 70C (GM3255)
Application
Boost Regulators CCFL Backlight Driver
Multiple Output Flyback Supplies Inverting Supplies TFT LCD Bias Supplies
Laptop Computer Supplies
TYPICAL APPLICATION CIRCUITS
R2 3.72K
GM3255
1 VC VSW 8 PGND 7 6 L1 22H +C2 22F 2 FB 3
D1 MBRS120T3
VOUT 5V
Test AGND
SS 3.3V R1 5k
4 SS
VCC 5
+ C3 22F
R3 1.28k
www.gammamicro.com
GM3255 V0.11
1
C1 0.01F
MARKING INFORMATION & PIN CONFIGURATIONS (TOP VIEW) SOP-8 & NSOP-8
PGND VSW AGND VCC
8765
GM3255 AYWW
12
VC FB
A = Assembly Location Y = Year W W = Work Week SS Test
34
Ordering Number GM3255S8T GM3255S8R GM3255NS8T GM3255NS8R
Package SOP - 8 SOP - 8 NSOP - 8 NSOP - 8
Shipping 100 Units / Tube 2,500 Units / Tape & Reel 100 Units / Tube 2,500 Units / Tape & Reel
* For detail Ordering Number identification, please see last page.
PIN DESCRIPTION
PIN NUMBER
1
PIN SYMBOL
VC
FUNCTION
Loop compensation pin. The VC pin is the output of the error amplifier and is used for loop compensation, current limit and start. Loop compensation can be implemented by a simple RC network as shown in the application diagram on page 2 as R1 and C1. Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to 1.276V. When the voltage at this pin falls below 0.4 V, chip switching frequency reduces to 20% of the nominal frequency. These pins are connected to internal test logic and should either be left floating or tied to ground. Connection to a voltage between 9.5V and 15V shuts down the internal oscillator and leaves the power switch running. Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly twice the base frequency. A TTL low shut the part down and put it into low current mode. If synchronization is not used, this pin should be either tied high or left floating for normal operation. Input power supply pin. This pin supplies power to the part and should have a bypass capacitor connected to AGND. Analog ground. This pin provides a clean ground for the controller circuitry ans should not be in the path of large currents. The output voltage sensing resistors should be connected to the IC substrate. Power ground. This pin is the ground connection for the emitter of the power switching transistor. Connection to a good ground plane is essential. High current switch pin. This pin connects internally to the collector of the power switch. The open voltage across the power switch can be as high as 40V. T minimize radiation, o use a trace as short as practical.
2
FB
3
Test
4
SS
5
VCC
6
AGND
7
PGND VSW
8
ABSOLUTE MAXIMUM RATINGS
PARAMETER VALUE
45 165 -40 to +150 -65 to +150 230 1.2
UNITS
C / W C / W C C C kV
GM3255
2
Package Thermal Resistance Junction-to-Case, RqJC junction-to-Ambient, RqJC Junction Temperature Range, TJ Storage Temperature Range, TSTG Lead Temperature (Peak) (reflow - soldering 60 sec. maximum above 183C) ESD, Human Body Model
* The maximum package power dissipation must be observed.
MAXIMUM RATINGS:
PIN NAME
IC Power Input Shutdown / Sync Loop Compensation Voltage Feedback Input Test Pin Power Ground Analog Ground Switch Input
PIN SYMBOL
VCC SS VC FB Test PGND AGND VSW
VMAX
30 V 30 V 6V 10 V 6V 0.3 V 0V 40 V
VMIN
-0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V 0V -0.3 V
ISOURCE
N/A 1 mA 10 mA 1 mA 1 mA 4A N/A 10 mA
ISINK
200 mA 1 mA 10 mA 1 mA 1.0 mA 10 mA 10 mA 3A
BLOCK DIAGRAM
VCC Shutdown Delay Timer SS Sync 2.0V Regulator
Thermal Shutdown Oscillator Frequency Shift 5 :1 Slope Compensation S PWM Latch Q R VSW Driver Switch
X5 63mW Ramp Summer
4A Test PWM Comparator PGND
+0.4 V Detector FB 1.276 V + Positive Error Amp
AGND VC
GM3255
3
Power Management
ELECTRICAL CHARACTERISTICS
(2.7 V < VCC < 30 V; Industrial Grade: 0C < TJ < 70C; Commercial Grade: 0C < TJ< 125C; unless otherwise noted)
CHARACTERISTICS
Error Amplifier Section
FB Reference Voltage FB Input Current FB Reference Voltage Line Regulation Error Amp Transconductance Error Amp Gain Negative Error Amp Gain VC Source Current VC Sink Current VC High Clamp Voltage VC Low Clamp Voltage VC Threshold
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VC tied to FB; measure at FB FB = VREF VC = FB IVC = 25 A (Note 2) (Note 2) FB = 1.0V, VC =1.25V FB = 1.5V, VC = 1.25V FB = 1.0V; VC sources 25A FB = 1.5V, VC sinks 25A Reduce VC from 1.5V until switching stops
1.246 -1.0 300 200 100 25 200 1.5 0.25 0.75
1.276 0.1 0.01 550 500 180 50 625 1.7 0.50 1.05
1.300 1.0 0.03 800 320 90 1500 1.9 0.65 1.30
V A %/V Mho V/V V/V A A V V V
Oscillator Section
Base Operating Frequency Reduced Operating Frequency Maximum Duty Cycle FB Frequency Shift Threshold
FB = 1.0V FB = 0V Frequency drops to reduced operating frequency
230 30 90 0.36
280 52 94 0.40
310 120 0.44
kHz kHz % V
Sync/ Shutdown Section
Sync Range Sync Pulse Transition Threshold SS Bias Current Shutdown Threshold Shutdown Delay
Rise time = 20ns SS = 0V SS = 3.0V 2.7 V VCC 12 V < VCC 12V 30V
320 2.5 -15 0.5 12 12
-3.0 3.0 0.85 80 36
500 8.0 1.2 350 200
kHz V A s s
(Note 1) The maximum package power dissipation must be observed. (Note 2) Guaranteed by design, not 100% tested in production.
GM3255
4
ELECTRICAL CHARACTERISTICS
(2.7 V < VCC < 30 V; Industrial Grade: 0C < TJ < 70C; Commercial Grade: 0C < TJ < 125C; unless otherwise noted)
CHARACTERISTICS
Power Switch Section
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISWITCH = 1.5A, (Note 2) Switch Saturation Voltage ISWITCH = 1.0A, 0C TJ 85C
1.6 1.5 200 1.0A -
0.8 0.55 0.75 0.09 1.9 1.7 250 10 17
1.4 1.00 1.30 0.45 2.4 2.2 300 30 100 30 mA / A A ns V
ISWITCH=1.0A, -40C TA 0C(Note 2) ISWITCH = 10mA Switch Current Limit Minimum Pulse Width 50% duty cycle(Note 2) 80% duty cycle(Note 2) FB = 0 V, ISW =4.0A(Note 2 ) 2.7 V 12V D ICC / DVSW 2.7 V VCC VCC VCC 12V, 10mA ISW
30V, 10mA ISW 1.0A 12V, 10mA ISW 1.5A (Note 2) 30V, 10mA ISW 1.5A (Note 2)
12V
VCC
-
2.0
100 100 A
Switch Leakage General Section Operating Current Shutdown Mode Current Minimum Operation Input Voltage Thermal Shutdown Thermal Hysteresis
VSW = 40 V, VCC = 0V
ISW = 0 VC < 0.8V, SS = 0V, 2.7V VC < 0.8V, SS = 0V, 12V VCC 12V VCC 30V
150 -
5.5 12 2.45 180 25
8.0 60
mA A
100 2.70 210 V C C
VSW switching, maximum ISW = 10mA (Note2) (Note2)
(Note 2) Guaranteed by design, not 100% tested in production.
GM3255
5
TYPICAL PERFORMANCE CHARACTERISTICS
7.2 7.0
VCC = 30 V
1.9
6.8
Current (mA)
1.8
6.6 6.4 6.2 6.0 5.8 5.6 0 50
Temperature (C) VCC = 2.7V VCC = 12V VIN (V)
1.7
1.6
100
1.5
0
50
Temperature (C)
100
Figure 1. ICC (No Switching) vs. Temperature
285 280 2.50 275
fosc (kHz) Current (A)
Figure 2. Minimum Input Voltage vs. Temperature
2.60
VCC = 12V
270 265
2.40
VCC = 2.7V
2.30 260
VCC = 30 V
255
0
50
Temperature (C)
100
2.20
0
50
Temperature (C)
100
Figure 3. Switching Frequency vs. Temperature (GM3255 only)
99
VCC = 30V
Figure 4. Current Limit vs. Temperature
98 97 96 95 94 93
VCC = 12V
Duty Cycle (%)
VCC = 22.7V
0
50
Temperature (C)
100
Figure 5. Maximum Duty Cycle vs. Temperature
GM3255
6
APPLICATION INFORMATION
Current Mode Control
VCC Oscillator S VC
Shown in Figure 6. The power switch is turned off by the output of the PWM Comparator. A TTL-compatible sync input at the SS pin is capable of syncing up to 1.8 times the base oscillator frequency. As shown in Figure 7, in order to sync to a higher frequency, a positive transition turns on the power switch before the output of the oscillator goes high, thereby resetting the oscillator. The sync operation allows multiple power supplies to operate at the same frequency. A sustained logic low at the SS pin will shut down the IC and reduce the supply current.
+
PWM Comparator
Q Power Switch VSW In Out
L D1
R
CO X5 Driver 63 m
RLOAD
SUMMER Slope Compensation
Figure 6. Current Mode Control Scheme
GM3255 family incorporates a current mode control scheme. In which the PWM ramp signal is derived from the power switch current. This ramp signal is compared to the output of the error amplifier to control the on-time power switch. The oscillator is used as a fixedfrequency clock to ensure a constant operational frequency. The resulting control scheme features several advantages over conventional voltage mode control. First, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. This eliminates the delay caused by the output filter and error amplifier, which is commonly found in voltage mode controllers. The second benefit comes from inherent pulse-by pulse current limiting by merely clamping the peak switching current. Finally, current mode commands an output current rather than voltage, then the filter offers only a single pole to the feedback loop. This allows both a simpler compensation and a higher gainbandwidth over a comparable voltage mode circuit. Without discrediting its apparent merits, current mode control comes with its own peculiar problems, and mainly subharmonic oscillation at duty cycles over 50%. The GM3255 family solves this problem by adopting a slope compensation scheme, in which, a fixed ramp generated by the oscillator is added to the current ramp. A proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control.
The FB pin is directly connected to the inverting input of the positive error amplifier, whose nonincerting input is fed by the 1.276V reference. The amplifier is transconductance amplifier with a high output impedance of approximately 1M W, as shown in Figure 8. The V C pin is connected to the output of
Figure 8. Error Amplifier Equivalent Circuit
FB 1.276 V + CM3255 1MW 120pF
An additional feature includes frequency shift to 20% of the nominal frequency when either the NFB or FB pins trigger the threshold. During power up, overload, or short circuit conditions, the minimum switch on-time is limited by the PWM comparator minimum pulse width. Extra switch off-time reduces the minimum duty cycle to protect external components and the IC itself. As Previously mentioned, this block also produces a ramp for the slope compensation to improve regulator stability.
Error Amplifier
VC
Voltage Clamp
C1 0.01F R1 5 kW
positive error-amp
Oscillator and Shutdown
to ground, forming a pole / zero for loop compensation. An external shunt can be connected between the VC
Sync Current Ramp VSW
pin and ground to reduce its clamp voltage.
GM3255
7
the error amplifiers and is internally clamped between 0.5V and 1.7V . A typical connection at the V C pin includes a capacitor in series with a resistor
Consequently, the current limit of the internal power transistor current is reduced from its nominal value.
Switch Driver and Power Switch
The switch driver receives a control signal from the logic section to drive the output power switch. The switch is grounded through emitter resistors (63mW total) to the PGND pin. PGND is not connected to the IC substrate so that switching noise can be isolated from the analog ground. The peak switching current is clamped by an internal circuit. The clamp current is guaranteed to be greater than 1.5A and varies with duty cycle due to slope compensation. The power switch can withstand a maximum voltage of 40V on the collector(VSW pin). The saturation voltage of the switch is typically less than 1V to minimize power dissipation. Short Circuit Condition When a short circuit condition happens in a boost circuit, the inductor current will increase during the whole switching cycle, causing excessive current to be drawn from the input power supply. Since control ICs don's have the means to limit load current, an external current limit circuit(such as a fuse or relay) has to be implemented to protect the load, power supply and ICs. In other topologies, the frequency shift built into the IC prevents damage to the chip and external components. This feature reduces the minimum duty cycle and allows the transformer secondary to absorb excess energy before the switch turns back on. GM3255 can be activated by either connecting the VCC pin to a voltage source or by enabling the SS pin. When the V CC voltage is below the minimum supply voltage, the VSW pin is in high impedance. Therefore, current conduces directly from the input power source to the output through the inductor and diode. Once VCC reaches approximately 1.5V, the internal power switch briefly turns on. This is a part of GM3255's normal operation. The turn-on of the power switch accounts for the initial current swing. When the V C pin voltage rises above the threshold, the internal power switch starts to switch and a voltage pulse can be seen at the VSW pin. Detecting a low output voltage at the FB pin, the built-in frequency shift feature reduces the switching frequency to a fraction of its nominal value, reducing the minimum duty cycle, which is otherwise limited by the minimum on-time of the switch. The peak current during this phase is clamped by the internal current limit.
When the FB pin voltage rises above 0.4V, the frequency increases to its nominal value, and the peak current begins to decrease as the output approaches the regulation voltage. The overshoot of the output voltage is prevented by the active pull-on, by which the sink current of the error amplifier is increased once an overvoltage condition is detected. The overvoltage condition is defined as when the FB pin voltage is 50mV greater than the reference voltage. COMPONENT SELECTION Frequency Compensation The goal of frequency compensation is to achieve desirable transient response and DC regulation while ensuring the stability of the system. A typical compensation network, as shown in Figure 9, provides a frequency response of two poles and one zero. This frequency response is further illustrated in the Bode plot shown in Figure 9.
VC R1
GM3255
C1 GND
C2
Figure 9. A Typical Compensation Network
The high DC gain in Figure 10 is desirable for achieving DC accuracy over ling and load variations. The DC gain of a transconductance error amplifier can be calculated as follows:
GainDC = GM x RO
Where: GM = error amplifier transconductance; RO = error amplifier output resistance 1MW The low frequency pole, fp1, is determined by the error amplifier output resistance and C1 as:
1 fP1 = 2pC1R
O
The first zero generated C1 and R1 is:
1 fz1 = 2pC1R1
GM3255
8
The phase lead provided by this zero ensures that the loop has at least a 45C phase margin at the crossover frequency. Therefore, this zero should be placed close to the pole generated in the power stage, which can be identified at frequency:
fP1 =
where:
1 2pCORLOAD
CO = equivalent output capacitance of the error amplifier 120pF; RLOAD = load resistance. The high frequency pole, fP2, can be placed at the output filter's ESR zero or at half the switching frequency. Placing the pole at this frequency will cut down on switching noise. The frequency of this pole is determined by the value of C2 and R1:
1 fP2 = 2pC1R1
When the power switch turns off, there exists a voltage spike superimposed on top of the steady-state voltage. Usually, this voltage spike is caused by transformer leakage inductance charging stray capacitance between the VSW and PGND pins. To present the voltage at the VSW pin from exceeding the maximum rating, a transient voltage suppressor in series with a diode is paralleled with the primary windings. Another method of clamping switch voltage is to connect a transient voltage suppressor between the VSW pin and ground. Magnetic Component Selection When choosing a magnetic component, one must consider factors such as peak current, core and ferrite material, output voltage ripple, EMI, temperature range, physical size, and cost. In boost circuits, the average inductor current is the product of output current and voltage gain (VOUT / VCC), assuming 100% energy transfer efficiency. In continuous conduction mode, inductor ripple current is
IRIPPLE = VCC(VOUT - VCC) ( f )( L )(VOUT)
One simple method to ensure adequate phase margin is to design the frequency response with a - 20 dB per decade slope, until unity-gain crossover. The crossover frequency should be selected at the midpoint between fZ1 and fP2 where the phase margin is maximized.
Gain (dB) DC Gain
fP1 fZ1 FP2
Frequency(LOG)
Figure 10. Bode Plot of the Compensation Network Shown in Figure 9.
VSW Voltage Limit In the boost topology, VSW pin maximum voltage is set by the maximum output voltage plus the output diode forward voltage. The diode forward voltage is typically 0.5V for Schottky diodes and 0.8V for ultrafast diodes
VSW(MAX) = VOUT(MAX) + VF
where: f = 280kHz. The peak inductor current is equal to average current plus half of the ripple current, which should not cause inductor saturation. The above equation can also be referenced when selecting the value of the inductor based on the tolerance of the ripple current in the circuits. Small ripple current provides the benefits of small input capacitors and greater output current capability. A core geometry like a rod or barrel is prone to generating high magnetic field radiation, but is relatively cheap and small. Other core geometries, such as toroids, provide a closed magnetic loop to prevent EMI. Input Capacitor Selection In boost circuits, the inductor becomes part of the input filter, as shown in Figure 11. In continuous mode, the input current waveform is triangular and does not contain a large pulsed current, During continuous conduction mode, the peak to peak inductor ripple current is given in the previous section. In most applications, input capacitors in the range of 10F to 100F with an ESR less than 0.3W work well up to a full 1.5A switch current.
Where:
VF = output diode forward voltage. In the flyback topology, peak VSW voltage is governed by: VSW(MAX) = VCC(MAX) + (VOUT + VF) X N
Where:
N = transformer turns ratio, primary over secondary
GM3255
9
IIN
IL
VCC
+ -
CIN
RESR
Reducing the Current Limit In some applications, the designer may prefer a lower limit on the switch current than 1.5A. An external shunt can be connected between the VC pin and ground to reduce its clamp voltage. Consequently, the current limit of the internal power transistor current is reduced from its nominal value. The voltage on the V C pin can be evaluated with the equation
VC = ISWREAV
Figure 11. Boost Circuit Effective Input Filter
The situation is different in a flyback circuit. The input current is discontinuous and a significant pulse current is see by the input capacitors. Therefore, there are two requirements for capacitors in a flyback regulator: energy storage and filtering. To maintain a stable voltage supply to the chip, a storage capacitor larger than 20F with low ESR is required. To reduce the noise generated by the inductor, insert a 1.0F ceramic capacitor between VCC and ground as close as possible to the chip. When the power switch is turned on, I L is shunted to ground and IOUT discharges the output capacitor. When the IL ripple is small enough, IL can be treated as a constant and is equal to input current IIN, Summing up, the output voltage peak-peak ripple can be calculated by:
(IIN - IOUT) (1 - D) VOUT(RIPPLE) = (COUT)(f) + IOUTD (COUT)(f) + IIN X ESR
where: R E = 0.063 W, the value of the internal emitter resistor; A V = 5V/ V, the gain of the current sense amplifier . Since R E and A V cannot be changed by the end user, the only available method for limiting switch current below 1.5A is to clamp the VC pin at a lower voltage. If the maximum switch or inductor current is substituted into the equation above, the desired clamp voltage will result. A simple diode clamp, as shown in Figure12, clamps the VC voltage to a diode drop above the voltage on resistor R3. Unfortunately, such a simple circuit is not generally acceptable if VIN is loosely regulated.
V IN VCC R2 VC
D1
R3 R1 C1 C2
The equation can be expressed more conveniently in terms of VCC, VOUT and IOUT for design purposes as follows:
VOUT(RIPPLE) = + IOUT(VOUT - VCC) (COUT)(f) VCC x 1 (COUT)(f)
Figure 12. Current Limiting using a Diode Clamp
(IOUT)(VOUT)(ESR)
The capacitor RMS ripple current is:
IRIPPLE = (IIN - IOUT)2 (1 - D) + (IOUT)2 (D) = IOUT VOUT - VCC VCC
GM3255
10
Although the above equations apply only for boost circuits, similar equations can be derived for flyback circuits.
Another solution to the current limiting problem is to externally measure the current through the switch using a sense resistor. Such a circuit is illustrated in Figure 13.
VCC
In some cases, SHM can rear its ugly head despite the presence of the onboard slope compensation. The simple cure to this problem is more slope compensation avoid the unwanted oscillation. In that case, an external circuit, shown in Figure 14, can be added to increase the amount of slope compensation used. This circuit requires only a few components and is "tacked on" to the compensation network.
VSW VSW
PGND AGND VIN
+ -
VC
R1 Q1 R2 C3 RSENSE Output Ground C1 C2
VC
R1 C1 C2
R2
Figure 13.Current Limiting using a Current Sense Resistor
The switch current is limited to
VBE(Q1) ISWITCH(PEAK) = R
C3
ESENSE
R3
Where: V BE(Q1) = the base - emitter voltage drop of Q1, typically 0.65V. The improved circuit does not require a require a regulated voltage to operate properly. Unfortunately, a price must be paid for this convenience in the overall efficiency of the circuit. The designer should note that the input and output grounds are no longer common. Also, the addition of the current sense resistor, RSENSE, results in a considerable power loss which increase with the duty cycle. Resistor R2 and capacitor C3 form a low - pass filter to remove noise. Subharmonic Oscillation Subharmonic oscillation (SHM) is a problem found in Current-mode control systems, where instability results when duty cycle exceeds 50%. SHM only occurs in switching regulators with a continuous inductor current. This instability is not harmful to the converter and usually does not affect the output voltage regulation. SHM will increase the radiated EM noise from the converter and can cause, under certain circumstances, the inductor to emit high - frequency audile noise. SHM is an easily remedied problem. The rising slope of the inductor current is supplemented with internal "slope compensation" to prevent any duty cycle instability from carrying through to the next switching cycle. In the GM3255, slope compensation is added during the entire switch on-time, typically in the amount of 180 mA/s.
Figure 14. Technique for Increasing Slope Compensation
The dashed box contains the normal compensation circuitry to limit the bandwidth of the error amplifier. Resistors R2 and R3 form a voltage divider off of the VSW pin. In normal operation VSW looks similar to a square wave, and is dependent on the converter topology. Formulas for calculating VSW in the boost and flyback topologies are given in the section "VSW Voltage Limit." The voltage on VSW charges capacitor C3 when the switch is off, causing the voltage at the VC pin to shift upwards. When the switch turns on, C3 discharges through R3, producing a negative slope at the VC pin. The negative slope provides the slope compensation. The amount of slope compensation added by this circuit is
R3 DI = VSW ( R2 + R3 ) (1 - e DT
-(1 - D) R3C3fSW
fSW ) ( (1 - D) R A ) EV
GM3255
11
Where:
DI /DT = the amount of slope compensation added (A/s); VSW = the voltage at the switch node when the transistor is turned off (V); fSW = the switching frequency, typically 280kHz (GM3255) or 560kHz D = the duty cycle; RE = 0.063W, the value of the internal emitter resistor; AV = 5V/V, the gain of the current sense amplifier.
Resistor R1 and capacitors C1 and C2 form the compensation network. At turn on, the voltage at the VC pin starts to come up, charging capacitor C3 through Schottky diode D2, clamping the voltage at the VC pin such that switching begins when VC reaches the VC threshold, typically 1.05V (refer to graphs for detail over temperature). VC = VF(D2) + VC3 Therefore, C3 slows the startup of the circuit by limiting the voltage on the VC pin. The soft- start time increases with the size of C3. Diode D1 discharges C3 when SS is low. If the shutdown function is not used with this part, the cathode of D1 should be connected to VIN. Calculating Junction Temperature To ensure safe operation of the GM3255, the designer must calculate the on-chip power dissipation and determine its expected junction temperature. Internal thermal protection circuitry will turn the part off once the junction temperature exceeds 180C 30C. However, repeated operation at such high temperatures will ensure a reduced operating life. Calculation of the junction temperature is an imprecise but simple task. First, the power losses must be quantified. There are three major sources of power loss on GM3255: Biasing of internal control circuitry, PBIAS Switch driver, PDRIVER Switch saturation, PSAT The internal control circuitry, including the oscillator and linear regulator, requires a small amount of power even when the switch is turned off. The specifications section of this datasheet reveals that the typical operating current IQ, due to this circuitry is 5.5 mA. Additional guidance can be found in the graph of operating current vs. temperature. This graph shows that IQ is strongly dependent on input voltage, VIN, and temperature. Then PBIAS = VINIQ Since the onboard switch is an NPN transistor, the base drive current must be factored in as well. This current is drawn from the VIN pin, in addition to the control circuitry current. The base drive current is listed in the specifications as DICC/DISW, or switch transconductance. As before the designer will find additional guidance in the graphs. With that information, the designer can calculate PDRIVER = VINISW X ICC XD DISW
In selecting appropriate values for the slope compensation network, the designer is advised to choose a convenient capacitor, then select values for R2 and R3 such that the amount of slope compensation added is 100mA /s. Then R2 may increased or decreased as necessary. Of course, the series combination of R2 and R3 should be large enough to avoid drawing excessive current from VSW. Additionally, to ensure that the control loop stability is improved, the time constant formed by the additional components should be chosen such that
R3C3 < 1-D fSW
Finally, it is worth mentioning that the added slope compensation is a trade-off between duty cycle stability and transient response. The more slope compensation a designer adds, the slower the transient response will be, due to the external circuitry interfering with the proper operation of the error amplifier. Soft Start Through the addition of an external circuit, a soft-start function can be added to GM3255 of components. Soft-start circuitry prevents the VC pin from slamming high during startup, thereby inhibiting the inductor current from rising at a high slope. This circuit, shown in Figure 15, requires a minimum number of components and allows the soft-start circuitry to activate any time the SS pin is used to restart the converter.
VIN VCC SS D1 Test C3 C1 Test SS 4 A Q VC R1 C2
GM3255
Figure 15. Soft Start
12
Where ISW = the current through the switch; D = the duty cycle or percentage of switch on-time. ISW and D are dependent on the type of converter. In a boost convert,
1 ISW(AVG) @ ILOAD X D X Efficiency D @ VOUT -VIN VOUT
If T J approaches 150C, the designer should consider possible means of reducing the junction temperature. Perhaps another converter topology could be selected to reduce the switch current. Increasing the airflow across the surface of the chip might be considered to reduce TA. Output Setting GM3255 develops a 1.276 V reference (V REF ) from the FB pin to ground. Output voltage is set by connecting the FB pin to an output resistor divider (Figure 16). The FB pin bias current represents a small error and can usually be ignored for values of R2 up to 7k. The suggested value for R2 is 6.19k.
VOUT FB PIN VREF Figure 16. Output Resistor Divider R1 R2 VOUT = VREF (1 + R1 ) R2
In a flyback converter,
ISW(AVG) @ D@ VOUTILOAD 1 X Efficiency VIN VOUT VOUT +
NS NP
VIN
The switch saturation voltage, V (CE)SAT , is the last major source of on-chip power loss. V(CE)SAT is the collector-emitter voltage of the internal NPN transistor when it is driven into saturation by its base drive current. The value for V(CE)SAT can be obtained from the specifications or from the graphs, as "Switch Saturation Voltage." Thus,
PSAT @ V(CE)SATISW X D
V R1 = R2 ( OUT -1) 1.276
Finally, the total on-chip power losses are
PD = PBIAS + PDRIVER + PSAT
Power dissipation in a semiconductor device results in the generation of heat in the junctions at the surface of the chip. This heat is transferred to the surface of the IC package, but a thermal gradient exists due to the resistive properties of the package molding compound. The magnitude of the thermal gradient is expressed in manufacturers' data sheets as QJA, or junction-to- ambient thermal resistance. The on-chip junction temperature can be calculated if QJA, the air temperature near the surface of the IC, and the on-chip power dissipation are known. TJ = TA + (PDQJA) where: TJ = IC or FET junction temperature (C); TA = ambient temperature (C); PD = power dissipated by part in question(W); QJA = junction-to ambient thermal resistance (C / W). For GM3255, QJA = 165C / W. Once the designer has calculated TJ, the question of whether the GM3255 can be used in an application is settled. If TJ exceeds 150C, the absolute maximum allowable junction temperature, the GM3255 is not suitable for that application.
Circuit Layout Guidelines In any switching power supply, circuit layout is very important for proper operation. Rapidly switching currents combined with trace inductance generates voltage transitions that can cause problems. Therefore the following guidelines should be followed in the layout. 1. In boost circuits, high AC current circulates within the loop composed of the diode, output capacitor, and on-chip power transistor. The length of associated traces and leads should be kept as short as possible. In the flyback circuit, high AC current loops exist on both sides of the transformer. On the primary side, the loop consists of the input capacitor, transformer, and on-chip power transistor, while the transformer, rectifier diodes, and output capacitors form another loop on the secondary side. Just as in the boost circuit, all traces and leads containing large AC current should be kept short. 2. Separate the low current signal grounds from the power grounds. Use single point grounding or ground plane construction for the best results. 3. Locate the voltage feedback as near the IC as, possible to keep the sensitive feedback wiring short. Connect feedback resistors to the low current analog ground.
GM3255
13
22 H 3.3 VIN 10 F VCC (5) GND PGND (7) AGND (6) GM3255 VC (1) 0.1 F 5.0 k 200 pF FB (2) VSW (8)
MBRS120T3 5.0 VO 3.6 k 22 F GND
1.3 k
Figure 17. Additional Application Diagram, 3.3 V Input, 5.0 V/ 400mA Output Boost Converter
R2 4.87 k 1 2 C1 0.01F SS VCC 5.0 V R1 5.0 k R3 1.27 k
+
C4 VC Test GM3255 VSW PGND AGND 8
D1
+
7 6 L1
+
VOUT -12 V
22F
MBRS120T3
3 NFB 4 SS
VCC 5
C3 22F
22H D2 MBRS120T3
C2 22F
Figure 18. Additional Application Diagram, 5.0V to -12V/ 75mA Inverting Converter
MBRS140T3 VCC
+
P6KE-15A 22 F 1.0 F VCC (5) 1N4148 VSW (8)
-12 V T1
+
47 F GND
GND
1:2
+
47F +12 V
PGND (7) AGND (6) GM3255 VC (1 ) 47 nF 4.7 nF 2.0 k
MBRS140T3 FB (2) 1.28 k 10.72 k
GM3255
Figure 19. Additional Application Diagram, 2.7 to 13 V Input, 12 V/ 200 mA Output Flyback Converter
14
GND VC (1) 2.2 F 200 pF 0.01F VIN AGND (6) PGND (7) 5.0 k GM3255 VSW (8) FB (2) 300 15 H VCC (5) 22 F Low ESR 1.1 k GND
-5.0 VOUT
Figure 20. Additional Application Diagram, -9.0 V to -28 V Input, -5.0 V/700 mA Output Inverted Buck Converter
22 H VCC 22 F GND VCC (5) PGND (7) AGND (6) GM3255 VC (1) 200 pF 0.01F 5.0 k 12.76k 22 F FB (2) VSW (8)
+
5.0 V
+
22 F
22 F Low ESR
37.24 k
GND
Figure 21. Additional Application Diagram, 2.7 V to 28 V Input, 5.0 V Output SEPIC Converter
R1 R2 1.245 k / 0.1 W, 1% 99.755k / 0.1 W, 1% GND C1 0.1 50 V D1 C2 0.1 50 V D1 D1 C3 0.1 50 V D1 100 VO
1N4148 1N4148 1N4148 1N4148 1N4148 1N4148 1N4148
D1 GM3255 C10 C11 0.01 0.1 R3 2.0 k 1V C 2 FB 3 Test 4 SS VSW 8 PGND 7 6 AGND VCC 5
D1
D1
C8 10
C9 0.1 C7 0.1 50 V
C4 0.1 50 V
C5 0.1 50 V
C6 0.1 50 V GND
4.0 V
Figure 22. Additional Application Diagram, 4.0 V Input, 100 V/ 10 mA Output Boost Converter with Output Voltage Multiplier
GM3255
15
200 pF C6 C1 0.01 F D1 1V C GM3255 2 FB 3 Test SS +5.0 V GND C5 + 22 F R2 1.28 k R3 10.72 k +12 V 4 SS + VSW 8 PGND 7 AGND 6 VCC 5 C4 0.1 F D2 D3 C3 + 22 F L1 15 H -12 V 22 F
R1
5.0 k
GND
Figure 23. Additional Application Diagram, 5.0 V Input, 12 V Output Dual Boost Converter
VIN 2.7V TO 16V T1
+
C1 22 F 5 VIN VSW GM3255 3 NFB VC GND 6, 7
D2 P6KE-15A D3 1N4148
2
4
* *
1 3
+
C4 47 F
OFF
ON 4 S/S
8
-VOUT -V
R2 2.49k 1% R3 2.49k 1% -5
D1 MBRS130LT3
1
C2 0.047 F R1 2k
C3 0.0047 F
Figure 24. Positive to Negative Converter with Direct Feedback
R2 1.21k 1% VIN 2.7V TO 13V R1 13k 1% MBRS140T3 T1 C1 22 F 2, 3 P6KE-20A * 2 5 + VOUT 15V C4 47 F
+
5
VIN 8 VSW 1N4148 6, 7
OFF
FB ON 4 S/S GM3255
*4 8 *
1
+
C5 47 F -V OUT -15V R4 12.1k 1% R5 2.49k 1%
NFB VC 1 C2 0.047 F R3 2k GND 6, 7
3
MBRS140T3
C3 0.0047 F
GM3255
Figure 25. Dual Output Flyback Converter with Over Voltage Protetion
16
VIN 5V
L1 2 1 3 4 C2 47 F 16V GM3255 R1 1k 1%
V OUT -3 V 250mA
C1 22 F 10V
+
5V IN 4 S/S 7 GND 6 GND S
VSW
8 + 3 1 D1 + R4 2k C4 0.047F R2 4.99k 1% C3 47F 16V C6 0.1 F
NFB VC
C5 0.0047F
Figure 26. Low Ripple 5V to -3V "Cuk" Converter
C2 27pF VIN 4.5V TO 30V + 5
10 F
5mA MAX LAMP 10 T1 4 3 2 C1 0.1 F 1 D1 1N4148
Q1 330 W 2.7V TO 5.5V +
2.2 F
Q2
OFF
ON 4 S/S
5 VIN
1N5818 8
L1 33 F
D2 1N4148
562 W* 20k
DIMMING
VSW
10k
GM3255 GND 6, 7 VFB VC +1 2 22k
0.1 F
2 F
1N4148
OPTIONAL REMOTE DIMMING
Figure 27. CCFL Supply
VIN 4V TO 9V
5 ON OFF GM3255 + C1 33 F 20V FB GND 6, 7 2 4 L1A 10 H
S/S
V SW
C2 1 F
R2 18.7k 1% L1B 10 H R3 6.19k 1%
5V + C3 100 F 10V
VC
1 R1 2k C4 0.047F
C5 0.0047F
Figure 28. 2 Li - Lion Cell to 5V SEPIC Converter
GM3255
17
V IN
MBRS130LT3 V OUT
8
SOP-8 PACKAGE OUTLINE DIMENSIONS
0.008 +0.0018 -0.0005
0 ~ 8
0.028
+0.013 -0.022 +0.33 -0.56
0.200
+0.05 -0.01
Pad Layout
0.060 1.52
0.710
0.236 0.008 5.990
+0.21 -0.20 +0.003 -0.004
0.275 7.0
0.155 4.0
0.154
PIN INDENT
3.91 0.1
0.024 0.6 0.050 1.270
Inches ( mm )
0.191
+0.002 -0.004 +0.05 -0.10
4.850
0.063 0.005 1.600 0.130
0.057 NOM 1.450 NOM
( Inches ) mm
0.007 0.003 0.175 0.075
0.050 NOM 1.270 NOM
0.016
+0.004 -0.003 +0.10 -0.08
0.410
NSOP-8 PACKAGE OUTLINE DIMENSIONS
90 X 90 95 X 130
GM3255
18
Exposed Pad Version Only
ORDERING NUMBER
GM 3255 S8 R
Gamma Micro. Circuit Type
Shipping R: Tape & Reel
Package S8: SO-8 NS8: NSOP-8
GM3255
19

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