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EPL09060
9 COM/ 60 SEG LCD Driver
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
December 2005
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (U.S.A) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600
Contents
Contents
1 2 3 4 5 6 7 General Description .................................................................................................. 5 Features ..................................................................................................................... 5 Applications............................................................................................................... 6 Pin Configuration (Package) .................................................................................... 6 Functional Block Diagram........................................................................................ 8 Pin Description.......................................................................................................... 9 Functional Description ........................................................................................... 12 7.1 MPU Interface ...................................................................................................12
7.1.1 7.1.2 Chip Select ........................................................................................................12 Selecting the Interface Type..............................................................................13 Display Data RAM (DDRAM) ............................................................................15 Programmable Duty Ratio.................................................................................16 Display Data Latch Circuit .................................................................................17 Shift Register Circuit..........................................................................................18 Common Driver Circuit ......................................................................................20 Segment Driver Circuit ......................................................................................20 LCD Driving Waveform......................................................................................21 Voltage Converter Circuits.................................................................................23 Voltage Regulator Circuits.................................................................................23 Voltage Follower Circuits...................................................................................25 Oscillator ...........................................................................................................26 Oscillator Frequency .........................................................................................26
7.2
Data Transfer ....................................................................................................14
7.2.1 7.2.2
7.3
LCD Driver Circuits ...........................................................................................17
7.3.1 7.3.2 7.3.3 7.3.4 7.3.5
7.4
Internal Power Circuits......................................................................................22
7.4.1 7.4.2 7.4.3 7.4.4 7.4.5
8 9
7.5 Reset Circuit .....................................................................................................27 Control Register ...................................................................................................... 28 Application Information .......................................................................................... 37 9.1 Instruction Procedure Examples .......................................................................37
9.1.1 Initial Setup........................................................................................................37
9 10 11 12 13
Relationship between Setting and Common/Display RAM ................................. 42 Absolute Maximum Ratings ................................................................................... 43 DC Characteristics .................................................................................................. 44 AC Characteristics .................................................................................................. 45 Application Circuit .................................................................................................. 53
Product Specification (V1.0) 12.28.2005
iii
Contents
Specification Revision History
Doc. Version 0.1 0.2 0.3 1.0 Initial version Deleted the background confidential mark. Modified the VREF20 Range at the DC characteristics table. Removed the background Preliminary mark. Revision Description Date 2004/02/20 2004/03/04 2005/03/28 2005/12/28
iv *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
1 General Description
The EPL09060 is a driver and controller LSI for graphic dot-matrix liquid crystal display systems. It can be interfaced to the MPU via serial or 8-bit interface. It contains 9 common and 60 segment driver circuits. A single chip can drive a graphic display system with a maximum of 60 x 9 dots.
2 Features
Direct Correspondence between Display Data RAM and LCD Pixel Display Data RAM : 43 x 102 = 4386 bits 69 LCD Drivers : 60-seg segment drivers, 8-common drivers and 1-icon Serial Interface (SPI) or 8-Bit Parallel Interface Mode (80-/68-series MPU) On-chip oscillator circuit Programmable Duty Ratio:
Duty Ratio 1: 8 (+ ICON) 1:16 (+ICON)
Note: ICON = "0" : Pin disable ICON = "1" : Pin enable
Common 8 (+ ICON) 16 (+ICON)
Segment 60 60
Selectable LCD driving bias level : 1/3,1/3.5,1/4,1/4.5,1/5,1/5.5,1/6,1/6.5,1/7,1/7.5,1/8 bias Selectable LCD display clock frequency Electronic contrast control function (64 steps) Built-in useful Instruction Set : Display data read/write, Display on/off, Inverse display, Page address set, Common address set, LCD display contrast control, Set Sleep mode, Standby mode, etc. Operating Voltage range : - Supply voltage : 2.2V to 3.4 V - LCD driving voltage : 3.0V to 6 V Package (Ordering information):
Part Number EPL09060H Package Bare die Description NA Package Information Page 6
Note: The EPL09060 series has the following sub-codes, depending on their shapes. H: Bare die (Aluminum pad without bump); GH: Gold bumped die F: COF package; T: TAB (TCP) package Example: EPL09060H EPL09060 Elan; H: Bare die
Product Specification (V1.0) 12.28.2005
*5
EPL09060
9 COM/60 SEG LCD Driver
3 Applications
Organizer Scientific calculator Graphic pager Electronic Dictionary Cellular phone Handy Terminals (PDA)
4 Pin Configuration (Package)
104 103102 1 2 3 72 71 70 69 68
DDRAM
67
15 16 17 18 19 20 49 50 51
53 52 51
Figure 1 Pin Configuration
NOTE With the Elan logo at the right bottom corner (as shown in the figure) and DDRAM (black color) at the right side, Pin 1 is at the upper left corner.
Pad Configuration
Item Chip size Pad size (Type A) Pad size (Type B) Pad size (Type C) Pad pitch Pad No. X - 1, 17~21, 30~52, 69~104 2, 14~15, 22~29 4~13, 16, 53~68 Type A Type B 4040 85 90 90 105 110 Size Y 2070 90 90 85 m Unit
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Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver Pad Coordinates Table
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Symbol COMI1 VDD VDD C1+ C1C2+ VOUT V0 V1 V2 V3 V4 VR GND GND PS C86 CLS OSC IRS /RES D7 D6 D5 D4 D3 D2 D1 D0 CS2 /CS1 A0 /WR /RD TEST COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMI2 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 X -3852.5 -3860.0 -3860.0 -3868.1 -3868.1 -3868.1 -3868.1 -3868.1 -3868.1 -3868.1 -3868.1 -3868.1 -3868.1 -3860.0 -3860.0 -3868.1 -3870.7 -3765.7 -3660.7 -3555.7 -3450.7 -3318.2 -3208.2 -3098.2 -2988.2 -2878.2 -2768.2 -2658.2 -2548.2 -2403.5 -2298.5 -2193.5 -2088.5 -1983.5 -1878.5 -1752.5 -1647.5 -1542.5 -1437.5 -1332.5 -1227.5 -1122.5 -1017.5 -912.5 -807.5 -702.5 -597.5 -492.5 -387.5 -282.5 -177.5 -72.5 Y -75.3 -229.15 -353.9 -473.1 -578.1 -683.1 -788.1 -893.1 -998.1 -1103.1 -1208.1 -1313.1 -1418.1 -1541.3 -1651.3 -1774.2 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1890.0 -1890.0 -1890.0 -1890.0 -1890.0 -1890.0 -1890.0 -1890.0 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 -1898.1 Pad No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Symbol SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 X -75.1 -75.1 -75.1 -75.1 -75.1 -75.1 -75.1 -75.1 -75.1 -75.1 -75.1 -75.1 -75.1 -75.1 -75.1 -75.1 -72.5 -177.5 -282.5 -387.5 -492.5 -597.5 -702.5 -807.5 -912.5 -1017.5 -1122.5 -1227.5 -1332.5 -1437.5 -1542.5 -1647.5 -1752.5 -1857.5 -1962.5 -2067.5 -2172.5 -2277.5 -2382.5 -2487.5 -2592.5 -2697.5 -2802.5 -2907.5 -3012.5 -3117.5 -3222.5 -3327.5 -3432.5 -3537.5 -3642.5 -3747.5 Y -1774.2 -1669.2 -1564.2 -1459.2 -1354.2 -1249.2 -1144.2 -1039.2 -934.2 -829.2 -724.2 -619.2 -514.2 -409.2 -304.2 -199.2 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3 -75.3
Note: For PCB layout, the IC substrate must be connected to VSS or floating.
Product Specification (V1.0) 12.28.2005
7
EPL09060
9 COM/60 SEG LCD Driver
5 Functional Block Diagram
SEG0 V0 V1 V2 V3 V4 VSS
SEG59 COM0
COM7 COMI
SEGMENT DRIVER CIRCUITS
COMMON DRIVER CIRCUITS
Voltage Followers LATCH CIRCUIT SHIFT REGISTER
VOUT Connect the capacitor
Voltage Converter
DISPLAY DATA RAM
COLUMN ADDRESS DECODER
COLUMN ADDRESS COUNTER
Display Timing Generator Circuit
COLUMN ADDRESS REGISTER
INSTRUCTION DECODER
INITIAL DISPLAY LINE REGISTER
VR
Voltage Regulator
PAGE ADDRESS REGISTER LOW ADDRESS DECODER LINE ADDRESS DECODE LINE COUNTER
Oscillator Bus holder
INSTRUCTION REGISTER STATUS REGISTER
CLS OSC
MPU Interface
I/O Buffer ( Serial / Parallel )
IRS /CS1CS2 A0 /RD /WRC86 P/S /RES D7 D6 D5 D4 D3 D2 D1 D0 (E) (R/W) (SDI)(SCK)(SDO)
Figure 2 System Block Diagram
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Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
6 Pin Description
Power Supply
Name VDD VSS I/O Power Power VDD Power Supply 0V (GND) LCD driver supply voltages. The voltage applied is determined by the LCD pixel and is changed through changing the impedance using an operational amplifier (OPA) for various applications. Voltage levels are determined based on V0, and must maintain the relative magnitudes shown below: V0V1V2V3V4VSS When the internal power circuit is active, these voltages are generated according to the state of LCD bias, The selection of voltages is determined by the "LCD bias select" instruction, as shown in the table below. V0 V1 V2 V3 V4 LCD Bias Power 1/8 Bias 1/7.5 Bias 1/7 Bias 1/6.5 Bias 1/6 Bias 1/5.5 Bias 1/5 Bias 1/4.5 Bias 1/4 Bias 1/3.5 Bias 1/3 Bias V1 7/8 x V0 6.5/7.5 x V0 6/7 x V0 5.5/6.5 x V0 5/6 x V0 4.5/5.5 x V0 4/5 x V0 3.5/4.5 x V0 3/4 x V0 2.5/3.5 x V0 2/3 x V0 V2 6/8 x V0 5.5/7.5 x V0 5/7 x V0 4.5/6.5 x V0 4/6 x V0 3.5/5.5 x V0 3/5 x V0 2.5/4.5 x V0 2/4 x V0 1.5/3.5 x V0 1/3 x V0 V3 2/8 x V0 2/7.5 x V0 2/7 x V0 2/6.5 x V0 2/6 x V0 2/5.5 x V0 2/5 x V0 2/4.5 x V0 2/4 x V0 2/3.5 x V0 2/3 x V0 V4 1/8 x V0 1/7.5 x V0 1/7 x V0 1/6.5 x V0 1/6 x V0 1/5.5 x V0 1/5 x V0 1/4.5 x V0 1/4 x V0 1/3.5 x V0 1/3 x V0 Description
LCD Driver Supply
Name C1+ C1C2+ VOUT VR I/O O O I/O I Description Boosted capacitor connecting terminals used for voltage booster. Boosted capacitor connecting terminals used for voltage booster. Voltage converter output V0 voltage adjustment pin
Product Specification (V1.0) 12.28.2005
9
EPL09060
9 COM/60 SEG LCD Driver
System Control
Name P/S I/O I Description Select theInterface mode with the MPU. When PS = "High": Parallel interface mode When PS = "Low": Serial interface mode Select the kinds of the MPU to interface. When C86 = "High": 68-series MPU interface mode When C86 = "Low": 80-series MPU interface Internal oscillator circuit enable / disable select pin. CLS = "H": Enable the Internal oscillator circuit CLS = "L": Disable the Internal oscillator circuit (External display clock input to the OSC pin) When using an external oscillator, input the clock to the OSC pin. When using an internal oscillator, leave this pin open. Internal resistor select pin. This pin selects the resistors for adjusting the V0 voltage level and is available only in master mode. - IRS = "H": Internal resistors are used. - IRS = "L": External resistors are used. V0 voltage is controlled using the external divider resistor connecting the VR pin. Test pin. Must be fixed at VSS.
C86
I
CLS
I
OSC
I
IRS
I
TEST
I
MPU Interface
Name /RES I/O I Description Hardware reset input The LSI is reset when this signal is pulled low (Active low) Chip select signals. The Chip Select of the LSI becomes active when CS1 is "L" and CS2 is "H", which allows input/output of data or commands. /CS1 /CS1, CS2 I "L" "L" "H" "H" CS2 "L" "H" "L" "H" Status The device is not active (D7~D0 is Hi-Z) Data and instruction are available. The device is not active (D7~D0 is Hi-Z) The device is not active (D7~D0 is Hi-Z)
A0
I
/WR (R/W)
I
/RD (E)
I
D0 to D7
I/O
Used as register selection input When A0 = "High", Data register When A0 = "Low", Instruction register When C86 = "High"(68-series MPU interface), used as read (/WR = "High"), write (/WR = "Low") When C86 = "Low " (80-series MPU interface), used as write enable input (/WR) When C86 = "High"(68-series MPU interface), used as read/write enable input (E). When C86 = "Low "(80-series MPU interface), used as read enable input (/RD) When in serial mode, D6 (SCK) is used as serial clock input pin, D7 (SDI) is used as serial data input pin, D5 (SDO) is used as serial data output pin and the others are not used. When in parallel mode, D0 to D7 are used as bidirectional data bus pin. Product Specification (V1.0) 12.28.2005
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EPL09060
9 COM/60 SEG LCD Driver
LCD Driver Output
Name I/O LCD common output pins Scan Data COM0 to COM7 H O L FR H L H L COMs Output Voltage Vss V0 V1 V4 Vss Description
Power Save Mode
COMI
O
There are two icon display pins. Both pins output the same signal. Leave these pins open when they are not used. LCD segment output pins Display Data FR V0 Vss V2 V3 Vss SEGs Output Voltage Normal Display Reverse Display V2 V3 V0 Vss
SEG0 to SEG59
O
H L H L L Power Save Mode H
Product Specification (V1.0) 12.28.2005
11
EPL09060
9 COM/60 SEG LCD Driver
7 Functional Description
Instruction Decoder
Bus Holder
Instruction Register
Status Register
MPU Interface
I/O Buffer ( Serial/Parallel )
/CS1 CS2 A0 /RD /WR C86 P/S /RES D7 D6 D5 D4 D3 D2 D1 D0 BUSY (E) (R/W) (SDI)(SCK)(SDO)
Figure 3 System Interface
7.1 MPU Interface
7.1.1 Chip Select
The EPL09060 has two chip select pins /CS1 and CS2. When /CS1="L" and CS2="H", MPU interface is available. When the chip select pin is inactive (other /CS1 and CS2 condition), D7 to D0 are high impedance (invalid) and input of A0, /RD, or /WR inputs are not effective. If serial interface is selected, the shift register and the counter are both reset. However, reset is always operated in any conditions of /CS1 and CS2.
P/S Serial Mode (L) C86 SPI interface (-) A0 A0 A0 A0 WR R/W /WR R/W /RD - /RD E D0~D4 D5 SDO D6 SCK D7 SDI
*
Parallel 80-series (L) Mode 68-series (H) (H)
Note: "
D0~D7 D0~D7
* " Don't care ("High", "Low" or "Open")
"-" Indicates that it is fixed to either "High" (VDD) or "Low" (VSS)
12 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
7.1.2 Selecting the Interface Type
The EPL09060 can be operated with serial interface (SPI) and parallel interface (80series or 68-series) as selected by P/S pin. Serial Interface (SPI) When serial mode (PS = "L"), D6 (SCK) is used as serial clock input pin, D7 (SDI) is used as serial data input pin, D5 (SDO) is used as serial data output pin. When the LSI is active (/CS1="L", CS2="H"), serial data input (D7), serial clock input (D6) inputs and serial data output (D5) are enabled. The 8-bit shift register and 3-bit counter are reset to the initial condition when the chip is not selected. The data input/output from SDI/SDO terminal is MSB first as in the order of D7, D6...D0, and is latched at the rising edge of the serial clock SCK. Serial input data is display data when A0="H" and instruction when A0="L". The A0 input is read in and identified at the rising edge of the (8 x n) serial clock pulse. Since the clock signal (D6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended.
/C 1 S C S2 SC K (D 6) SD I (D 7) SD O (D 5)
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
D 7
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
D 7
A 0
Figure 4 Serial Interface Signal Chart
A0 0 0 1 1
/WR (R/W) 0 1 0 1
D7 (SDI) Instruction Write Invalid Display Data Write Invalid
D5 (SDO) Status Read Status Read Status Read Display Data Read
Product Specification (V1.0) 12.28.2005
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EPL09060
9 COM/60 SEG LCD Driver
Parallel Interface (8-bit Length) Parallel mode (8-bit length): When parallel input is selected (PS = "H"), D0~D7 can be connected directly to the 80-series or 68-series MPU by setting the C86 pin to high or low.
A0
/RD
/WR
D7~D0
N
D(N)
D(N+1)
D(N+2)
D(N+3)
D(N+4)
Write Timing Diagram
A0
/RD
/WR
D7~D0
N
Dummy
D(N)
D(N+1)
D(N+2)
D(N+3)
Read Timing Diagram
Figure 5 Write and Read Timing Diagrams
Common A0 H H L L /RD L H L H
80-Series /WR H L H L
68-Series R/W H L H L
Description Display data read Display data write Register status read Writes to Instruction register
7.2 Data Transfer
The EPL09060 uses a bus holder and an internal data bus for data transfer with the MPU. When writing data from the MPU to the DDRAM, data is automatically transferred from the bus holder to the DDRAM. When reading data from the DDRAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from the bus holder for the next data read cycle.
14 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
7.2.1 Display Data RAM (DDRAM)
Initial Display Line
Page Address
Line Address
Low Address
Line Counter
Decoder
Decoder
Register
D is p la y D a t a R A M
C o lu m n A d d r e s s D e c o d e r
C o lu m n A d d r e s s C o u n t e r
C o lu m n A d d r e s s R e g is t e r
Figure 6 Display Data RAM Diagram
The display data RAM (DDRAM) stores pixel data for the LCD. It is a 43-row x 102column addressable array. It is possible to access any required bit by specifying the page address and the column address. The 43 rows are divided into five pages of eight lines, one page with two lines (D0, D1) and the seventh page with a single line (D0 only). Each bit in the Display Data RAM corresponds to each pixel of the LCD panel. Each bit in the Display Data RAM corresponds to each pixel of the LCD panel and controls the display by applying the following bit data. When in Normal Display : On="1" , Off="0" When in Inverse Display : On="0" , Off="1" (Refer to "Inverse Display On/Off" instruction for more details.)
0 0 0 0 0 0 0
0 1 1 1 1 1 0
0 1 0 1 0 1 0
0 1 0 1 0 1 0
0 1 0 1 0 1 0
0 1 0 1 0 1 0
0 0 0 0 0 0 0 Normal Display Inverse Display
Display Data RAM
Figure 7 Display Data RAM, Normal and Inverse Liquid Crystal Display Diagrams
Product Specification (V1.0) 12.28.2005
Register
15
EPL09060
9 COM/60 SEG LCD Driver
7.2.2 Programmable Duty Ratio
The duty ratio is selected by using the "Set Duty Ratio" instruction. The common output circuits are shown in the following figure. They are separated into three shift registers and controlled by the "duty ratio register".
COM0 COM7 COMI
Common Driver (8)
Common Driver (1)
8-bit Shift Register
1-bit Shift Register
4
Duty Ratio Register
Figure 8 Common Output Circuits Common Output Pins Duty SHL COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COMI Line Address 1/9 1/8 1/17 1/16 0 1 0 1 0 7 0 F 1 6 1 E 2 5 2 D 3 4 3 C 4 B 5 A 6 9 7 8 COMI COMI -
Relationship between Duty Ratio and Common Output It should be noted that when using 1/16 duty (SHL=0), the MCU writes data to the LCD DRAM (Page 0: line addresses 0~7; Page 1: line addresses 8~15) and it will correspond to common output pins (Page 0: COM0~7; Page 1: COM34~41). But the EPL09060 have real output common pins COM0~7 and COMI, the others are invalid. Initial Display Line Register The initial display line register assigns a DDRAM line address which corresponds to COM0 by using the "Initial display line set" instruction. It is used not only for normal display but also for vertical display scrolling and page switching without changing the contents of the DDRAM. However, the 9th address for the icon display cannot be assigned for the initial display line address. Line Counter The line counter provides a DDRAM line address. It initializes its contents at the switching of frame reversal signal (FR (internal)), and also counts-up in synchronization with the common timing signal.
16 * Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver Column Address Counter The column address counter is an 8-bit preset counter which provides a DDRAM column address, and is independent of page address register. It will increment (+1) the column address whenever "display data read" or "display data write" instructions are issued. However, the incrementing of column address is stopped at column address 65H. The count-lock will be released by the "column address set" instruction again. The counter can inverts the correspondence between the column address and segment driver direction by means of "ADC select" instruction. Page Address Register The page address register provides a DDRAM page address. The Page Address 6 is used for icon display, and only D0 is valid.
7.3 LCD Driver Circuits
COM0 COM7 COMI SEG0 SEG59
V0 V1 V2 V3 V4 VSS
Common Driver Circuits
Segment Driver Circuits
Shift Register Display Timing Generator Circuit
Latch Circuit
From the Display Data RAM
Figure 9 LCD Driver Circuits
This driver circuit is configured by 8-common drivers, 60-segment drivers and 1-iconcommon driver. This LCD panel driver voltage depends on the combination of display data and FR (internal) signal.
7.3.1 Display Data Latch Circuit
The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. "Display on/off", "Inverse display on/off" and "Entire display on/off" instructions control only the contents of this latch circuit, they cannot change the contents of the DDRAM.
Product Specification (V1.0) 12.28.2005 17
EPL09060
9 COM/60 SEG LCD Driver
7.3.2 Shift Register Circuit
The circuit contains a 42-bit shift register to shift the turn-on data required for the LCD drive common signals and 1-bit shift register used for icon. The clock of this shift register is generated by display clock CL (internal). Examples of 1/17 duty (ICON enable) driving waveform
1 /1 7 D u ty
CL (in te rn a l) FR (in te rn a l)
0
1
7
16 0
1
2
7
16
0
1
COM0
COM1
COM7
COMI
Figure 10 1/17 Duty Driving Waveform 18 * Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
Examples of 1/16 duty (ICON disable) driving waveform
1 /1 6 D u ty
CL (in te rn a l) FR (in te rn a l)
0
1
7
15 0
1
2
7
15 0
1
COM0
COM1
COM7
Figure 11 1/17 Duty Driving Waveform
Product Specification (V1.0) 12.28.2005
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EPL09060
9 COM/60 SEG LCD Driver
7.3.3 Common Driver Circuit
The Common driver circuit consists of nine drive circuits. One of the four LCD driving level is selected by the combination of FR (internal) and the data from the sift register.
V0
VCON
VSS
Shift Data
COM0~7,COM I
Scan Data H
FR
COMs Output Voltage VSS V0 V1 V4 VSS
V4
VCOFF
V1
H L H L L Power save mode
FR (internal)
Figure 12 Common Driver Circuit
7.3.4 Segment Driver Circuit
The Segment driver circuit consists of 60 driver circuits. One the four LCD driving level is selected by the combination of FR (internal) and the display data transferred from the latch circuit.
VSS
VSON
V0
Display Data
SEG0~59
Display Data H
SEGs Output Voltage FR Normal Display V0 VSS V2 V3 VSS Inverse Display V2 V3 V0 VSS
V3
VSOFF
V2
H L H L L Power save mode
FR (internal)
Figure 13 Common Driver Circuit
20 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
7.3.5 LCD Driving Waveform
The following illustration is an example of how the common and segment drivers are attached to an LCD panel.
CL (internal)
SEG 0
COM0 COM1
FR (internal)
V0 V1
COM0
V4 VSS V0 V1
COM1
V4 VSS V0 V2
SEG0
V3 VSS V0
SEG0-COM0
-V0
Figure 14 LCD Driver Circuits
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9 COM/60 SEG LCD Driver
7.4 Internal Power Circuits
LCD Driving Voltage Supply
Voltage Followers
VR
Voltage Regulator
IRS
VOUT Connect the capacitor Voltage Converter
Figure 15 Internal Power Circuits
The internal power supply circuits can generate the voltage levels necessary to drive the liquid crystal driver circuits, with low power consumption and the least components. They comprise of voltage converter (V/C) circuits, voltage regulator (V/R) circuits, and voltage follower (V/F) circuits.
User Setup Only the internal power supply circuits are used Only the voltage Regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Power Control (VC VR VF) 111 V/C V/R V/F VOUT V0 V1 ~ V4
Circuits Circuits Circuits On On On
Open
Open
Open
011
Off
On
On
External Input
Open
Open
001
Off
Off
On
Open
External Input
Open
000
Off
Off
Off
Open
External External Input Input
22 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
7.4.1 Voltage Converter Circuits
These circuits boost up the electric potential between VDD and VSS to 2 times toward the positive side and the boosted voltage is outputted from VOUT pin. The boosting magnitude of the internal booster circuit is selected by means of the capacitor connection (Refer to Figure 16 below). The internal oscillator is required to be operating when using this converter, since the divided signal provided from the oscillator is used for the internal timing of this circuit.
C1+ C1C2+ VOUT
2X Boost Capacitors = 1uF~4.7uF
Figure 16 Capacitor Connections
7.4.2 Voltage Regulator Circuits
The voltage regulator determines the LCD driving voltage V0, by adjusting resistors Ra and Rb, within the range of |V0| < |VOUT|. Since VOUT is the operating voltage of the operational-amplifier circuits, it is necessary to be applied either internally or externally. For Equation 1, V0 is determined by Ra, Rb and VEV. Ra and Rb are connected internally or externally through the IRS pin. VEV which is the electronic volume voltage, is determined by Equation 2, where the parameter is the value selected by the instruction "Set Contrast Control Mode," within the range 0 to 63. VREF, a constant voltage source is 2 V at TA=25C.
Product Specification (V1.0) 12.28.2005
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EPL09060
9 COM/60 SEG LCD Driver
VOUT
V0
Rb VEV (Constant reference voltage + electronic volume) VR Ra
VSS
Figure 17 Resistor Connections
V 0 = (1 +
Rb ) x VEV .....................Equation 1 Ra (63 - ) ) x VREF ..........Equation 2 252
VEV = (1 -
Register Value (R2, R1, R0) (0, 0, 0)
1 + (Rb/Ra) 3.5
Refer to "Regulator Resistor Select" instruction for details.
D5 0 1 .. .. 62 63 0 0 . . 1 1 D4 0 0 . . 1 1 D3 0 0 . . 1 1 D2 0 0 . . 1 1 D1 0 0 . . 1 1 D0 0 1 . . 0 1
Refer to "Set Contrast Control Mode" instruction for details. Using Internal Resistors, Ra and Rb (IRS = "H") When the IRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. V0 is determined by using the two instructions, "Regulator Resistor Select" and "Set Reference Voltage".
24 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
Using External Resistors, Ra and Rb ( IRS = "L") When IRS pin is "L", it is necessary to connect the external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. For a particular liquid, the optimum VLCD can be calculated for a given multiplex rate. For a 1/9 duty ratio, the optimum operating voltage of the liquid can be calculated as:
VLCD =
1+ 9 1 2 x 1 - 9
x Vth = 3.464 x Vth
where Vth is the threshold voltage of the liquid crystal material used.
7.4.3 Voltage Follower Circuits
From the Voltage Regulator V0
V1 0.890xV0 0.880xV0 V2
Total Req = 4M
Switching Network V3 V4
0.120xV0 0.110xV0
Bypass Capacitor = 0.47uF~1uF
Figure 18 OTP Voltage Follower
The VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3, V4), and those output impedance are converted by the voltage follower (OPA) to increase the drive capability. Total 6 levels LCD reference voltage (V0, V1, V2, V3, V4, VSS) is generated by the voltage follower circuits.
LCD Bias 1/8 1/7.5 1/7 1/6.5 1/6 1/5.5 1/5 V1 0.875xV0 0.865xV0 0.855xV0 0.845xV0 0.835xV0 0.820xV0 0.800xV0 V2 0.750xV0 0.735xV0 0.715xV0 0.690xV0 0.665xV0 0.635xV0 0.600xV0 V3 0.250xV0 0.265xV0 0.285xV0 0.310xV0 0.335xV0 0.365xV0 0.400xV0 V4 0.125xV0 0.135xV0 0.145xV0 0.155xV0 0.165xV0 0.180xV0 0.200xV0 25
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
LCD Bias 1/4.5 1/4 1/3.5 1/3
V1 0.780xV0 0.750xV0 0.715xV0 0.665xV0
V2 0.555xV0 0.500xV0 0.430xV0 0.335xV0
V3 0.445xV0 0.500xV0 0.570xV0 0.665xV0
V4 0.220xV0 0.250xV0 0.285xV0 0.335xV0
Different duty radio requires different bias level. For optimum bias level, BL can be calculated using the following equation:
BL =
1 Duty ratio + 1
Changing the bias system from the optimum will have an effect on the contrast and viewing angle. The LCD Bias affects the display quality. But to reduce the current consumption, an unsuitable bias may be selected. Hence, the LCD Bias could be selected by "Select LCD bias" instruction.
7.4.4 Oscillator
The on-chip RC type oscillator provides the display clock and voltage converter timing clock. It has low power consumption and its frequency is nearly independent of VDD. When "CLS"="H", the oscillator circuit is enabled. When CLS="L", the oscillator is stopped, and the oscillator clock has to be input to the OSC pin.
RC Oscillator
To the Internal Circuit
CLS
OSC
Sleep Mode
Figure 19 RC Oscillator
7.4.5 Oscillator Frequency
The EPL09060 contains an RC oscillator. The frame frequency (fFM) is derived from the RC circuit's oscillation frequency (fOSC) by giving it an appropriate value. The relationship between the oscillation frequency (fOSC), display clock frequency (fCL) and the frame frequency (fFM) is shown below. The fOSC could be selected from an internal or external oscillator via the CLS pin, fCL could be selected via "Set display clock CL frequency" instruction, and frame frequency could be calculated using the following equation. fCL = (Duty ratio) x (Frame frequency)
26 * Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
7.5
Reset Circuit
When the /RES input comes to the "L" level, this LSI returns to its default state. The default settings are as follows: Display OFF Normal display ADC select: Normal (ADC select instruction D0 = "L") SHL select: Normal (SHL select instruction D3 = "L") Power Control Register: (D2, D1, D0) = (0, 0, 0) Serial interface internal register data clear Duty ratio = 1/43, (D3~D0) = (1, 1, 0, 1) CL frequency Register (D4, D3, D2, D1, D0) = (0, 0, 0, 0, 1, 1) LCD power supply bias level = (1/8), (D3~D0) = (1, 0, 1, 0) Entire display OFF (Entire display instruction D0 = "L") Power saving clear Modify-Read OFF Display initial line set to first line : 0 Column address set to Address : 0 Page address set to Page : 0 V0 voltage regulator internal resistor ratio set mode clear: (R2, R1, R0) = (0, 0, 0) Contrast control set mode clear Contrast control register : (D5, D4, D3, D2, D1,D0) = (1, 0, 0, 0, 0, 0)
NOTE After issuing the command "reset", the registers "Duty ratio" and "bias" must be set with a suitable value.
Product Specification (V1.0) 12.28.2005
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9 COM/60 SEG LCD Driver
8 Control Register
Instruction Read Display Data Write Display Data Read Status Set Duty Ratio Mode Duty Ratio Register Set CL frequency Mode CL frequency Register Set LCD Bias select Mode LCD Bias select Register Display On/Off Initial Display Line Set Contrast Control Mode Set Contrast Control Register Set Page Address Set Column Address MSB Set Column Address LSB A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Read Data Read data from DDRAM Write Data Write data into DDRAM 0 00 0 Read the internal status 00 10 0 Set duty ratio Mode ICO D2 D1 D0 Select the duty ratio * N 00 01 0 Set CL frequency Mode D4 D3 D2 D1 D0 Set CL frequency Register 00 10 1 Set LCD Bias select Mode * D3 D2 D1 D0 Select the LCD Bias Turn on/off LCD panel 01 1 1 Don When DON=0: display off When DON=1: display on 0 0 D2 D1 D0 Specify DDRAM line for COM0 00 00 1 Set Contrast Control Mode
1 * 1 * 1 * 1 0 1 * 1 0 0
Status 00 * 0 * 0 * 0 1 0 * 0 0 0 * 0 * 0 * 1 0 0
D5 D4 D3 D2 D1 D0 Set Contrast Control Register 1 0 0 Set page address DDRAM column address of 1 Higher 4-bits DDRAM column address of 0 lower 4-bits Select segment direction When ADC=0: normal direction 0 0 0 0 ADC (SEG0 SEG59) When ADC=1: reverse direction (SEG59 SEG0) Select normal/inverse display 0 0 1 1 REV 0 : Normal display 1 : Inverse display on Select normal/entire display ON 0 0 1 0 EON When EON=0: normal display. When EON=1: entire display ON 0 0 00 0 Set modify-read mode 0 1 11 0 Release modify-read mode 0 0 01 0 Initialize the internal functions Select COM output direction When SHL=0: normal direction (COM0 -> COM7) 0 SHL * * * When SHL=1: reverse direction (COM7 -> COM0) 0 1 VC VR VF Control power circuit operation Select internal resistance ratio 0 0 00 0 ofthe regulator resistor Compound instruction of display OFF and entire display ON 1 Page Address Higher order Column Add Lower order Column Add
ADC Select
0
1
0
1
0
1
Inverse Display ON/OFF
0
1
0
1
0
1
Entire Display ON/OFF Set Modify-read Reset Modify-read Reset
0 0 0 0
1 1 1 1
0 0 0 0
1 1 1 1
0 1 1 1
1 1 1 1
SHL Select
0
1
0
1
1
0
Power Control Regulator Resistor Select Power Save
Note: * : Don't care
0 0 -
1 0 -
0 0 -
0 0 -
0 0 -
1 1 -
28 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
Read Display Data The 8-bit data from the display data RAM specified by the column address and page address can be read by this instruction. As the column address is automatically incremented by 1 after each instruction execution, the microprocessor can continuously read data from the addressed page.
A0 1 /RD 0 /WR 1 D7 D6 D5 D4 D3 D2 D1 D0 Read Data
Write Display Data The 8-bit display data from the microprocessor can be written to the RAM location specified by the column address and page address. After writing the display data, the column address is automatically incremented so that the microprocessor can continuously write data to the addressed page.
A0 1 /RD 1 /WR 0 D7 D6 D5 D4 D3 D2 D1 D0 Write Data
Read Status This instruction reads out the internal status regarding "ADC select", "Display On/Off" and "Reset".
A0 0 /RD 0 /WR 1 D7 D6 ADC D5 D4 D3 0 D2 0 D1 0 D0 0 On/Off RESET
Flag
Description It shows the correspondence between the column address and segment drivers. ADC = 0 : Normal direction (SEG0 SEG59) ADC = 1 : Reverse direction (SEG59 SEG0) This bit indicates the ON/OFF state of the display. 0 : Display ON 1 : Display OFF Indicates that the initialization is in progress, by the RESETB signal. RESET = 0 : Normal display operation state RESET = 1 : Internal reset operation state with reset command.
ADC
On/Off
RESET
Set Duty Ratio (Two-Byte instruction) The first instruction sets the duty ratio mode, the second one updates the contents of the duty ratio register. After the second instruction, the set duty mode is released. The LSI cannot accept any instructions except the "Set duty ratio register" during the set duty ratio mode. Set Duty Ratio Mode (First Instruction)
A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 0
Product Specification (V1.0) 12.28.2005
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EPL09060
9 COM/60 SEG LCD Driver Set Duty Ratio Register (Second Instruction)
A0 /RD /WR D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 D1 0 0 1 1 0 0 D0 0 1 0 1 0 1 Duty Ratio 8 (+ICON) 16 (+ICON) 24 (+ICON) 32 (+ICON) 36 (+ICON) 42 (+ICON)
0
1
0
*
*
*
*
ICON
Note: "*" means "Don't care"
ICON: "0" Disable COMI (icon display) pin "1" Enable COMI (icon display) pin Set Display Clock CL Frequency (Two-Byte Instruction) The display clock CL affects the current consumption and the frame frequency affects the flicker, so fine adjustment is required for the display clock CL (internal) and the frame frequency. Set CL Frequency Select Mode (First Instruction)
A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0
Set CL Frequency Select Register (Second Instruction)
A0 /RD /WR D7 D6 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 * D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 * D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 * D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * CL Frquency fOSC fOSC / 2 fOSC / 3 fOSC / 4 fOSC / 5 fOSC / 6 fOSC / 7 fOSC / 8 fOSC / 9 fOSC / 10 fOSC / 11 fOSC / 12 fOSC / 13 fOSC / 14 fOSC / 15 fOSC / 16 fOSC / 32
0
1
0
*
*
*
Note: "*" means "Don't care"
Select LCD Bias (Two-Byte Instruction) This instruction selects the LCD bias ratio of the voltage required for driving the LCD. Set LCD Bias Select Mode (First Instruction)
A0 0 30 * /RD 1 /WR 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 1
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
Set LCD Bias select Register (Second instruction)
A0 /RD /WR D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 D1 0 0 1 1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 1 0 1 0 LCD Bias 1/3 1/3.5 1/4 1/4.5 1/5 1/5.5 1/6 1/6.5 1/7 1/7.5 1/8
0
1
0
*
*
*
*
Note: "*" means "Don't care"
Display ON/OFF This instruction is used to control the turning on or off of the LCD panel, regardless of the contents of the DDRAM.
A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 1 Display On or Off 0 :Off 1 :On
Initial Display Line This instruction sets the line address of the display RAM to determine the initial display line. The initial display line corresponds to COM0. The display area read from the display data RAM corresponds to the number of the lines set by the Duty select command.
A0 /RD /WR D7 D6 D5 D4 D3 D2 0 0 . . 1 1 D1 0 0 . . 1 1 D0 0 1 . . 0 1 Line Address for COM0 0 1 . . 6 7
0
1
0
0
1
0
0
0
Electronic Contrast Control Set (Two-Byte instruction) The first instruction sets the contrast control mode, the second one updates the contents of the contrast control register. After the second instruction, the contrast control mode is released. The LSI cannot accept any instructions except for the "Set Contrast Control Register" during the Contrast Control Mode. Set Contrast Control Mode (First instruction)
A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1
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9 COM/60 SEG LCD Driver
Set Contrast Control Register (Second instruction)
A0 0 /RD 1 /WR 0 D7 * D6 * D5 0 0 . . 1 1 D4 0 0 . . 1 1 D3 0 0 . . 1 1 D2 0 0 . . 1 1 D1 0 0 . . 1 1 D0 0 1 . . 0 1 Electronic Volume Value () 0 Minimum 1 . . 62 63
Set Page Address This instruction sets the page address of the display data RAM from the microprocessor into the page address register. It is possible to access any required bit in the display data RAM by specifying the page address and the column address. Along with the column address, the page address defines the address of the display RAM used to write or read the display data. Changing the page address does not affect the display status. Page 6 is assigned for the icon display. Only D0 is valid.
A0 /RD /WR D7 D6 D5 D4 D3 0 0 . . . . 0 D2 0 0 . . . . 1 D1 0 0 . . . . 1 D0 0 1 . . . . 0 Page Address 0 1 . . . . 6
0
1
0
1
0
1
1
Set Column Address This instruction sets the column address of the display data RAM from the microprocessor into the column address register. When accessing the display data RAM from the MPU, the column address is incremented. The incrementing of the column address is stopped at address 65H.
A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 0 D4 1 0 D3 0 A3 D2 0 A2 D1 A5 A1 D0 A4 A0 Column Address Setting Upper 4-bit Lower 4-bit
A5 0 0 . . 1 1
A4 0 0 . . 1 1
A3 0 0 . . 1 1
A2 0 0 . . 0 0
A1 0 0 . . 1 1
A0 0 1 . . 0 1
Column Address 0 1 . . 58 59
32 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
ADC Select This instruction selects the segment driver direction. Normal or reverse can be selected in the correlation between the display data RAM column address and the segment output terminal.
A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 1 Segment Driver Direction Normal Reverse
D0 = 0 Normal D0 = 1 Reverse
Column addresses 00H to 3BH corresponds to segment outputs 0 to 59. Column addresses 2AH to 65H corresponds to segment outputs 59 to 0.
Inverse Display ON/OFF This instruction is used to invert the display status on the LCD panel without rewriting the contents of the display data RAM.
A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 1 Display Status Normal Inverse
D0 = 0 Normal D0 = 1 Inverse Entire Display ON/OFF
Display data "1" makes the LCD on. Display data "0" makes the LCD on.
This instruction forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM will be retained. This instruction has priority over the Reverse Display On/Off instruction.
A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0 1 Entire display on/off Normal Entire display on
Set Modify-Read This instruction stops the automatic increment of the column address by the Read Display Data instruction, but the column address is still incremented by the Write Display Data instruction. This instruction can reduce the load of the MPU, during the display, the data in a specific DDRAM area is repeatedly changed for cursor blinking or others. This mode is canceled by the Reset Modify-read instruction.
A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0
Product Specification (V1.0) 12.28.2005
33
EPL09060
9 COM/60 SEG LCD Driver Reset Modify-Read This instruction cancels the Modify-read mode. The column address of the display data RAM returns to the address before the Read Modify Write is executed.
A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
Reset This instruction resets the initial display line, column address, page address, and the common output status is reset to their initial status, but does not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the /RES pin.
A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0
Reset status by "Reset" instruction: Read modify write off Initial display line address : (00)H Column address : (00)H Page address : (0) page SHL select : Normal mode (D3=0) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Sets contrast control set mode off and contrast control register : (20)H SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status.
A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 0 D4 0 D3 0 1 D2 * D1 * D0 * Common Driver Direction Normal Reverse
Note: "*" means "Don't care"
D3 =0 Normal D3 =1 Reverse
Normal direction (COM0 COM 7) (1/16duty ratio, Page 0) Reverse direction (COM7 COM 0) (1/16duty ratio, Page 1)
34 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
Power Control Selects one of eight power circuit functions by using the 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously.
A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 VC D1 VR D0 VF
VC: Voltage converter VR: Voltage regulator VF: Voltage follower 0: Off 1: ON Regulator Resistor Select Selects the resistance ratio of the internal resistor used in the internal voltage regulator. See the voltage regulator section in power supply circuit for more details.
A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 R2 D1 R1 D0 R0
R2 0
R1 0
R0 0
[Rb/Ra] Ratio 3.5
Power Save (Compound Instruction) The current consumption can be greatly reduced by entering the power save status and inputting the "Entire Display ON" instruction while the display is in OFF mode. According to the status in static indicator mode, power save is entered through one of two modes (sleep and standby mode). Power Save mode is released by the "Display ON" & "Entire Display OFF" instructions.
S tatic in d icato r O F F S tatic in d ica to r O N
P o w er save r (co m p ou n d co m m an d ) [ D is pla y O F F ] [ E n tire D isp la y O N ] S ta tic In d ica to r ON S leep m o d e R e set in stru ctio n P o w er S ave O F F ( C o m p o u nd Ins tru ctio n ) [ E n tire D isp lay O FF ] [ D is p lay O N ] [ S ta tic In d ica to r O N ] S tan d b y m o d e
P o w e r S ave O F F ( C om p o u nd In stru ctio n ) [ E n tire D isp lay O F F ] [ D is p lay O N ]
S leep m o d e c an cel
S ta nd b y m o d e can ce l
Product Specification (V1.0) 12.28.2005
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EPL09060
9 COM/60 SEG LCD Driver
Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the current consumption is reduced to a value near the static current. The internal modes during sleep mode are as follows: The oscillator circuit and the LCD power supply circuit are stopped. All liquid crystal drive circuits are stopped, as well as the segment and common driver output VSS level. When a "static indicator on" instruction is issued in the sleep mode, the LSI goes into the standby mode. Standby Mode All operations of the dynamic LCD display section are stopped, only the static display circuits for the indicators operate and hence the current consumption will be the minimum necessary for static drive. The internal conditions in the standby state are as follows: The power supply circuit for LCD drive is stopped. The oscillator circuit will still be operating. The LCD drive circuits for dynamic display are stopped and the segment and common driver outputs will be at the VSS level. The static display section will still be operating. When a reset instruction is issued in the standby mode, the LSI goes into a sleep mode.
36 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
9 Application Information
9.1 Instruction Procedure Examples
9.1.1 Initial Setup
(From power application to display ON using internal power supply circuits)
V D D -V S S P o w e r O N P o w e r S t a b iliz a t io n I n p u t R e s e t S ig n a l W a it f o r m o r e t h a n 2 0 m s I n it ia l s e t t in g s s t a t e ( d e f a u lt ) U s e r s e t t in g s v ia in s t r u c t io n in p u t ( 1 ) D U T Y s e le c t L C D b ia s s e le c t C L f r e q u e n c y s e le c t A D C s e le c t S H L s e le c t
U s e r s e t tin g s v ia c o m m a n d in p u t ( 2 ) C o n t r a s t c o n t r o l v o lu m e
U s e r s e t tin g s v ia c o m m a n d in p u t ( 3 ) P o w e r c o n tro l V C ,V R ,V F = (1 , 1 , 1 ) W a it in g f o r m o r e t h a n 3 0 0 m s t o s t a b iliz e t h e L C D p o w e r le v e ls
E n d o f in it ia l s e t t in g s
L C D d is p la y s c r e e n s e t tin g s D is p la y s t a r t lin e s e t W r it in g s c r e e n d a t a , e t c .
D is p la y O N
Product Specification (V1.0) 12.28.2005
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EPL09060
9 COM/60 SEG LCD Driver
The "Modify-read" sequence
Page address set
Column address set
Set modify-read
Dummy read Data read Data write No Change complete Yes End
The "External oscillator input" sequence
Set CL frequency select mode
Set CL frequency select register
Input the clock to OSC pin
End
38 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
PROGRAM EXAMPLES Use Elan Risc II MCU assembly ;************************************************************************** ; Initialization Setting Example of EPL09060
;**************************************************************************
INI_DRIVER_IC: MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL BS MOV CALL CALL MOV CALL CALL RET A,#LCD_COM_RESET WRITE_LCD_1BYTE A,#LCD_COM_DUTY WRITE_LCD_1BYTE A,#DUTY_SET WRITE_LCD_1BYTE A,#LCD_COM_BIAS WRITE_LCD_1BYTE A,BIAS_SET WRITE_LCD_1BYTE A,#LCD_COM_FREQ WRITE_LCD_1BYTE A,#CL_FREQ WRITE_LCD_1BYTE A,#LCD_ADC_SET WRITE_LCD_1BYTE A,#LCD_SHL_SET WRITE_LCD_1BYTE A,#LCD_REGULATOR_RES_SET WRITE_LCD_1BYTE A,#LCD_COM_CONTRAST WRITE_LCD_1BYTE A,#CONTRAST_SET WRITE_LCD_1BYTE A,#LCD_POWER_CONTROL_SET WRITE_LCD_1BYTE REG_CPUCON,F_CKS A,#150 WAIT_A_MS LCD_DISPLAY_ON A,#LCD_DISPLAY_INI_LINE WRITE_LCD_1BYTE LCD_DATA_WRITE ;WRITING SCREEN DATA ;TURN ON LCD ;SET INITIAL DISPLAY LINE ;ADD CLOCK BY OSC PIN (CLOCK FROM CPU) ;WAITING FOR LCD POWER TO STABILIZE ;SET POWER CONTROL (INTERNAL OR EXTERNAL) ;SET CONTRAST 2ND INSTRUCTION ;SET CONTRAST 1ST INSTRUCTION ;SET REGULATOR RESISTOR 1+(Rb/Ra) ;SET SHL FUNCTION SELECT ;SET ADC FUNCTION SELECT ;SET CL FREQUENCY 2ND INSTRUCTION ;SET LCD CL FREQUENCY 1ST INSTRUCTION ;SET BIAS 2ND INSTRUCTION ;SET LCD BIAS 1ST INSTRUCTION ;SET DUTY 2ND INSTRUCTION ;SET DUTY 1ST INSTRUCTION ;INITIAL SETTINGS STATE (DEFAULT)
Product Specification (V1.0) 12.28.2005
39
EPL09060
9 COM/60 SEG LCD Driver ************************************************************************************** ; Write Display_Picture Data into Display Data Ram of EPL09060
;************************************************************************************
DATA_WRITE: TBPTL TBPTM TBPTH #DISPLAY_PICTURE*2 #DISPLAY_PICTURE/0x80 #DISPLAY_PICTURE/0x8000 ;DEFINE DISPLAY PICTURE DATA INDEX
DATA_WRITE_09060: MOV MOV DATA_W1: MOV MOV BC MOV ADD CALL MOV CALL MOV CALL BS DATA_W2: TBRD CALL DEC JBS DEC JBS BC RET 01,REG_ACC WRITE_LCD_1BYTE REG_LCDARL REG_STATUS,F_C,DATA_W2 REG_LCDARH REG_STATUS,F_C,DATA_W1 REG_PORTB,F_LCD_A0 ;LCD /A0 = 0 FOR INSTRUCTION OUTPUT ;IDENTIFY RES_STATUS CARRY BIT SET OR NOT ;ACCESS THE DATA OF DISPLAY_PICTURE A,#LINE_X_MAX REG_LCDARL,A REG_PORTB,F_LCD_A0 A,#LCD_COM_PAGE A,REG_LCDARH WRITE_LCD_1BYTE A,#0b00000000 WRITE_LCD_1BYTE A,#0b00010000 WRITE_LCD_1BYTE REG_PORTB,F_LCD_A0 ;SET LCD /A0 = 1 DATA OUTPUT ;SET HIGHER ORDER COLUMN ADDRESS=0000 ;SET LOWER ORDER COLUMN ADDRESS=0000 ;SET LCD /A0 = 0 INSTRUCTION OUTPUT ;SET MAX SEGMENTS OF DDRAM A,#LINE_Y_MAX REG_LCDARH,A ;MAX PAGES OF DDRAM
40 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
;********************************************************************************* ; Write One Byte Data Into DDRAM (Parallel Mode 80 Series)
;*********************************************************************************
;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION WRITE WRITE_LCD_1BYTE: JBS BC MOV NOP REG_DCRG,F_LAHEN,WRITE_LCD_1BYTE_1 REG_PORTC,F_LCD_WR REG_DATA,A ;CHECK REG_DCRG LAHEN BIT=1 OR NOT ;SET /WR=0 ENABLE WRITE ;MOVE A==> PORT_G ;Write low pulse( Wait for ;2 instruction cycles) NOP BS NOP NOP NOP NOP RET WRITE_LCD_1BYTE_1: MOV RET REG_DATA,A ;MOVE A==> PORT_G REG_PORTC,F_LCD_WR ;SET /WR=1 DISABLE WRITE
;********************************************************************************* ;; Read One Byte Data Into DDRAM (Parallel Mode 80 Series)
;;*********************************************************************************
;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION READ READ_LCD_1BYTE: BC NOP NOP MOV NOP BS NOP RET REG_PORTB,F_LCD_RD ;SET /RD=1 DISABLE READ A,REG_DATA ;MOVE PORT_G ==> A REG_PORTB,F_LCD_RD ;SET /RD=0 ENABLE READ
Product Specification (V1.0) 12.28.2005
41
EPL09060
9 COM/60 SEG LCD Driver
9 Relationship between Setting and Common/Display RAM
The microprocessor (MPU) can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM simultaneously as data is being displayed without causing the LCD to flicker.
Page Address Data P3,P2,P1,P0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D0 ADC 0 0 0 0 =0 0 1 2 3 ADC =1 S E G M E N T 0 S E G M E N T 1 S E G M E N T 2 S E G M E N T 3 Column Address Line Common Common Common Common Output pins Output pins Output pins Address SHL=0 Output pins SHL=0 SHL=1 SHL=1 (HEX) (1/16) (1/8) (1/16) (1/8) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 COMI 3 8 2 D S E G M E N T 56 3 9 3 A 3 B 2 A S E G M E N T 59 000 210 COMI COM0 COM1 COM2 COM3 COM7 COM6 COM5 COM4 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
00
00
PAGE0
0001
PAGE1
0010
PAGE2
00
11
PAGE3
PAGE4
0
100
0101 0110 Column Address (HEX)
PAGE5 PAGE6
22 CB S E G M E N T 57 S E G M E N T 58
LCD Output
None segment
Note: 1. The data on Page Address 2~5 would not be output to the common pins, but can be regarded as general data RAM. 2. The EPL09060 will output RAM data (Page 0) to COM0 ~ COM7 (COMI) when using 1/16 (1/17) duty and SHL=0.
42 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
10 Absolute Maximum Ratings
Parameter Power supply voltage Driver supply voltage Input voltage Operating temperature range Storage temperature range Applicable Pins VDD VOUT All Input Symbol VDD VLCD VIN TA Condition Rate Value -0.3 to +7 -0.3 to +17 -0.3 to VDD+0.3 -30 to +80 C -55 to +125 Unit V
Recommended Operating Conditions
Parameter Power supply Voltage Voltage converter output voltage V0 output voltage Output voltage Applicable Pins VDD VOUT V0 Symbol VDD VOUT V0 VOH VOL VIH VIL TA Condition Min. 2.2 4.0 3.0 0.7VDD VSS 0.7VDD VSS 0 Rated Value Typ. Max. 3.4 6.8 6.0 VDD 0.3VDD VDD 0.3VDD 40 OC V Unit
Input voltage Operating temperature range
Product Specification (V1.0) 12.28.2005
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EPL09060
9 COM/60 SEG LCD Driver
11 DC Characteristics
VSS = 0V, VDD = 2.6 to 3.3V, TA = -30~80C
Parameter Power Supply Voltage Voltage Converter Input Voltage Reference Voltage Regulated Voltage OP Amp Voltage Output of LCD Power supply Voltage Converter Output Voltage LCD Driver ON Resistance Reset Resistor Output Current (Source and Drain) Input Leakage Current Output Tri-state Applicable Pins VDD VDD V0 V0 V1 V2 V3 V4
1
Symbol VDD VDD2 VREF0 VREF20 VREF40 V0 VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT RON RRESET IOH IOL IIL
Condition Min. 2.2 2 x boost TA=0C TA=20C TA=40C TA=0~40C 2.2
Rated Value Typ. 2.16 1.98 1.94 V0 V0 V1 V2 V3 V4 99 2 800 50 -4 2.2 Max. 3.4 3.4 2.25 2.05 2.02 V0+4%
Unit
2.07 1.96 1.86 V0-4%
V
No load
2 and 3
mV
VOUT COMn SEGn /RES
5 4
x 2 (no-load) Current load load= 50 A VDD=3V, Vin=0V VDD=3V, Vin=1.7V VDD=3V, VOH=2.4V VDD=3V, VOL=0.2V VIN=VDD or 0V VDD=3V, 2 boosting, TA=25C, internal OSC. fOSC=22kHz, 1/17 duty ratio,1/4.5 bias ratio, DV value=10H, regulator=(0, 0,0), CL=(0, 0, 0), all display pattern off, no load V0=3.6V, V1=2.4V (No load) VOH=2.8V V0=3.6V, V4=1.2V (No load) VOL=0.8V Standby mode Sleep mode TA=25C TA=25C
95 400 25 -3 1.2
100 5 1200 75 -5 3.2 1 3
%
k
mA
All Input
5
Dynamic Current Consumption (1/17 duty)
IDDD1
40
55
A 0.75 1
V1 Sink Capability
V1
Isv1
V4 Source Capability Current Consumption Current Consumption Frame Frequency Internal Oscillator Frequency External Input Oscillator
V4
Isv4 IDD1 IDD2 fFM
-0.75 17
-1 5 1 85 22 22
10 2 27 kHz
Hz
OSC
fOSC fOSC
44 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
Note :
2
1
V 0 = (1 +
(63 - ) Rb ) x VEV ; VEV = (1 - ) x VREF Ra 252
V0 V1 (7/8) x V0 (6.5/7.5) x V0 (6/7) x V0 (5.5/6.5) x V0 (5/6) x V0 (4.5/5.5) x V0 (4/5) x V0 (3.5/4.5) x V0 (3/4) x V0 (2.5/3.5) x V0 (2/3) x V0 V2 (6/8) x V0 (5.5/7.5) x V0 (5/7) x V0 (4.5/6.5) x V0 (4/6) x V0 (3.5/5.5) x V0 (3/5) x V0 (2.5/4.5) x V0 (2/4) x V0 (1.5/3.5) x V0 (1/3) x V0 V3 (2/8) x V0 (2/7.5) x V0 (2/7) x V0 (2/6.5) x V0 (2/6) x V0 (2/5.5) x V0 (2/5) x V0 (2/4.5) x V0 (2/4) x V0 (2/3.5) x V0 (2/3) x V0 V4 (1/8) x V0 (1/7.5) x V0 (1/7) x V0 (1/6.5) x V0 (1/6) x V0 (1/5.5) x V0 (1/5) x V0 (1/4.5) x V0 (1/4) x V0 (1/3.5) x V0 (1/3) x V0
:
LCD Bias 1/8 Bias 1/7.5 Bias 1/7 Bias 1/6.5 Bias 1/6 Bias 1/5.5 Bias 1/5 Bias 1/4.5 Bias 1/4 Bias 1/3.5 Bias 1/3 Bias
3: 4 5
The target value of V0~V4 is Theoretical Value 50 mV
: Input pin D0~D7, A0, /RD, /WR, /CS1, CS2, CLS, C86, IRS : Output pin D0~D7
12 AC Characteristics
/CS1, CS2
tCSS tCHS
A0
/WR (R/W)
tASS tCYCS tCLLS tDSS tCLHS tDHS tAHS
D6 (SCK) D7 (SDI)
tDDS
tOHS
D5 (SDO)
Product Specification (V1.0) 12.28.2005
45
EPL09060
9 COM/60 SEG LCD Driver
Serial Interface Timing Characteristics
Parameter Chip Select Setup Time Chip Select Hold Time Address Setup time Address Hold time Data Setup Time Data Hold Time Clock Cycle Time Clock L Time Clock H Time Data Delay Time Data Disable Time Applicable Pins /CS1 CS2 A0 R/W D7 (SDI) D6 (SCK) D5 (SDO) Symbol tCSS tCHS tASS tAHS tDSS tDHS tCYCS tCLLS tCLHS tDDS tOHS Condition Rated Value Min. 100 100 100 100 80 80 300 100 100 10 Max. 80 50 ns Unit
DATA SCK SCK DATA
CL= 100 pF
80-Family MPU Read/Write Timing Characteristics
(VSS= 0V, VDD= 2.6~3.3V, TA=0~40C)
tAH8
A0
/CS1 (CS2)
tAW8 tCC8
tCYC8
/WR,/RD
tDS8 tDH8
D0 to D7 (Write)
tACC8 tOH8
D0 to D7 (Read)
Parameter Address Setup Time Address Hold Time System Cycle Time Pulse Width(/WR) Pulse Width(/RD) Data Setup Time Data Hold Time Read Access Time Output Disable Time 46 *
Applicable pins A0 A0 /WR /RD
Symbol tAW8 tAH8 tCYC8 tCC8 tDS8 tDH8
Condition
Rated value Min. 0 0 500 160 200 20 10 10 Max. 60 40
Unit
ns
D0~D7
tACC8 tOH8
CL=100pF
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
68-Family MPU Read/Write Timing Characteristics (VSS = 0V, VDD = 2.6~3.3V, TA=0~40C)
tcyc6
E
tAW6 tEW
A0 R/W
tAH6
/CS1 (CS2)
tDS6 tDH6
D0 to D7 (Write)
tACC6 tOH6
D0 to D7 (Read)
Parameter Address Setup Time Address Hold Time System Cycle Time Pulse Width (/WR) Pulse Width (/RD) Data Setup Time Data Hold Time Read Access Time Output Disable Time
Applicable Pins A0 R/W A0 E
Symbol tAW6 tAH6 tCYC6 tEW tDS6 tDH6
Condition
Rated Value Min. 0 0 500 160 200 20 10 10 Max. 60 40
Unit
ns
D0~D7
tACC6 tOH6
CL=100pF
Product Specification (V1.0) 12.28.2005
47
EPL09060
9 COM/60 SEG LCD Driver
Input Pin Configuration
(VSS = 0V, VDD = 2.6V~3.3V, TA = 0~40C)
VDD
Input/Output Pin Configuration
VDD
Output data
Output enable
Input enable
48 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
Output Pin Configuration
VDD
Reset Input Pin Configuration
VDD
Product Specification (V1.0) 12.28.2005
49
EPL09060
9 COM/60 SEG LCD Driver
LCD Output Pin Configuration
V0
V0
V1 COMMON OUTPUT
SEGMENT OUTPUT
V2
V4
V3
VSS
VSS
MPU Interface Elan 8-bit MPU (with external memory)
VDD
VCC P O R T D _1 P O R T A,B P O R T D _4 P O R T D _5 R IS C 2 M P U PORT G P O R T D _2 P O R T D _3 /R E S GND
A0 /C S 1 CS2
VCC C 86 LCD PANEL
E P L 09 06 0 D 0 ~D 7 /R D /W R PS /R E S GND
VDD
/R E S E T
VDD
VCC /O E R /W /C E F L AS H
D 0 ~D 7 A0~An GND
50 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
Serial Interface (SPI)
VDD
VCC A0 PORT3_1 VDD MPU PORT2 PORT1 PORT0 /RES GND /RESET
A0 /CS1 CS2
VCC C86
VDD OR VSS LCD PANEL
EPL09060 SDI (D7) SCK (D6) SDO (D5) PS /RES GND
80-Family MPU
VDD
VCC
A0 A1~A7 /IORQ
A0 /CS1 CS2
VCC C86 EPL09060
DECODER
80 type MPU D0 ~D7 /RD /WR /RES GND
D0 ~D7 /RD /WR /RES GND
VDD
PS
/RESET
Product Specification (V1.0) 12.28.2005
51
EPL09060
9 COM/60 SEG LCD Driver
68-Family MPU
VDD
VCC
A0 A1~A15 VMA Decoder
A0 /CS1 CS2
VCC C86 EPL09060
VDD
68-Type MPU D0 ~D7 E R/W /RES GND
D0 ~D7 /RD /WR /RES GND
VDD PS
/RESET
52 *
Product Specification (V1.0) 12.28.2005
EPL09060
9 COM/60 SEG LCD Driver
13 Application Circuit
For customer application circuit
V DD COM I1 SEG 33 SEG 34 SEG 35 SEG 0 SEG 1
COM 0 COM 1 COM 2 COM 3 SEG 59
VDD VDD C 1+ C 1C 2+ V OU T V0 V1 V2 V3 V4 VR GN D GN D COM I2 COM 7 COM 6 CL S O SC COM 0 C S2 T EST PS /R ES /C S1 /W R /R D
1uF 1uF 1uF 1uF 1uF 1uF 1uF
E PL 09060
SEG 59
C 86
IRS
D0
/R ES
/C S1
CL S
C S2
IRS
SD O
A0
V DD
M CU
Product Specification (V1.0) 12.28.2005
GN D
SD I
SC K
SEG 52
D7
D6
D5
D4
D3
D2
D1
A0
SEG 0 COM 7 COM 6 COM 5 COM 4 COM I SEG 36 SEG 37 SEG 50 SEG 51
L CD
53
EPL09060
9 COM/60 SEG LCD Driver
54 *
Product Specification (V1.0) 12.28.2005

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