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EL9200, EL9201, EL9202
Data Sheet April 7, 2005 FN7438.0
Programmable VCOM
The EL9200, EL9201, and EL9202 represent programmable VCOM amplifiers for use in TFT-LCD displays. Featuring 1, 2, and 4 channels of VCOM amplification, respectively, each device features just a single programmable current source for adding offset to one VCOM output. This current source is programmable using a single wire interface to one of 128 levels. The value is stored on an internal EEPROM memory. The EL9200 is available in the 12-pin DFN package and the EL9201 and EL9202 are available in 24-pin QFN packages. All are specified for operation over the -40C to +85C temperature range.
Features
* 128 step adjustable sink current * EEPROM memory * 2-pin adjustment and disable * Single, dual or quad amplifiers - 44MHz bandwidth - 80V/s slew rate - 60mA continuous output - 180mA peak output * Up to 18V operation * 2.6V to 3.6V logic control * Pb-free available (RoHS compliant)
RF RG
Typical Block Diagram
Applications
* TFT-LCD VCOM supplies for - LCD-TVs - LCD monitors
AVDD
VS+
INN + VOUT INP GND AVDD R1 R2
VSD
CE
EEPROM
CTL
CONTROL
UP/DOWN COUNTER
ANALOG POT SET RSET
IOUT
GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL9200, EL9201, EL9202 Pinouts
EL9200 (12-PIN DFN) TOP VIEW EL9201 (24-PIN QFN) TOP VIEW
21 VINA+ 20 VINA24 VINA23 GND
EL9202 (24-PIN QFN) TOP VIEW
23 VINA+ 21 VINB+ 20 VINB19 VOUTB 18 VOUTC 17 VINCTHERMAL PAD 16 NC 15 VINC+ 14 GND 13 AVDD SET 10 IOUT 11 NC 12 CE 8 NC 9 22 VS+
24 NC
VINA- 1 GND 2 VINA+ 3 IOUT 4 AVDD 5 GND 6 THERMAL PAD
12 VS+ 11 VOUTA 10 SET 9 CE 8 CTL 7 VSD
NC 1 NC 2 VINB+ 3 IOUT 4 NC 5 AVDD 6 GND 7 NC 10 VSD 11 CTL 12 NC 8 NC 9 THERMAL PAD
22 NC
19 NC 18 VOUTA 17 VS+ 16 VOUTB 15 VINB14 SET 13 CE
VOUTA 1 VOUTD 2 VIND- 3 NC 4 VIND+ 5 AVDD 6 CTL 7
Ordering Information
PART NUMBER EL9200IL EL9200IL-T7 EL9200IL-T13 EL9200ILZ (See Note) EL9200ILZ-T7 (See Note) EL9200ILZ-T13 (See Note) EL9201IL EL9201IL-T7 EL9201IL-T13 PACKAGE 12-Pin DFN 12-Pin DFN 12-Pin DFN 12-Pin DFN (Pb-Free) 12-Pin DFN (Pb-Free) 12-Pin DFN (Pb-Free) 24-Pin QFN 24-Pin QFN 24-Pin QFN TAPE & REEL 7" 13" 7" 13" 7" 13" PKG. DWG. # MDP0047 MDP0047 MDP0047 MDP0047 MDP0047 MDP0047 MDP0046 MDP0046 MDP0046 PART NUMBER EL9201ILZ (See Note) EL9201ILZ-T7 (See Note) EL9201ILZ-T13 (See Note) EL9202IL EL9202IL-T7 EL9202IL-T13 EL9202ILZ (See Note) EL9202ILZ-T7 (See Note) EL9202ILZ-T13 (See Note) PACKAGE 24-Pin QFN (Pb-Free) 24-Pin QFN (Pb-Free) 24-Pin QFN (Pb-Free) 24-Pin QFN 24-Pin QFN 24-Pin QFN 24-Pin QFN (Pb-Free) 24-Pin QFN (Pb-Free) 24-Pin QFN (Pb-Free) TAPE & REEL 7" 13" 7" 13" 7" 13" PKG. DWG. # MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN7438.0 April 7, 2005
EL9200, EL9201, EL9202
Absolute Maximum Ratings (TA = 25C)
VS+ Supply Voltage between VS+ and GND . . . . . . . . . . . . . .18V Supply Voltage between VSD and GND . . . . . . . . . . . . . . . . . . . .4V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 65mA Input Voltages to GND SET, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V CTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V Output Voltages to GND OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V ESD Rating - HBM for Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER VS+ IS+ Supply Voltage
VSD = 3V, VS+ = 15V, AVDD = 15V, RSET = 24.9k, and TA = 25C unless otherwise specified CONDITION MIN 4.5 EL9200 EL9201 EL9202 3.8 7.6 10.5 3 2.6 TYP MAX 16.5 4.8 9.6 16 3.6 3.6 50 25 23 3 25 0.7*VSD 0.2*VSD 20 20 200 200 10 CTL = GND CTL = VSD 10 10 10 2.6V < VSD < 3.6V 2.6V < VSD < 3.6V (Note 1) 2.6V < VSD < 3.6V (Note 2) > 4.9V 1.6 1 4.9 200 100 Guaranteed by design Monotonic over-temperature 1000 1 15.75 0.4 0.8*VSD 0.3*VSD UNIT V mA mA mA V V A A mA mA A V V s s s s s A A pF V V ms V s ms cycles LSB
DESCRIPTION
Quiescent Current
VSD
Logic Supply Voltage
For programming For operation
ISD
Quiescent Logic Current
CE = 3.6V CE = GND Program (charge pump current) (Note 1) Read (Note 1)
IADD CTLIH CTLIL CTLIHRPW CTLILRPW CTLIHMPW CTLILMPW CTLMTC ICTL
Supply Current CTL High Voltage CTL Low Voltage CTL High Rejected Pulse Width CTL Low Rejected Pulse Width CTL High Minimum Pulse Width CTL Low Minimum Pulse Width CTL Minimum Time Between Counts CTL Input Current
Note 2 2.6V < VSD < 3.6V 2.6V < VSD < 3.6V
CTLCAP CEIL CEIH CEST CTLPROM CTLPT PT EEWC SETDN
CTL Input Capacitance CE Input Low Voltage CE Input High Voltage CE Minimum Start Up Time CTL EEPROM Program Voltage CTL EEPROM Programming Signal Time Programming Time EE Write Cycles SET Differential Nonlinearity
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FN7438.0 April 7, 2005
EL9200, EL9201, EL9202
Electrical Specifications
PARAMETER SETZSE SETFSE ISET SETER VSD = 3V, VS+ = 15V, AVDD = 15V, RSET = 24.9k, and TA = 25C unless otherwise specified CONDITION Note 3 Note 3 Through RSET (Note 1) To GND, AVDD = 20V (Note 1) To GND, AVDD = 4.5V (Note 1) AVDD to SET OUTST VOUT OUTVD AVDD to SET Voltage Attenuation OUT Settling Time OUT Voltage Range OUT Voltage Drift To 0.5 LSB error band (Note 1) (Note 1) (Note 1) VSET + 0.5V 10 2.25 1:20 20 13 10 MIN TYP MAX 2 8 120 200 45 UNIT LSB LSB A k k V/V s V mV
DESCRIPTION SET Zero-Scale Error SET Full-Scale Error SET Current SET External Resistance
AMPLIFIER CHARACTERISTICS INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN CMRR AVOL Input Offset Voltage Average Offset Voltage Drift (Note 1) Input Bias Current Input Impedance Input Capacitance Common-Mode Rejection Ratio Open-Loop Gain For VIN from -5.5V to +5.5V -4.5V VOUT +4.5V 50 60 VCM = 0V VCM = 0V 3 7 2 1 2 70 70 60 15 mV V/C nA G pF dB dB
OUTPUT CHARACTERISTICS VOL VOH ISC IOUT Output Swing Low Output Swing High Short-Circuit Current Output Current RL = 1.5k to 0 14.85 150 0.09 14.9 180 65 0.15 V V mA mA
POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS+ is moved from 4.5V to 15.5V 55 80 dB
DYNAMIC PERFORMANCE SR tS BW GBWP PM CS dG dP NOTES: 1. Simulated and determined via design and not directly tested 2. Tested at AVDD = 20V 3. Wafer sort only 4. NTSC signal generator used Slew Rate (Note 4) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation Differential Gain (Note 5) Differential Phase (Note 5) f = 5MHz (EL9201 & EL9202 only) RF = RG = 1k and VOUT = 1.4V RF = RG = 1k and VOUT = 1.4V -4.0V VOUT 4.0V, 20% to 80% (AV = +1), VOUT = 2V step 60 80 80 44 32 50 110 0.17 0.24 V/s ns MHz MHz dB %
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FN7438.0 April 7, 2005
EL9200, EL9201, EL9202
Pin Descriptions
PIN VINXIN/OUT Input DESCRIPTION Amplifier X inverting input, where: X = A for EL9200 X = A, B for EL9201 X = A, B, C, D for EL9202 EQUIVALENT CIRCUIT
VS+
GND CIRCUIT 1
VINX+
Input
Amplifier X non-inverting input, where: X = A for EL9200 X = A, B for EL9201 X = A, B, C, D for EL9202 Op amp supply; bypass to GND with 0.1F capacitor Amplifier X output, where: X = A for EL9200 X = A, B for EL9201 X = A, B, C, D for EL9202
Reference Circuit 1
VS+ VOUTX
Supply Output
VS+
GND CIRCUIT 2
GND
NC GND IOUT
Supply Output
No connect; not internally connected Ground connection Adjustable sink current output pin; the current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 128; see SET pin function description for the maxim adjustable sink current setting Maximum sink current adjustment point; connect a resistor from SET to GND to set the maximum adjustable sink current of the OUT pin; the maximum adjustable sink current is equal to (AVDD/20) divided by RSET Counter enable pin; connect CE to VDD to enable counting of the internal counter; connect CE to GND to inhibit counting Internal counter up/down control and internal EEPROM programming control input; if CE is high, a mid-to-low transition increments the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT; a mid-to-high transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage at OUT; applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-bit counter; see EEPROM Programming section for details analog voltage supply; bypass to GND with 0.1F capacitor System power supply input; bypass to GND with 0.1F capacitor
SET
Output
CE
Input
CTL
Input
AVDD VSD
Supply Supply
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FN7438.0 April 7, 2005
EL9200, EL9201, EL9202 Amplifier Typical Performance Curves
500 QUANTITY (AMPLIFIERS) VS=5V TA=25C TYPICAL PRODUCTION DISTRIBUTION 0.008 INPUT BIAS CURRENT (A) VS=5V
400
0.004
300
0
200
-0.004
100
-0.008
0 -8 -6 -4 -2 0 2 4 6 8 10 -12 -10 12 INPUT OFFSET VOLTAGE (mV)
-0.012 -50
-10
30
70
110
150
TEMPERATURE (C)
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
25 QUANTITY (AMPLIFIERS)
FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE
4.96 OUTPUT HIGH VOLTAGE (V)
VS=5V
20
TYPICAL PRODUCTION DISTRIBUTION
VS=5V IOUT=5mA
4.94
15
4.92
10
4.9
5
4.88
0 1 3 5 7 9 11 13 15 17 19 21 INPUT OFFSET VOLTAGE DRIFT, TCVOS (V/C)
4.86 -50
-10
30
70
110
150
TEMPERATURE (C)
FIGURE 3. INPUT OFFSET VOLTAGE DRIFT
2 INPUT OFFSET VOLTAGE (mV)
FIGURE 4. OUTPUT HIGH VOLTAGE vs TEMPERATURE
-4.85 OUTPUT LOW VOLTAGE (V)
VS=5V IOUT=5mA
1.5
-4.87
1
-4.89
0.5
-4.91
0
-4.93
-0.5 -50
-10
30
70
110
150
-4.95 -50
-10
30
70
110
150
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. INPUT OFFSET VOLTAGE vs TEMPERATURE
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
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FN7438.0 April 7, 2005
EL9200, EL9201, EL9202 Amplifier Typical Performance Curves
75 VS=5V RL=1k SLEW RATE (V/s) 78 77 76 75 74 73 60 -50 72 -50 VS=V
OPEN-LOOP GAIN (dB)
70
65
-10
30
70
110
150
-10
30
70
110
150
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 7. OPEN-LOOP GAIN vs TEMPERATURE
0 -0.02 DIFFERENTIAL GAIN (%) -0.04 -0.06 -0.08 -0.1 -0.12 -0.14 -0.16 -0.18 0 100 IRE 200 VS=5V AV=2 RL=1k
FIGURE 8. SLEW RATE vs TEMPERATURE
0.3 DIFFERENTIAL PHASE () 0.25 0.2 0.15 0.1 0.05 0
0
100 IRE
200
FIGURE 9. DIFFERENTIAL GAIN
-30 80
FIGURE 10. DIFFERENTIAL PHASE
250
DISTORTION (dB)
VS=5V AV=2 -40 R =1k L FREQ=1MHz -50 -60 -70 -80 -90 3rd HD GAIN (dB) 2nd HD
60 GAIN 40
190 PHASE ()
130
20
PHASE
70
0
10
0
2
4
6
8
10
-20 1K
10K
100K
1M
10M
-50 100M
VOP-P (V)
FREQUENCY (Hz)
FIGURE 11. HARMONIC DISTORTION vs VOP-P
FIGURE 12. OPEN LOOP GAIN AND PHASE
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FN7438.0 April 7, 2005
EL9200, EL9201, EL9202 Amplifier Typical Performance Curves
5 MAGNITUDE (NORMALIZED) (dB) MAGNITUDE (NORMALIZED) (dB) VS=5V AV=1 3 CLOAD=0pF 25 100pF 1000pF 47pF 5 10pF
1k
15
1
-1
150 560
-5
-3
-5 100K
1M
10M
100M
-15 VS=5V AV=1 RL=1k -25 100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS RL
400 350 OUTPUT IMPEDANCE () 300 250 200 150 100 50 0 10K 100K 1M FREQUENCY (Hz) 10M 100M
FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS CL
12 MAXIMUM OUTPUT SWING (VP-P) 10 8 6 4 VS=5V 2 AV=1 RL=1k DISTORTION <1% 0 10K 100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 15. CLOSED LOOP OUTPUT IMPEDANCE
-15
FIGURE 16. MAXIMUM OUTPUT SWING vs FREQUENCY
-80
PSRR+ PSRR-
VS=5V TA=25C
-25 CMRR (dB) PSRR (dB)
-60
-35
-40
-45
-55
-20
-65 1K
10K
100K
1M
10M
100M
0 100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. CMRR
FIGURE 18. PSRR
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FN7438.0 April 7, 2005
EL9200, EL9201, EL9202 Amplifier Typical Performance Curves
1K VOLTAGE NOISE (nV/Hz) -60 DUAL MEASURED CH A TO B QUAD MEASURED CH A TO D OR B TO C -80 OTHER COMBINATIONS YIELD IMPROVED REJECTION XTALK (dB) 1K 10K 100K 1M 100M -100
100
-120 VS=5V -140 RL=1k AV=1 VIN=110mVRMS -160 1K 10K
10
1 100
10M
100K
1M
10M 30M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. INPUT VOLTAGE NOISE SPECTRAL DENSITY
100 5
FIGURE 20. CHANNEL SEPARATION
OVERSHOOT (%)
60
STEP SIZE (V)
VS=5V AV=1 80 RL=1k VIN=50mV TA=25C
VS=5V AV=1 3 RL=1k 0.1% 1
40
-1 0.1% -3
20
0 10
100 LOAD CAPACITANCE (pF)
1K
-5 55
65
75
85
95
105
SETTLING TIME (ns)
FIGURE 21. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE
FIGURE 22. SETTLING TIME vs STEP SIZE
VS=5V TA=25C AV=1 RL=1k
VS=5V TA=25C AV=1 RL=1k
100mV STEP
1V STEP 50ns/DIV 50ns/DIV
FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE
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FN7438.0 April 7, 2005
EL9200, EL9201, EL9202 Amplifier Typical Performance Curves
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
4.5 4 POWER DISSIPATION (W)
1.2 POWER DISSIPATION (W) 1 0.8 0.6 0.4 0.2 0
3.5 3.378W 3 2.5 2 1.5 1 0.5 0 0 25 50 75 85 100 125 150
J
A=
893mW
QF N2 0
QF N2 37 4 C /W
JA =
14
4 C/ W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Application Information
This device provides the ability to reduce the flicker of an LCD panel by adjustment of the VCOM voltage during production test and alignment. A 128-step resolution is provided under digital control which adjusts the sink current of the output. The output is connected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing the output sink current. The adjustment of the output and the programming of the non-volatile memory are provided on one pin while the counter enable (CE) is provided on a separate pin. The output is adjusted via the CTL pin either by counting up with a mid to low transition or by counting down with a mid to high transition. Once the minimum or maximum value is reached on the 128 steps, the device will not overflow or underflow beyond that minimum or maximum value. An increment of the counter will increase the output sink current which will lower the voltage on the external voltage divider. A decrement of the counter will decrease the output sink current, which will raise the voltage on the external voltage divider. Once the desired output level is obtained, the part can store it's setting using the non-volatile memory in the device. See the non-volatile programming section for detailed information.
NOTE: Once the desired output level is stored in the EEPROM, the CE pin must go low to preserve the stored value.
Adjustable Sink Current Output
The device provides an output sink current which lowers the voltage on the external voltage divider. The equations that control the output are given below:
A VDD Setting I OUT = -------------------- x -------------------------20 ( R SET ) 128 R1 R2 Setting V OUT = -------------------- V AVDD 1 - -------------------- x -------------------------- 20 ( R SET ) 128 R 1 + R 2 NOTE: Where setting is an integer between 1 and 128.
7-Bit Up/Down Counter
The counter sets the level to the digital potentiometer and is connected to the non-volatile memory. When the part is programmed, the counter setting is loaded into the nonvolatile memory. This value will be loaded from the nonvolatile memory into the counter during power-on. The counter will not exceed its maximum level and will hold that value during subsequent increment requests on the CTL pin. The counter will not exceed its minimum level and will hold that value during subsequent decrement requests on the CTL pin.
CTL Pin
CTL should have a noise filter to reduce bouncing or noise on the input that could cause unwanted counting when the CE pin is high. The board should have an additional ESD protection circuit, with a series 1k resistor and a shunt 0.01F capacitor connected on the CTL pin. In order to increment the setting, pulse CTL low for more than 200s. The output sink current increases and lowers the VCOM lever by one least-significant bit (LSB). On the other hand, to decrement the setting, pulse CTL high for
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FN7438.0 April 7, 2005
EL9200, EL9201, EL9202
more than 200s. The output sink current will decrease and the VCOM level will increase by one LSB. To avoid unintentional adjustment, the EL9200, EL9201, and EL9202 guarantees to reject CTL pulses shorter than 20s. Since the internal comparators come up in an unknown state, the very first CTL pulse is ignored to avoid the possibility of a false pulse. See Figure 27 for the timing information.
TABLE 1. TRUTH TABLE INPUT CTL Mid to Hi Mid to Lo X > 4.9V X CE Hi Hi Lo X X VDD VDD VDD VDD VDD 0 to VDD SET Decrement Increment No Change No Change Read OUTPUT ICC Normal Normal Lower Increased Increased MEMORY X X X Program Read
NOTE: CE should be disabled (pulled low) before powering down the device to assure that the glitches and transients will not cause unwanted EEPROM overwriting.
CTLMTC CTL HIGH CTL VDD/2 CTL LOW CTLIHMPW CTLILMPW
CTLIHRPW
CTLILRPW
CE
COUNTER OUTPUT
UNDEF
78
79
7A
7B
7A
VCOM
FIGURE 27. VCOM ADJUSTMENT
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FN7438.0 April 7, 2005
EL9200, EL9201, EL9202 Non-Volatile Memory (EEPROM) Programming
When the CTL pin exceeds 4.9V, the non-volatile programming cycle will be activated. The CTL signal needs to remain above 4.9V for more than 200s. The level and timing needed to program the non-volatile memory is given below. It then takes a maximum of 100ms for the programming to be completed inside the device (see PT specification in Electrical Specification Table).
CTL VOLTAGE
Short-Circuit Current Limit
The amplifiers will limit the short circuit current to 180mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds 65mA. This limit is set by the design of the internal metal interconnects.
Output Phase Reversal
The amplifiers are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 28 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's over-voltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and over-voltage damage could occur.
1V 10s
4.9V
TIME CTLPT
FIGURE 28. EEPROM PROGRAMMING
Amplifiers' Operating Voltage, Input, and Output
The amplifiers are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most amplifier specifications are stable over both the full supply range and operating temperatures of -40C to +85C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The input common-mode voltage range of the amplifiers extends 500mV beyond the supply rails. The output swings of the those typically extend to within 100mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 27 shows the input and output waveforms for the device in the unity-gain configuration. Operation is from 5V supply with a 1k load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.8VP-P.
5V 10s
1V
VS=2.5V AV=1 TA=25C VIN=6VP-P
FIGURE 30. OPERATION WITH BEYOND-THE-RAILS INPUT
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane.
Power Supply Bypassing and Printed Circuit Board Layout
The amplifiers can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal operation a 0.1F ceramic capacitor should be placed from VS to pin to GND. A 4.7F tantalum capacitor should then be connected in parallel, placed in the region of the amplifier.
5V
AV=1 VS=5V TA=25C VIN=10VP-P
FIGURE 29. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT
12
OUTPUT
INPUT
FN7438.0 April 7, 2005
EL9200, EL9201, EL9202 Replacing Existing Mechanical Potentiometer Circuits
Figures 29 and 30 show the common adjustment mechanical circuits and equivalent replacement with the EL920X.
AVDD RA + VCOM EL9200 RC SET RSET AVDD RF RG
INVOUT IN+ OUT
AVDD R1 R2 VCOM
RB
R1 = RA R2 = RB + RC RA ( RB + RC ) R SET = ----------------------------------20R B FIGURE 31. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING EL9200
AVDD RX + VCOM
AVDD
RF
RG
INVOUT EL9200 IN+ OUT SET RSET
AVDD R1 R2 VCOM
RY
RZ
R1 = RX R2 = RZ RX ( RX + RY + RZ ) R SET = ------------------------------------------------20R Y FIGURE 32. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE EL9200
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FN7438.0 April 7, 2005
EL9200, EL9201, EL9202 QFN Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN7438.0 April 7, 2005

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