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EL5108, EL5308
Data Sheet June 15, 2006 FN7358.5
450MHz Fixed Gain Amplifiers with Enable
The EL5108 and EL5308 are fixed gain amplifiers with a bandwidth of 450MHz. This makes these amplifiers ideal for today's high speed video and monitor applications. They feature internal gain-setting resistors and can be configured in a gain of +1, -1 or +2. The same bandwidth is seen in both gain-of-1 and gain-of-2 applications. The EL5108 and EL5308 also incorporate an enable and disable function to reduce the supply current to 25A typical per amplifier. Allowing the CE pin to float or applying a low logic level will enable the amplifier. The EL5108 is offered in the 6 Ld SOT-23 and the industrystandard 8 Ld SO packages and the EL5308 is available in the 16 Ld SO and 16 Ld QSOP packages. All operate over the industrial temperature range of -40C to +85C.
Features
* Pb-free plus anneal available (RoHS compliant) * Gain selectable (+1, -1, +2) * 450MHz -3dB BW (AV = -1, +1, +2) * 3.5mA supply current per amplifier * Single and dual supply operation, from 5V to 12V * Available in SOT-23 packages * 350MHz, 1.5mA product available (EL5106 & EL5306)
Applications
* Battery powered equipment * Handheld, portable devices * Video amplifiers * Cable drivers * RGB amplifiers
Ordering Information
PART NUMBER EL5108IW-T7 EL5108IW-T7A EL5108IS EL5108IS-T7 EL5108IS-T13 EL5108ISZ (See Note) EL5108ISZ-T7 (See Note) r r 5108IS 5108IS 5108IS 5108ISZ 5108ISZ PART MARKING PACKAGE 6 Ld SOT-23 6 Ld SOT-23 8 Ld SO 8 Ld SO 8 Ld SO 8 Ld SO 8 Ld SO 8 Ld SO 16 Ld SO (0.150") 16 Ld SO (0.150") 16 Ld SO (0.150") 16 Ld QSOP 16 Ld QSOP 16 Ld QSOP 16 Ld QSOP (Pb-free) 16 Ld QSOP (Pb-free) 16 Ld QSOP (Pb-free) TAPE & REEL 7" (3K pcs) 7" (250 pcs) 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" PKG. DWG. # MDP0038 MDP0038 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040
EL5108ISZ-T13 (See Note) 5108ISZ EL5308IS EL5308IS-T7 EL5308IS-T13 EL5308IU EL5308IU-T7 EL5308IU-T13 EL5308IUZ (See Note) EL5308IUZ-T7 (See Note) EL5308IS EL5308IS EL5308IS 5308IU 5308IU 5308IU 5308IUZ 5308IUZ
EL5308IUZ-T13 (See Note) 5308IUZ
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2004, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL5108, EL5308 Pinout
EL5108 (8 LD SO) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 + 8 CE 7 VS+ 6 OUT 5 NC
EL5308 (16 LD SO, QSOP) TOP VIEW
INA+ 1 CEA 2 VS- 3 CEB 4 INB+ 5 + + 16 INA15 OUTA 14 VS+ 13 OUTB 12 INB11 NC + 10 OUTC 9 INC-
EL5108 (6 LD SOT-23) TOP VIEW
OUT 1 VS- 2 IN+ 3 6 VS+ 5 CE 4 IN-
NC 6 CEC 7 INC+ 8
+-
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FN7358.5 June 15, 2006
EL5108, EL5308
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . 13.2V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA Maximum Slewrate from VS+ to VS- . . . . . . . . . . . . . . . . . . . . 1V/s Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW -3dB Bandwidth
VS+ = +5V, VS- = -5V, RL = 150, TA = 25C unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
AV = +1 AV = -1 AV = +2
440 445 450 40 3500 4500 10 2
MHz MHz MHz MHz V/s ns nV/Hz pA/Hz %
BW1 SR tS eN iN dG dP
0.1dB Bandwidth Slew Rate 0.1% Settling Time Input Voltage Noise Input Current Noise Differential Gain Error (Note 1) Differential Phase Error (Note 1)
AV = +2 VO = -2.5V to +2.5V, AV = +2 VOUT = -2.5V to +2.5V, AV = +2
f = 2kHz AV = +2 AV = +2
12 0.01 0.01
DC PERFORMANCE VOS TCVOS AE RF, RG Offset Voltage Input Offset Voltage Temperature Coefficient Gain Error Internal RF and RG Measured from TMIN to TMAX VO = -3V to +3V, RL = 150 -8 +3 5 0.7 325 2.5 +8 mV V/C %
INPUT CHARACTERISTICS CMIR +IIN RIN CIN Common Mode Input Range + Input Current Input Resistance Input Capacitance at IN+ 3 3.3 2 0.7 1 8 V A M pF
OUTPUT CHARACTERISTICS VO Output Voltage Swing RL = 150 to GND RL = 1k to GND IOUT SUPPLY ISON ISOFF PSRR Supply Current - Enabled (per amplifier) No load, VIN = 0V 3.18 3.7 9 75 4.35 25 mA A dB Output Current RL = 10 to GND 3.6 3.8 100 3.8 4.0 135 V V mA
Supply Current - Disabled (per amplifier) No load, VIN = 0V Power Supply Rejection Ratio DC, VS = 4.75V to 5.25V
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FN7358.5 June 15, 2006
EL5108, EL5308
Electrical Specifications
PARAMETER ENABLE tEN tDIS IIHCE IILCE VIHCE VILCE NOTES: 1. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz 2. Measured from the application of the CE logic signal until the output voltage is at the 50% point between initial and final values Enable Time Disable Time (Note 2) CE Pin Input High Current CE Pin Input Low Current CE Input High Voltage for Power-down CE Input Low Voltage for Enable CE = VS+ CE = VS-1 +1 VS+ -1 VS+ -3 280 560 5 25 -1 ns ns A A V V VS+ = +5V, VS- = -5V, RL = 150, TA = 25C unless otherwise specified. (Continued) CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Pin Descriptions
EL5108 (SO8) 1, 5 2 4 EL5108 (SOT23-6) EL5308 (SO16, QSOP16) 6, 11 9, 12, 16 PIN NAME NC INFUNCTION Not connected Inverting input EQUIVALENT CIRCUIT
IN+
RG RF
IN-
CIRCUIT 1
3 4 6
3 2 1
1, 5, 8 3 10, 13, 15
IN+ VSOUT
Non-inverting input Negative supply Output
(Reference Circuit 1)
OUT RF
CIRCUIT 2
7 8
6 5
14 2, 4, 7
VS+ CE
Positive supply Chip enable
VS+
CE
VSCIRCUIT 3
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FN7358.5 June 15, 2006
EL5108, EL5308 Typical Performance Curves
5 NORMALIZED GAIN (dB)
VS=5V VIN=200mVP-P 3 RL=150 PHASE () 1 -1 -3 -5 100K AV = 2 AV = 1 AV = -1
135 45 -45 -135 -225
VS=5V VIN=200VP-P RL=150 AV = -1
AV = 2 AV = 1
1M
10M FREQUENCY (Hz)
100M
1G
-315 100K
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 1. FREQUENCY RESPONSE
FIGURE 2. PHASE RESPONSE
11 9 GAIN (dB) 7 5 3
VS=5V AV=2 RL=150 VOP-P = 400mV
11 9 GAIN (dB) 7 5 3
VS=5V AV=2
RL = 500 RL = 150
VOP-P = 2V
RL = 100 RL = 50
1 100K
1M
10M FREQUENCY (Hz)
100M
1G
1 100K
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 3. FREQUENCY RESPONSE vs OUTPUT VOLTAGE
FIGURE 4. FREQUENCY RESPONSE vs RL
11 9 GAIN (dB) 7 5 3
VS=5V AV=2 RL=150
CL = 6.8pF CL = 4.7pF DELAY (ns)
1.2 1 0.8 0.6 0.4 0.2
VS=5V RL=150
AV = -1 AV = 1
AV = 2
CL = 2.2pF CL = 0pF
1 100K
1M
10M FREQUENCY (Hz)
100M
1G
0 100K
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 6. GROUP DELAY vs FREQUENCY
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FN7358.5 June 15, 2006
EL5108, EL5308 Typical Performance Curves
(Continued)
15 -5 GAIN (dB) -25 -45 -65
100 AV=2 RL=150 IMPEDENCE () 10
1
0.1
0.01 0.002 10K
-85 100K
1M
10M FREQUENCY (Hz)
100M
1G
100K
1M FREQUENCY (Hz)
10M
100M
FIGURE 7. INPUT TO OUTPUT ISOLATION vs FREQUENCY (FOR DISABLE MODE)
FIGURE 8. OUTPUT IMPEDENCE vs FREQUENCY
1K
0 -10
VS=5V AV=2
VN (nV/Hz), IN (pA/Hz)
-20 PSRR (dB) 100 -30 -40 -50 -60 VN 1 100 1K 10K 100K 1M 10M -70 -80 1K 10K 100K 1M 10M 100M
IN 10
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 10. POWER SUPPLY REJECTION RATIO vs FREQUENCY
480 460 BANDWIDTH (MHz) 440 420 400 380 360 340 320
1.4 RL = 150 AV = 2 PEAKING (dB) 1.2 1 0.8 0.6 0.4
RL = 150
AV = -1 AV = 2 AV = 1
AV = -1 AV = 1
300 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 VS (V)
0.2 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 VS (V)
FIGURE 11. BANDWIDTH vs SUPPLY VOLTAGE
FIGURE 12. PEAKING vs SUPPLY VOLTAGE
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FN7358.5 June 15, 2006
EL5108, EL5308 Typical Performance Curves
(Continued)
-40 -50 -60 -70 -80 -90
DISTORTION (dB)
VS=5V AV=2 RL=150 VO=2VP-P
3.9 HD2 3.7 3.5 HD3 IS (mA) 3.3 3.1 2.9 2.7 2.5 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 VS (V) IS+, IS-
0
10
20
30
40
50
60
FREQUENCY (MHz)
FIGURE 13. DISTORTION vs FREQUENCY
FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE
VO=2V
VO=200mV
1V/DIV
100mV/DIV
10ns/DIV
10ns/DIV
FIGURE 15. LARGE SIGNAL RESPONSE
FIGURE 16. SMALL SIGNAL RESPONSE
M=100ns CH1 2.00V/DIV
M=100ns
CH1 2.00V/DIV
CH2 1.00V/DIV
CH2 1.00V/DIV
FIGURE 17. DISABLED RESPONSE
FIGURE 18. ENABLED RESPONSE
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FN7358.5 June 15, 2006
EL5108, EL5308 Typical Performance Curves
1 0.9 POWER DISSIPATION (W) 0.8 0.7 625mW 0.6 633mW 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 391mW SOT23-6 JA=256C/W QSOP16 JA=158C/W SO8 JA=160C/W
(Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.250W SO16 (0.150") JA=80C/W SO8 JA=110C/W
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 909mW POWER DISSIPATION (W) SO16 (0.150") JA=110C/W 1.4 1.2
1 909mW 0.8 893mW 0.6 435mW 0.4 0.2 0.1 0
SOT23-6 JA=230C/W 0 25 50 75 85
QSOP16 JA=112C/W 100 125 150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Applications Information
Product Description
The EL5108 and EL5308 are fixed gain amplifiers that offer a wide -3dB bandwidth of 450MHz and a low supply current of 3.5mA per amplifier. They work with supply voltages ranging from a single 5V to 10V and they are also capable of swinging to within 1.2V of either supply on the output. These combinations of high bandwidth, low power, and high slew rate make the EL5108 and EL5308 the ideal choice for many low-power/high-bandwidth applications such as portable, handheld, or battery-powered equipment. For varying bandwidth and higher gains, consider the EL5166 with 1GHz on a 9mA supply current or the EL5164 with 600MHz on a 3.5mA supply current. Versions include single, dual, and triple amp packages with 6 Ld SOT-23, 16 Ld QSOP, and 8 Ld or 16 Ld SO outlines.
Disable/Power-Down
The EL5108 and EL5308 amplifiers can be disabled and placing their outputs in a high impedance state. When disabled, the amplifier supply current is reduced to <25A. The EL5108 and EL5308 are disabled when the CE pin is pulled up to within 1V of the positive supply. Similarly, the amplifier is enabled by floating or pulling its CE pin to at least 3V below the positive supply. For 5V supply, this means that the amplifier will be enabled when CE is 2V or less, and disabled when CE is above 4V. Although the logic levels are not standard TTL, this choice of logic voltages allow the EL5108 and EL5308 to be enabled by tying CE to ground, even in 5V single supply applications. The CE pins can be driven from CMOS outputs.
Gain Setting
The EL5108 and EL5308 are built with internal feedback and gain resistors. The internal feedback resistors have equal value; as a result, the amplifier can be configured into gain of +1, -1, and +2 without any external resistors. Figure 21 shows the amplifier in gain of +2 configuration. The gain error is 2% maximum. Figure 22 shows the amplifier in gain of -1 configuration. For gain of +1, IN+ and IN- should be connected together as shown in Figure 23. This configuration avoids the effects of any parasitic capacitance on the IN- pin. Since the internal feedback and gain resistors change with temperature and process, external resistor should not be used to adjust the gain settings.
325 IN325 IN+ +
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Low impedance ground plane construction is essential. Surface mount components are recommended, but if leaded components are used, lead lengths should be as short as possible. The power supply pins must be well bypassed to reduce the risk of oscillation. The combination of a 4.7F tantalum capacitor in parallel with a 0.01F capacitor has been shown to work well when placed at each supply pin.
FIGURE 21. AV = +2
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FN7358.5 June 15, 2006
EL5108, EL5308
325 IN325 GND +
Video Performance
For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150, because of the change in output current with DC level. Previously, good differential gain could only be achieved by running high idle currents through the output transistors (to reduce variations in output impedance). Special circuitry has been incorporated in the EL5108 and EL5308 to reduce the variation of output impedance with current output. This results in dG and dP specifications of 0.01% and 0.01, while driving 150 at a gain of 2.
FIGURE 22. AV = -1
325 IN325 +
IN+
FIGURE 23. AV = +1
Output Drive Capability
In spite of its low 3.5mA of supply current per amplifier, the EL5108 and EL5308 are capable of providing a maximum of 130mA of output current.
Supply Voltage Range and Single-Supply Operation
The EL5108 and EL5308 have been designed to operate with supply voltages having a span of greater than or equal to 5V and less than 12V. In practical terms, this means that they will operate on dual supplies ranging from 2.5V to 5V. With single-supply, they will operate from 5V to 10V. As supply voltages continue to decrease, it becomes necessary to provide input and output voltage ranges that can get as close as possible to the supply voltages. The EL5108 and EL5308 have an input range which extends to within 2V of either supply. So, for example, on 5V supplies, the input range is about 3V. The output range is also quite large, extending to within 1V of the supply rail. On a 5V supply, the output is therefore capable of swinging from -4V to +4V. Single-supply output range is larger because of the increased negative swing due to the external pull-down resistor to ground. Figure 24 shows an AC-coupled, gain of +2, +5V single supply circuit configuration.
Driving Cables and Capacitive Loads
When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, the back-termination series resistor will decouple the EL5108 and EL5308 from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. In these applications, a small series resistor (usually between 5 and 50) can be placed in series with the output to eliminate most peaking.
Current Limiting
The EL5108 and EL5308 have no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device.
325 +5
Power Dissipation
With the high output drive capability of the EL5108 and EL5308, it is possible to exceed the 125C Absolute Maximum junction temperature under certain very high load current conditions. Generally speaking when RL falls below about 25, it is important to calculate the maximum junction temperature (TJMAX) for the application to determine if power supply voltages, load conditions, or package type need to be modified for the EL5108 and EL5308 to remain in the safe operating area. These parameters are calculated as follows:
T JMAX = T MAX + ( JA x n x PD MAX )
4.7F 325 +5 1K 0.1F VIN 1K +
VOUT
0.1F
FIGURE 24.
9
FN7358.5 June 15, 2006
EL5108, EL5308
where: TMAX = Maximum ambient temperature JA = Thermal resistance of the package n = Number of amplifiers in the package PDMAX = Maximum power dissipation of each amplifier in the package PDMAX for each amplifier can be calculated as follows:
V OUTMAX PD MAX = ( 2 x V S x I SMAX ) + ( V S - V OUTMAX ) x --------------------------RL
where: VS = Supply voltage ISMAX = Maximum supply current of 1A VOUTMAX = Maximum output voltage (required) RL = Load resistance
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FN7358.5 June 15, 2006
EL5108, EL5308 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
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FN7358.5 June 15, 2006
EL5108, EL5308 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY SYMBOL A A1 A2 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. E 3/00 NOTES: 1. Plastic or metal protrusions of 0.25mm maximum per side are not included.
E1 2 3
E
b c D
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). 6. SOT23-5 version has no center lead (shown as a dashed line).
(L1)
H
A
GAUGE PLANE c L 0 +3 -0
0.25
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FN7358.5 June 15, 2006
EL5108, EL5308 Quarter Size Outline Plastic Packages Family (QSOP)
A D N (N/2)+1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES A
PIN #1 I.D. MARK
0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16
0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24
0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28
Max. 0.002 0.004 0.002 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference
1, 3 2, 3 Rev. E 3/01
A1 A2 b c
E
E1
1 B 0.010 CAB
(N/2)
D E E1
e C SEATING PLANE 0.004 C 0.007 CAB b
H
e L L1 N NOTES:
L1 A c SEE DETAIL "X"
1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010 A2 GAUGE PLANE L 44 DETAIL X
A1
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN7358.5 June 15, 2006

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