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Rev 0; 9/06
I2C Programmable-Gain Amplifier for Audio Applications
General Description
The DS4420 is a fully differential, programmable-gain amplifier for audio applications. It features a -35dB to +25dB gain range controlled by an I2C interface and it is optimized to drive loads as low as 50. The gain is adjustable in 3dB increments across the entire range. Three address inputs, used to select the I 2 C slave address, enable up to eight devices on a common bus. The product operates from a single 5V supply over a -20C to +70C temperature range. It is offered in a 3mm x 3mm TDFN package. o Differential Inputs and Outputs o -35dB to +25dB Adjustable Gain o Low Output Noise o Low-Distortion Driving into a 50 Load o 3dB Gain Steps Programmed through I2C Interface o 5V Single Supply o 20kHz Bandwidth for All Gain Settings o Small 3mm x 3mm x 0.8mm TDFN Package o Up to Eight DS4420s can be Placed on the Same I2C Bus
Features
DS4420
Applications
Telephone Headsets Audio Volume Control Microphone Gain Control
Pin Configuration
TOP VIEW
A2 A1 A0 SCL SDA VCC GND 1 2 3 4 14 13 12 11 AVCC OUT+ OUTAGND N.C. ININ+
Ordering Information
PART DS4420+ TEMP RANGE -20C to +70C PIN-PACKAGE 14 TDFN-EP*
+ DS4420 TDFN (3mm x 3mm x 0.8mm)
MICROPR0CESSORCONTROLLED GAIN AUDIO SOURCE
+Denotes lead-free package. *EP = Exposed paddle.
5 6 7
10 9 8
Typical Operating Circuit
VCC SDA SCL A2 A1 A0
GND
AGND AVCC
I2C INTERFACE
OUT+ IN+ IN-35dB TO +25dB GAIN OUTAUDIO AMPLIFIER
DS4420
______________________________________________ Maxim Integrated Products
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I2C Programmable-Gain Amplifier for Audio Applications DS4420
ABSOLUTE MAXIMUM RATINGS
Voltage on VCC, SDA, and SCL Relative to GND.................................................-0.5V to +6.0V Voltage on A0, A1, and A2 Relative to GND ......................................-0.5V to (VCC + 0.5V; not to exceed 6.0V) Voltage on IN+, IN-, OUT-, and OUT+ Relative to AGND .................................-0.5V to (AVCC + 0.5V; not to exceed 6.0V) Voltage on AVCC Relative to VCC ..........................-0.3V to +0.3V Voltage on AGND Relative to GND .......................-0.3V to +0.3V Output Current ..................................................................150mA Operating Temperature Range ...........................-20C to +70C Storage Temperature .....................See J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -20C to +70C.)
PARAMETER Digital Supply Voltage Analog Supply Voltage Analog Ground Input Logic 1 (SCL, SDA, A0, A1, A2) Input Logic 0 (SCL, SDA, A0, A1, A2) SYMBOL VCC AVCC AGND VIH VIL (See Figure 5) 2.0 -0.3 (Note 1) CONDITIONS MIN +4.5 VCC GND VCC + 0.3 +0.8 TYP MAX +5.5 UNITS V V V V V
ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to +5.5V, TA = -20C to +70C, unless otherwise noted.)
PARAMETER Supply Current Standby Current Input Leakage (SDA, SCL, A2, A1, A0) Output Leakage (SDA) Output-Current Low (SDA) Input Voltage Range Max Peak-to-Peak Input Level Input Resistance Input Common-Mode Voltage Output Voltage Output Peak-to-Peak Signal Swing Output Common-Mode Voltage Output Offset Voltage Amplifier Output Current (Sourcing) SYMBOL ICC ISTBY IIL IL IOL VIN VINP-P RIN VIN:CM VO VOP-P VO:CM VO:OS IOS1 AV = +25dB VOUT = GND VOUT = VCC - 0.75V RL = 50 differential Differential 0.45 x VCC -20 95 64 0.5 x VCC VOL = 0.4V VOL = 0.6V Differential Differential Differential, active mode (Note 3) 29 0.45 x VCC 49 3 6 -19 +1 3.2 60 0.55 x VCC 6 5.6 0.55 x VCC +20 CONDITIONS VCC = 5.5V, RL = , VIN = 0V differential (Note 9) VCC = 5.5V (Notes 2, 9) VCC = 5.5V MIN TYP 1.7 MAX 3 140 1 1 UNITS mA A A A mA dBV V k V dBV V V mV mA
2
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I2C Programmable-Gain Amplifier for Audio Applications DS4420
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +4.5V to +5.5V, TA = -20C to +70C, unless otherwise noted.)
PARAMETER Amplifier Output Current (Sinking) Resistive Load Range Capacitive Load Closed-Loop Bandwidth Passband Flatness Output Noise (Note 5) NO SYMBOL IOS2 RL CL VOUT = VCC VOUT = 0.75V Differential Cap to GND (Note 4) All gain settings (Note 5) 20Hz to 20kHz (Notes 2, 5) A = -35dB, 300Hz to 3.4kHz A = +25dB, 300Hz to 3.4kHz RL = 50, VO +6dBV, f = 1kHz, A = 16dB Total Harmonic Distortion (Note 5) THD RL = 1k, VO +6dBV, f = 1kHz, A = 16dB Gain Range Gain Step Size Gain Accuracy Mute and Standby Mode Gain Standby Mode Exit Time A AS AERR1 AMUTE tPU (Note 10) (Note 5) (Note 6) -35 2.0 -2.5 3.0 0.01 +25 4.0 +2.5 -90 10 dB dB dB dB s 20 -1 -123 -88 0.03 1.0 % CONDITIONS MIN 89 64 50 50k 100 20k +1 TYP MAX UNITS mA pF Hz dB dBV
I2C AC ELECTRICAL CHARACTERISTICS (See Figure 3)
(VCC = +4.5V to +5.5V, TA = -20C to +70C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time Start Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB (Note 8) (Note 8) (Note 8) (Note 7) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF
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I2C Programmable-Gain Amplifier for Audio Applications DS4420
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative. Note 2: Standby supply current specified with SDA = SCL = VCC, the output disconnected, and A0, A1, and A2 driven to within 100mV of VCC or GND. Note 3: Input resistance during mute and power-down is approximately one-half of the active-mode resistance. Note 4: Each output is capable of driving a 100nF capacitive load to ground using an external 10 series resistor. However, output capacitance should be minimal for optimal distortion performance. Note 5: Guaranteed by design. Note 6: This is the time it takes for the output to become active after exiting standby mode. Note 7: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standardmode timing. Note 8: CB = total capacitance of one bus line in picofarads. Note 9: The current specified is the sum of VCC and AVCC supply currents. Note 10: Gain accuracy specified assuming the output impedance of signal source driving of the DS4420 is 2.5k.
Typical Operating Characteristics
(TA = +25C, VCC = AVCC = 5.0V, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (STANDBY MODE ENABLED)
DS4420 toc01
SUPPLY CURRENT vs. SUPPLY VOLTAGE (SETTING AT -11dB)
VCC = AVCC = SDA = SCL NO LOAD IN+ AND IN- SHORTED +25C TOGETHER
DS4420 toc02
SUPPLY CURRENT vs. GAIN SETTING
1.8 1.6 SUPPLY CURRENT (mA) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 IN+ AND IN- SHORTED TOGETHER NO LOAD 0 5 10 GAIN SETTING 15 20
DS4420 toc03
84 82 SUPPLY CURRENT (A) 80 78 76 74 72 70
SUPPLY CURRENT (mA)
VCC = AVCC = SDA = SCL NO LOAD +70C IN+ AND IN- SHORTED TOGETHER
1.8
2.0
+25C
1.7
-20C
1.6
-20C
1.5
+70C
1.4 4.50 4.75 5.00 5.25 SUPPLY VOLTAGE (V) 5.50 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V)
0
4
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I2C Programmable-Gain Amplifier for Audio Applications
Typical Operating Characteristics (continued)
(TA = +25C, VCC = AVCC = 5.0V, unless otherwise noted.)
POWER-SUPPLY REJECTION RATIO vs. GAIN SETTING
DS4420 toc04
DS4420
COMMON-MODE FREQUENCY RESPONSE SWEEP AT -11dB
DS4420 toc05
GAIN vs. FREQUENCY RESPONSE
50 LOAD +25dB SETTING 20 10 GAIN (dB) 0 -2dB SETTING -10 -20 -30 -40 -35dB SETTING
DS4420 toc06 DS4420 toc09
120 100 80 60 40 20 0 0 5 10 GAIN SETTING 15 20kHz 50 LOAD 1kHz 50 LOAD
0 -10 -20 CMRR (dB) -30 -40 -50 -60 -70 -80
NO LOAD
30
PSRR (dB)
20
1000
10,000 FREQUENCY (Hz)
100,000
1000
10,000
100,000
1,000,000
FREQUENCY (Hz)
GAIN vs. SETTING
DS4420 toc07
CCITT NOISE vs. GAIN SETTING
NO LOAD
DS4420 toc08
TOTAL HARMONIC DISTORTION vs. FREQUENCY
0.018 0.016 0.014 WITH 50 LOAD AND 1k LOAD 1VRMS INPUT -11dB SETTING
30 20 10 GAIN (dB) 0 -10 -20 -30 -40 0
IN+ AND IN- SHORTED TOGETHER ACROSS -20C TO +70C WITH 50 LOAD, 1k LOAD, AND NO LOAD
0 -20 CCITT NOISE (dBV) -40
0.012 -60 -80 -100 -120 -140 THD+N (%) 0.010 0.008 0.006 0.004 0.002 0.000 0 5 10 GAIN SETTING 15 20 10 100 1000 FREQUENCY (Hz) 10,000 100,000
5
10 GAIN SETTING
15
20
TOTAL HARMONIC DISTORTION vs. FREQUENCY
0.08 0.07 0.06 THD+N (%) 0.05 0.04 0.03 0.02 0.01 0.00 10 100 1000 FREQUENCY (Hz) 10,000 100,000 VOUT (dB) WITH 50 LOAD AND 1k LOAD 1VRMS INPUT +10dB SETTING
DS4420 toc10
TOTAL HARMONIC DISTORTION vs. VOUT
10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 2 4 6 8 10 12 14 16 18 20 GAIN SETTING THD+N
DS4420 toc11
0.09
50 LOAD 1kHz 2VRMS INPUT
0.020 0.018 0.016 0.014 THD+N (%) 0.012 0.010 0.008 0.006 0.004 0.002 0.000
VOUT
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I2C Programmable-Gain Amplifier for Audio Applications DS4420
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 EP NAME A2 A1 A0 SCL SDA VCC GND IN+ INN.C. AGND OUTOUT+ AVCC EP I2C Serial Clock--Input for I2C Clock I2C Serial Data--Input/Output for I2C Data Digital Power-Supply Terminal Ground Differential Audio Input Signal No Connection Analog Ground (Must be Connected to GND) Differential Audio Output Signal Analog Power Supply (Must be Connected to VCC) Exposed Paddle. Connect to GND and AGND. Address Select Inputs--Determine I2C Slave Address. Device address is 1010A2A1A0. FUNCTION
Detailed Description
The key features of the DS4420 are illustrated in the Block Diagram.
A0 A1 A2 VCC AVCC
Block Diagram
Controlling the DS4420
The DS4420 is controlled through the I2C serial interface. Gain, mute, and standby settings all reside in one control register located at memory address F8h (see Figure 1). Writes to other memory addresses are invalid.
SDA I2C INTERFACE SCL 3dB GAIN STEPS
DS4420
Programmable Gain The gain is adjustable from -35dB to +25dB in 3dB increments. The gain is determined by the five LSBs of the control register as shown in Figure 1. Gain settings greater than 14h are invalid. Mute Mode The DS4420 is placed in mute mode by setting the mute bit located in the control register (see Figure 1). When in this mode, the output of the amplifier is muted and is independent of the gain setting. The input-to-output attenuation is specified in the Electrical Characteristics table as AMUTE. Standby Mode Standby mode is entered by setting the standby control bit (see Figure 1). Setting the standby control bit mutes the output of the amplifier and places the DS4420 into a
IN+ IN-
-35dB TO +25dB GAIN
OUT+ OUT-
GND
AGND
low-current (I STBY ) consumption state. Unlike mute mode, however, standby mode is intended for use when no input signal is present. While in standby mode, the DS4420 maintains input and output common-mode bias voltages. The device produces no audible clicks or pops when entering or exiting the standby state. The time required for the output to become active when exiting standby mode is specified as tPU.
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I2C Programmable-Gain Amplifier for Audio Applications DS4420
Control Register (F8h) Power-Up Default: F8h Standby bit 7 1000 0000 b x Mute bit 4 bit 3 Gain Setting[4:0] bit 2 bit 1 bit 0
bit 7 bit 6 bit 5 bit 4:0
Standby: Places the DS4420 in standby mode. 0 = Normal operation. 1 = Places the DS4420 in standby mode. (Power-up default.) Don't care. Mute: Mutes the amplifier output, regardless of the current gain setting. 0 = Normal operation. (Power-up default.) 1 = Mutes the amplifier output. Gain Setting: Five-bit gain setting. The power-up default is setting 00h. GAIN SETTING (hex) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah GAIN (dB) -35 -32 -29 -26 -23 -20 -17 -14 -11 -8 -5 GAIN SETTING (hex) 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h to 1Fh GAIN (dB) -2 +1 +4 +7 +10 +13 +16 +19 +22 +25 Illegal
Figure 1. Control Register Description
Slave Address Byte and Address Pins
The slave address byte consists of a 7-bit slave address plus a R/W bit (see Figure 2). The DS4420's slave address is determined by the state of the A0, A1, and A2 address pins. These pins allow up to eight DS4420s to reside on the same I2C bus. Address pins connected to GND result in a `0' in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a `1' in the corresponding bit positions. For example, the DS4420's slave address byte is A0h when A0, A1, and A2 pins are grounded. I2C communication is described in detail in the I2C Serial Interface Description section.
MSB 1 0 1 0 A2 A1 A0 LSB R/W
SLAVE ADDRESS*
READ/WRITE BIT
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.
Figure 2. DS4420 Slave Address Byte
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I2C Programmable-Gain Amplifier for Audio Applications DS4420
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN). tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 3. I2C Timing Diagram
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe I2C data transfers. See the timing diagram (Figure 3) and the I2C AC Electrical Characteristics table for additional information. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start and stop conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states. Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition. Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition.
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Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one (done by releasing SDA) during the 9th bit. Timing (Figure 3) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition.
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I2C Programmable-Gain Amplifier for Audio Applications
Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a start condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS4420's slave address is determined by the state of the A0, A1, and A2 address pins as shown in Figure 2. Address pins connected to GND result in a `0' in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a `1' in the corresponding bit positions. When the R/W bit is 0 (such as in A0h), the master is indicating it will write data to the slave. If R/W is set to a 1, (A1h in this case), the master is indicating it wants to read from the slave. If an incorrect (nonmatching) slave address is written, the DS4420 will assume the master is communicating with another I2C device and ignore the communication until the next start condition is sent. Memory Address: During an I2C write operation to the DS4420, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
DS4420
I2C Communication Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a stop condition. The master must read the slave's acknowledgement during all byte write operations. Reading a Single Byte from a Slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. A dummy write cycle can be used to force the address pointer to a desired location. To do this, the master generates a start condition, writes the slave address byte (R/W =0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/W = 1), reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. See Figure 4 for I2C communication examples.
Applications Information
Power-Supply Decoupling
The DS4420 has separate supply voltages for its analog and digital circuitry. For best noise and distortion performance, place a 0.1F or 0.01F capacitor from VCC to GND and from AVCC to AGND. These capacitors should be placed as close as possible to the supply and ground pins of the device.
COMMUNICATIONS KEY S START A ACK NOT ACK X X X X X WHITE BOXES INDICATE THE MASTER IS CONTROLLING SDA NOTE 1: ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. P STOP REPEATED START N SHADED BOXES INDICATE THE SLAVE IS CONTROLLING SDA X X X 8-BITS ADDRESS OR DATA NOTE 2: THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT.
Sr
WRITE THE GAIN SETTING S 10 1 0 A2 A1 A0 0 A 11 1
F8h 11 F8h A 11 1 11 0 0 0 A Sr 10 1 0 A 2 A1 A0 1 A REGISTER SETTING N P 0 0 0 A REGISTER SETTING A P
READ THE GAIN SETTING S 10 1 0 A2 A1 A0 0
Figure 4. I2C Communication Examples
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I2C Programmable-Gain Amplifier for Audio Applications DS4420
Exposed Paddle
The DS4420 exposed paddle is not electrically isolated. It must be soldered to ground for proper operation.
Internal Ground Connections
The DS4420's ground pins, GND and AGND, must be connected together externally. Internally, they are connected as shown in Figure 5.
Input-Coupling Capacitors
The DS4420 is designed to be operated with an ACcoupled input signal. The input resistance, RIN, is sufficiently large to allow the use of small and inexpensive external capacitors. The input resistance combined with the AC-coupling capacitor will create a highpass filter. The -3dB cutoff frequency of the highpass, fC, is given by: fC = 1 2 x CIN x RIN
13 TYPICAL
GND
AGND
where CIN is the external coupling capacitor and RIN is the internal input resistance. At the cutoff frequency, the input signal will be attenuated 3dB, with less attenuation as the signal's frequency increases beyond the cutoff frequency. To guarantee passband flatness, the cutoff frequency of the filter should be designed using the specified minimum input resistance, and placed well below the desired flat band of the circuit. The typical input resistance should only be used to estimate typical performance.
Figure 5. Internal Ground Connections
Chip Topology
TRANSISTOR COUNT: 5347 SUBSTRATE CONNECTED TO: Ground
Package Information
For the latest package outline information, go to www.maximic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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