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| (R) ISO 9001 Registered Process C3017 CMOS 3m 10 Volt Analog Mixed Mode Electrical Characteristics T=25oC Unless otherwise noted N-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Voltage Symbol VTN N N LeffN WN BVDSSN VTFP(N) Minimum 0.6 42 2.85 12 12 Typical 0.8 0.6 47 3.2 0.7 Maximum 1.0 52 3.55 Unit V V1/2 A/V2 m m V V Comments 100x4m 100x4m 100x100m 100x4m Per side P-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Voltage Symbol VTP P P LeffP WP BVDSSP VTFP(P) Minimum -0.6 13 2.85 -12 -12 Typical -0.8 0.55 15 3.2 0.9 Maximum -1.0 19 3.55 Unit V V1/2 A/V2 m m V V Comments 100x4m 100x4m 100x100m 100x4m Per side Diffusion & Thin Films Well (field) Sheet Resistance N+ Sheet Resistance N+ Junction Depth P+ Sheet Resistance P+ Junction Depth Gate Oxide Thickness Interpoly Oxide Thickness Gate Poly Sheet Resistance Bottom Poly Sheet Res. Metal-1 Sheet Resistance Metal-2 Sheet Resistance Passivation Thickness Capacitance Gate Oxide Metal-1 to Poly-1 Metal-1 to Silicon Metal-2 to Metal-1 Poly-1 to Poly-2 Symbol P-well(f) N+ xjN+ P+ xjP+ TGOX TP1P2 POLY1 POLY2 M1 M2 TPASS Symbol COX CM1P CM1S CMM CP1P2 Minimum 3.2 16 50 44 15 15 Typical 4.8 21 0.8 80 0.7 48 60 22 22 50 30 200+900 Typical 0.72 0.0523 0.30 0.0384 0.57 Maximum 6.5 27 100 52 30 30 Unit K/ / m / m nm nm / / m/ m/ nm Unit fF/m2 fF/m2 fF/m2 fF/m2 fF/m2 Comments P-well oxide+nit. Comments Minimum 0.66 0.26 0.033 0.51 Maximum 0.78 0.34 0.041 0.63 (c) IMP, Inc. 91 Process C3017 Physical Characteristics Starting Material Starting Mat. Resistivity Typ. Operating Voltage Well Type Metal Layers Poly Layers Contact Size Via Size Metal-1 Width/Space Metal-2 Width/Space Gate Poly Width/Space P <100> 15 - 25 -cm 10V P-well 2 2 2.0x2.0m 2.0x2.0m 3.5 / 2.5m 5.0 / 3.0m 4.0 / 2.5m N+/P+ Width/Space N+ To P+ Space Contact To Poly Space Contact Overlap Of Diffusion Contact Overlap Of Poly Metal-1 Overlap Of Contact Metal-1 Overlap Of Via Metal-2 Overlap Of Via Minimum Pad Opening Minimum Pad-to-Pad Spacing Minimum Pad Pitch 3.0 / 3.0m 12m 2.5m 1.5m 1.0m 1.0m 1.75m 1.5m 100x100m 5.0m 80.0 m Special Feature of C3017 Process: P-well analog process with double metal CMOS 3.0 m technology. Second metal VIA Metal 1 Poly gate A1 SIO2 LTO p+ n+ n+ SIO2 p+ p+ n+ Field Oxide source Drain N- substrate contact Sidewall spacer Bottom poly p-well contact p-well n-epi N+ substrate Cross-sectional view of the C3017 process ID vsVD, W/L = 20/4.0 5 VGS = 10V ID vsVD, W/L = 20/4.0 -3 Drain Current (mA) IDS VGS = 8.0V Drain Current (mA) IDS 4 VGS = 9.0V -2.5 -2 3 VGS = 7.0V VGS = 6.0V VGS = -9.0V -1.5 VGS = -8.0V VGS = -7.0V 2 VGS = 5.0V VGS = 4.0V VGS = 3.0V VGS = 2.0V -1 VGS = -6.0V VGS = -5.0V 1 -.5 VGS = -4.0V VGS = -3.0V VGS = -2.0V 0 0 1 2 3 4 5 6 7 8 9 10 0 0 1 2 3 4 5 6 7 8 9 10 Drain Voltage (v) VDS n-ch Transistor IV characteristics of a 20/4.0 device Drain Voltage (v) VDS p-ch Transistor IV characteristics of a 20/4.0 device 92 C3017-4-98 Poly gate VGS = -10V Source Contact Drain p p p |
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