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| (R) ISO 9001 Registered Process C1004 CMOS 1.0m 5 Volt Digital Electrical Characteristics N-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Symbol VTN N N LeffN WN BVDSSN VTFP(N) Minimum 0.55 74 0.60 7 10 Typical 0.75 0.60 87 0.75 0.8 T=25oC Unless otherwise noted Maximum Unit Comments 0.95 V 100x1.0m V1/2 100x1.0m 100 A/V2 100x100m 0.90 m 100x1.0m m Per side V V P-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Voltage Symbol VTP P P LeffP WP BVDSSP VTFP(P) Minimum -0.85 24 0.83 -7 -10 Typical -1.0 0.4 28 0.98 0.85 Maximum -1.15 32 1.13 Unit V V1/2 A/V2 m m V V Comments 100x1.0m 100x1.0m 100x100m 100x1.0m Per side Diffusion & Thin Films Well (field) Sheet Resistance N+ Sheet Resistance N+ Junction Depth P+ Sheet Resistance P+ Junction Depth Gate Oxide Thickness Field Oxide Thickness Poly Sheet Resistance Metal-1 Sheet Resistance Metal-2 Sheet Resistance Passivation Thickness Symbol N-well(f) N+ xjN+ P+ xjP+ TGOX TFIELD POLY M1 M2 TPASS Minimum 0.8 20 60 15 Typical 1.0 35 0.45 80 0.5 20 700 22 50 30 200+900 Maximum 1.22 50 100 30 Unit K/ / m / m nm nm / m/ m/ nm Comments n-well oxide+nit. Capacitance Gate Oxide Metal-1 to Poly1 Metal-1 to SIlicon Metal-2 to Metal-1 Symbol Cox CM1P CMIS CMM Minimum 1.52 Typical 1.64 0.046 0.028 0.038 Maximum 1.82 Unit fF/m2 fF/m2 fF/m2 fF/m2 Comments (c) IMP, Inc. 17 Process C1004 Physical Characteristics Starting Material Starting Mat. Resistivity Typ. Operating Voltage Well Type Metal Layers Poly Layers Contact Size Via Size Metal-1 Width/Space Metal-2 Width/Space Gate Poly Width/Space P <100> 7-8.5 -cm 5V N-well 2 1 1.2x1.2m 1.2x1.2m 1.4 / 1.2m 2.0 / 1.4m 1.0 / 1.4m N+/P+ Width/Space N+ To P+ Space Contact To Poly Space Contact Overlap Of Diffusion Contact Overlap Of Poly Metal-1 Overlap Of Contact Metal-1 Overlap Of Via Metal-2 Overlap Of Via Minimum Pad Opening Minimum Pad-to-Pad Spacing Minimum Pad Pitch 2.0 / 1.2m 7.0m 0.8m 0.7m 0.7m 0.7m 0.7m 0.7m 65x65m 5.0m 80.0m Metal 2 Metal 1 SIO2 LTO LTO n+ p+ Field Oxide n+ p+ p+ n+ p- substrate contact Poly gate Poly gate Source Source Drain N-well contact N-well p-epi p+ substrate Sidewall spacer ID vs VD, W/L = 20/1.2 35.0 VGS = 5.0V -15.0 ID vs VD, W/L = 20/1.2 VGS = -5.0V Drain Current (mA) IDS Drain Current (mA) IDS 28.0 VGS = 4.0V -12.0 VGS = -4.0V -9.0 21.0 VGS = 3.0V 14.0 VGS = 2.0V 7.0 VGS = 1.0V 0 0 1.0 2.0 3.0 4.0 5.0 Drain Voltage (V) VDS N-ch Transistor IV Characteristics of a 20/1.2 device -6.0 Channel stop Contact Drain LDD p p VGS = -3.0V -3.0 VGS = -2.0V 0 -1.0 -2.0 -3.0 -4.0 -5.0 0 Drain Voltage (V) VDS P-ch Transistor IV Characteristics of a 20/1.2 device 18 C1004-4-98 |
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