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Features
* Hardware
- ATSTK94 Onboard Features Programmable Switches, LEDs and Alphanumeric Displays Two RS232 Compatible Serial Ports Multiple Clocks (4 MHz, 18.432 MHz, 32.768 kHz and Manual) 2-wire Serial Interface for Communication Easy Access to all FPSLIC Pins via Headers Push Button AVR and FPSLIC Reset - Supports both Drop-In and In-System Programming (ISP) - Runs Off Portable 9V DC Power Supply - Designed to Work with Atmel System DesignerTM 1.0 or Above * Software - Atmel's System Designer Atmel's AVR Studio(R) Atmel's Configurator Programming System (CPS) Co-verification, Powered by Mentor Graphics Exemplar's LeonardoSpectrumTM Model TechnologyTM's ModelSim(R) Several C Compiler Evaluation Copies - Atmel's Integrated Development System (IDS) - FPGA Place & Route Tool - Supports Windows(R) 95/98/2000/Me and WindowsNT(R) - Online Help * Contents - ATSTK94 Starter Kit Board with 1 Configurator - ATDH2225 Programming Dongle with 10-pin Ribbon Cable - 9V DC, 200 mA, 2.1 mm Center Positive Power Supply - Atmel System Designer CD with Evaluation License (4 Months) - Detailed User Guide including Complete Board Schematics - Software Tutorial and Sample Designs on Floppy Disk
Starter Kit
Programmable SLI ATSTK94
Description
Atmel's AT94K Starter Kit (ATSTK94) allows designers to, quickly and economically, evaluate Atmel's family of AT94K Field Programmable System Level Integrated Circuit (FPSLIC) devices and AT17 FPSLIC Configuration Memory devices. The ATSTK94, see Figure 1, board connects to any x86 PC via the parallel port through a 10-pin header cable to program the AT17 FPSLIC Configuration EEPROM, which in turn programs the AT94K FPSLIC device. A truly portable solution, which allows engineers to prototype and develop designs from their lab bench or office.
Rev. 2309B-FPSLI-01/02
1
Figure 1. ATSTK94 FPSLIC Starter Kit Board
Switches
Jumpers LEDs
UART0
UART1
Power Socket
Programming Switch
Configurator Header Power LED
Alphanumeric Displays
Configurator Socket
Power Switch
Reset Switch
2
ATSTK94
2309B-FPSLI-01/02
ATSTK94
Switches, LEDs, and Alphanumeric Displays
Program and Run Switch
The user configures each Programmable Switch or LED for use, with either the FPGA or AVR portion of the FPSLIC device. Furthermore, some switches may be configured for use as AVR External Interrupts allowing simulation of external events. The board features four Alphanumeric Displays which are connected to I/O pins of the embedded AT40KAL FPGA core. The Program and Run Switch controls the connection from the download cable to the Configurator and the Configurator to the FPSLIC. In the PROG position you can use the download cable and CPS to program the configuration memory with your FPSLIC Bitstream file generated by System Designer. In the Run position the FPSLIC device will load the Bitstream file and run your design. If the design does not start, you can use the RESET button with JP19 in the RESET position to force a reconfiguration of the device. In the Run position, the configurator will boot the FPSLIC device with the current program.
ISP and Reset Connections
There are 2 device reset connections in the FPSLIC device. The AVR RESET will reset the AVR and start from the reset vector in the interrupt table. RESET will cause the whole device to reset and reboot from the Configurator. SW12 is used to perform the reset. Jumper 19 is used to determine whether it will be an AVR reset or a full device reset, see Table 1. If you have logic RESET signal in your design, you cannot use SW12 to perform this reset; you should use one of the switches SW 1 - 8 to perform your design reset. Your design reset can be connected to any User IO on the FPGA side of FPSLIC. If you are using SW1 - 8, then you should use Pin locks to assign the correct user IO for the correct Switch. Table 1. Reset Connections
RESET RESET AVR RESET Source SW12 SW12 Pin 108 48 Hardware Settings JP19 Set to RESET (Default) JP19 Set to AVR RESET
Button/Switch Connections
The jumpers, located next to the buttons/switches control the button/switch connections, see Table 2. The left side of the jumpers are connected to LEDs, the right side of the jumpers are connected to Switches. The A and F markings indicate a connection to the AVR or the FPGA. When you press the switch it generates a "1".
3
2309B-FPSLI-01/02
Table 2. Switch Connections
Switch SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 Destination FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO AVR Interrupt INTP0 AVR Interrupt INTP1 AVR Interrupt INTP2 AVR Interrupt INTP3 AVR PortE PE0 AVR PortE PE1 AVR PortE PE2 AVR PortE PE3 Pin 202 198 192 188 180 176 172 168 135 145 146 152 109 110 113 122 Hardware Settings Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to A Jumper Set to A Jumper Set to A Jumper Set to A Jumper Set to A Jumper Set to A Jumper Set to A Jumper Set to A
LED Connections
The jumpers, located next to the LEDs, control the LED connections. Alternate jumpers connect to the switches, see Table 3, and to the LEDs. A white line on the silk screen indicates whether the jumper is for LED or the Switch. With the A F text the right way up the left most Jumper is for the LED 1. The A and F markings indicate a connection to the AVR or the FPGA. When you drive a "1" to the LED it will light. Table 3. LED Connections
LED L1 L2 L3 L4 L5 L6 L7 L8 L1 L2 L3 Source FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO AVR PortD PD0 AVR PortD PD1 AVR PortD PD2 Pin 200 196 190 186 178 174 170 166 111 112 114 Hardware Settings Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to F Jumper Set to A Jumper Set to A Jumper Set to A
4
ATSTK94
2309B-FPSLI-01/02
ATSTK94
Table 3. LED Connections
LED L4 L5 L6 L7 L8 Source AVR PortD PD3 AVR PortD PD4 AVR PortD PD5 AVR PortD PD6 AVR PortD PD7 Pin 120 121 126 127 134 Hardware Settings Jumper Set to A Jumper Set to A Jumper Set to A Jumper Set to A Jumper Set to A
Alphanumeric Connections
There are 4 digits of Alphanumeric on the board. The connections to the Alphanumeric are shared between both bits on the same device, see Table 4. This means that Bit 0 and Bit 1 share connections, and Bit 2 and Bit 3 share connections for all the segments, see Figure 2. The difference in connection is in the cathode connection that selects between the 2 digits. The cathodes should be driven with a 1/10 Duty Cycle and a 0.1 ms Pulse Width, see Table 5. Table 4. Alphanumeric Connections
LED 0 Anode A Anode B Anode C Anode D Anode E Anode F Anode G Anode H Anode J Anode K Anode L Anode M Anode N Anode P Anode D.P. Cathode Bit 1 Cathode Bit 2 Source FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO Pin 94 98 97 93 81 82 87 89 91 88 86 83 92 84 95 85 96 LED 1 Anode A Anode B Anode C Anode D Anode E Anode F Anode G Anode H Anode J Anode K Anode L Anode M Anode N Anode P Anode D.P. Cathode Bit 1 Cathode Bit 2 Source FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO FPGA User IO Pin 73 80 76 72 59 60 66 69 70 68 65 61 71 63 74 64 75
5
2309B-FPSLI-01/02
Figure 2. LEDs
LED 1 LED 0
Bit 3
Bit 2
Bit 2
Bit 0
Table 5. ASCII Code Table
Value 0 1 2 3 4 5 6 7 8 9 a b c d e f . * DP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 N 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 M 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 K 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 J 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 G 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 F 1 0 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 0 E 1 0 1 0 0 0 1 0 1 0 1 1 1 1 1 1 0 0 D 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 C 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 B 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 A 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 0 0
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ATSTK94
2309B-FPSLI-01/02
ATSTK94
RS232-compatible UARTs
UART Connections
The RS232-compatible UARTs allow for communication between the two on-board UARTs through the null-modem cable. It is also possible for communication between the UARTs and other devices, such as your PC, by using a simple terminal program. The 2 UART connections, see Table 6, are made to DB9 connectors. Printf commands are sent out on UART 0. Table 6. UART Connections
UART UART 0 UART 0 UART1 UART1 Source /Destination RX0 TX0 RX1 TX1 Pin 140 141 149 150 Hardware Settings Connect Cable to UART0 Connect Cable to UART 0 Connect Cable to UART 1 Connect Cable to UART 1
Multiple Clocks
There are multiple clock circuits on the Starter Kit. A Manual Clock or the 4 MHz Oscillator are connected to 2 of the FPGA Global Clock pins. The 32,768 KHz (for the implementation of the Real Time Clock calculations), 4 MHz, or 18.432 MHz can be used to drive the AVR. The FPGA has 8 Global Clocks, 2 of these (GCLK5 and GCLK6) can also be driven from the AVR system Clock. GCLK6 can alternatively be driven from the Watchdog timer or one of the timer counters. For full details on the Clock circuits in the FPSLIC device please refer to the AT94K datasheet available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc1138.pdf. Table 7. Clock Connections
Frequency Manual Clock Available Global Clocks Destination FPGA GCLK7 FPGA FPGA FPGA FPGA FPGA FPGA GCLK1 GCLK2 GCLK3 GCLK4 GCLK7 GCLK8 Pin 162 4 47 57 100 162 204 147 138 None For Rev2 - JP17 towards side of board, JP18 is unconnected. For Rev3 and beyond -Position of JP17 is changed, it is aligned with FPGA and AVR jumpers. JP17 is connected towards the inner side of the board, JP18 is unconnected. For Rev2 - JP17 towards middle of board, JP18 connected. For Rev3 and beyond - Position of JP17 is changed, it is aligned with FPGA and AVR jumpers. JP17 is connected towards the edge of the board, JP18 is connected. Hardware Settings Use MAN CLK Switch (SW9) to Pulse Clock
32,768 KHz Crystal 4 MHz Oscillator
AVR TOSC 1 AVR System Clock
18.432 MHz Crystal
AVR System Clock
138
7
2309B-FPSLI-01/02
2-wire Serial Interface
The 2-wire Serial Interface is the protocol from which the FPSLIC device receives configuration data from the AT17LV010 Configuration Memory. The maximum size of an AT94K40 design is approximately 800 kbits, thus leaving approximately 200 kbits of unused space. By using the 2-wire Serial Interface, it is possible to use the unused 200 kbits as external data storage memory. * * * * * * ATSTK94 Starter Kit User Guide (Supplied with ATSTK94) AT94K Series datasheet, available at http://www.atmel.com/atmel/acrobat/doc1138.pdf. AT94K Series Configuration application note, available at http://www.atmel.com/atmel/acrobat/doc2313.pdf. AT17LV010 datasheet, available at http://www.atmel.com/atmel/acrobat/doc0944.pdf. Programming Specification for Atmel's Configuration EEPROMs, available at http://www.atmel.com/atmel/acrobat/doc0437.pdf. Additional application notes found on the Atmel web site, at http://www.atmel.com/atmel/products/prod183.htm.
Related Documents
8
ATSTK94
2309B-FPSLI-01/02
XTAL1_138
C
Label OSC and XTAL
3
1
2309B-FPSLI-01/02
D B A
Clock Circuits
Board Schematics
5
4
3
2
1
VCC
U11 1 8 N/C VCC GND OUT 4 5
D
GCK4_100
4 MHz Osc SOCKETED DIP8
JP17 3JUMPER
2 TOSC1_147 C23 27 pF Y1 18.432 MHz JP18 C16 27 pF R21 10M Y2 32,768 Hz
C
XTAL2_139
1
2 JUMPER C17 33 pF R22 TOSC2_148 200K C24 33 pF
VCC
B
R23 330 ohm
SW9 GCK7_162
C18 10 nF
R3 1K ATMEL CORPORATION Title: Clock Circuits
A
ATSTK94
Size: A
Document Number: CHW5454 Sheet 1 of 8
1
Rev: 4
Date: Wednesday, June 27, 2001
5 4 3 2
9
Alphanumeric Display Circuits
10
5 4 3 2 1
ATSTK94
2309B-FPSLI-01/02
D U9 E_59 M_61 L_65 K_68 J_70 D_72 DP_74 C_76 1 2 3 4 5 6 7 8 9 +E +M nc +L +K +J +D +DP +C +F +P -1 +G +H +N +A -2 +B 18 17 16 15 14 13 12 11 10 F_60 P_63 1_64 G_66 H_69 N_71 A_73 2_75 B_80
D
LPT3784G01
U10 C E_81 M_83 L_86 K_88 J_91 D_93 DP_95 C_97 1 2 3 4 5 6 7 8 9 +E +M nc +L +K +J +D +DP +C +F +P -1 +G +H +N +A -2 +B 18 17 16 15 14 13 12 11 10 F_82 P_84 1_85 G_87 H_89 N_92 A_94 2_96 B_98 C
LPT3784G01
Green Display Modules
B
B
A
ATMEL CORPORATION Title: Alphanumeric Display Circuits Size: A Document Number: CHW5454 Sheet 2 of 8 1 Rev: 4
A
5
4
3
Date: Wednesday, June 27, 2001 2
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
PIN61 PIN60 PIN59 PIN58 PIN57 PIN56 PIN55 PIN54 PIN53 PIN52 PIN51 PIN50 PIN49 PIN48 PIN47 PIN46 PIN45 PIN44 PIN43 PIN42 PIN41 PIN40 PIN39 PIN38 PIN37 PIN36 PIN35 PIN34 PIN33 PIN32 PIN31 PIN30 PIN29 PIN28 PIN27 PIN26 PIN25 PIN24 PIN23 PIN22 PIN21 PIN20 PIN19 PIN18 PIN17 PIN16 PIN15 PIN14 PIN13 PIN12 PIN11 PIN10
GCK8
GND
VCC GND
GND
0.1
uF U1
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
C
Add labels to connectors every 10 pins. Labels should match chip pin numbers up to 208.
M0_50
B
NC NC VCC M2 GCK3(I/O) HDC(I/O) I/O I/O I/O LDC(I/O) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT)I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GCK4(I/O) GND NC CON NC
PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13 PIN14 PIN15 PIN16 PIN17 PIN18 PIN19 PIN20 PIN21 PIN22 PIN23 PIN24 PIN25 PIN26 PIN27 PIN28 PIN29 PIN30 PIN31 PIN32 PIN33 PIN34 PIN35 PIN36 PIN37 PIN38 PIN39 PIN40 PIN41 PIN42 PIN43 PIN44 PIN45 PIN46 PIN47 PIN48 PIN49 PIN50 PIN51 PIN52
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
GND GCK1
GND FCK1
GND VCC
FCK2 GND
OTS GCK2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 0.1 uF
NC NC NC VCC GCK8(I/O) I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O CS1(I/O) I/O I/O GCK7(I/O) I/O GND I/O NC NC
NC GND NC GCK1(I/O) I/O I/O I/O I/O I/O I/O I/O I/O I/O GND FCK1(I/O) I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O FCK2(I/O) GND I/O I/O I/O I/O I/O I/O I/O I/O OTS(I/O) GCK2(I/O) AVRRESET GND M0 NC NC
AT94K40-25DQC
NC NC VCC CCLK INTP3 D0 TX1 RX1 TOSC2 TOSC1 INTP2 INTP1 NC NC GND TX0 RX0 XTAL2 XTAL1 NC NC INTP0 PD7 PE7 PE6 GND VCC PE5 PE4 PD6 PD5 SCL SDA CS0 PE3 PD4 PD3 NC NC NC NC NC PD2 PE2 PD1 PD0 PE1 PE0 RESET NC VCC NC
156 155 VCC 154 153 152 151 150 149 148 147 146 145 144 143 GND 142 141 140 139 138 137 136 135 134 PE7 133 PE6 132 GND 131 VCC 130 PE5 129 PE4 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 VCC 105
VCC
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
CON52 AVRRESET_48 VCC
VCC
C4 0.1 uF E_81 F_82 M_83 P_84 1_85 L_86 G_87 K_88 H_89 J_91 N_92 D_93 A_94 DP_95 2_96 C_97 B_98 CON_103 GCK4_100 RESET_108 PE0_109 PE1_110 PD0_111 PD1_112 PE2_113 PD2_114 PD3_120 PD4_121 PE3_122 SDA_124 SCL_125 PD5_126 PD6_127 PD7_134 PE7_133
GCK3 HDC
GND
A
PIN10 PIN11 PIN12 PIN13 PIN14 PIN15 PIN16 PIN17 PIN18 PIN19 PIN20 PIN21 PIN22 PIN23 PIN24 PIN25 PIN26 PIN27 PIN28 PIN29 PIN30 PIN31 PIN32 PIN33 PIN34 PIN35 PIN36 PIN37 PIN38 PIN39 PIN40 PIN41 PIN42 PIN43 PIN44 PIN45 PIN46 PIN47 PIN48 PIN49 PIN50 PIN51 PIN52 PIN53 PIN54 PIN55 PIN56 PIN57 PIN58 PIN59 PIN60 PIN61
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
VCC GND
GCK4
E_59 F_60 M_61 P_63 1_64 L_65 G_66 K_68 H_69 J_70 N_71 D_72 A_73 DP_74 2_75 C_76 INIT_77 B_80
M2_56
VCC
2309B-FPSLI-01/02
D
FPSLIC Connections
5
4
3
2
1
52 Pin Connectors are double rows of Probe pins, 26 x 2 on each side of the chip.
CON52
D
SW1_202 LED1_200 SW2_198 LED2_196 SW3_192 LED3_190 SW4_188 LED4_186
SW5_180 LED5_178 SW6_176 LED6_174 SW7_172 LED7_170 SW8_168 LED8_166 GCK7_162 GND C2 0.1 uF
VCC C1
CCLK_153 INTP3_152 D0_151 TX1_150 RX1_149 TOSC2_148 TOSC1_147 INTP2_146 INTP1_145 TX0_141 RX0_140 XTAL2_139 XTAL1_138 INTP0_135 CON52
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
PIN61 PIN60 PIN59 PIN58 PIN57 PIN56 PIN55 PIN54 PIN53 PIN52 PIN51 PIN50 PIN49 PIN48 PIN47 PIN46 PIN45 PIN44 PIN43 PIN42 PIN41 PIN40 PIN39 PIN38 PIN37 PIN36 PIN35 PIN34 PIN33 PIN32 PIN31 PIN30 PIN29 PIN28 PIN27 PIN26 PIN25 PIN24 PIN23 PIN22 PIN21 PIN20 PIN19 PIN18 PIN17 PIN16 PIN15 PIN14 PIN13 PIN12 PIN11 PIN10
C
B
A
ATMEL CORPORATION
CON52
Title: FPSLIC Connections Size: C Document Number: CHW5454 Date: Wednesday, June 27, 2001
5 4 3 2
ATSTK94
Rev: 4 Sheet 3 of 8
1
11
ISP and Reset Circuits
150 R7
2
1
1
C19
3
12
4 3 2 1 VCC VCC VCC D R4 2K7 PE7_133 VCC SCL_125 SDA_124 CCLK_153 D0_151 CON_103 INIT_77 10-pin header from ATDH2200 J1 VCC C R5 2K7 R6 2K7 JP20 17 14 5 7 10 AT17C010_2J SOCKET PLCC20 D3 R20 2.7k 1N4001 SER_ENPE7 VCC CEO/A2 CLK WP1 DATA WP2 CE RESET/OE GND READY U12 20 4 2 8 6 15 1 3 5 7 9 1 3 5 7 9 2 4 6 8 10 HDR2X5 U5_ISP 2 4 6 8 10 AVR AVRRESET_48 JP19 Label as shown if possible DEVICE 10 9 8 7 RESET_108 6 5 4 3 2 1 SW 4PDT Need a 3-channel switch, single item. Close to program Configurator. Clock and Data need to be isolated to allow programming without removinng the cable. SER_EN pulled low to program. B 12 SW10 11 ATMEL CORPORATION Title: ISP and Reset Circuits Size: A Document Number: CHW5454 Sheet 4 of 8 3 1 Rev: 4 A 4 Date: Wednesday, June 27, 2001 2
5
D
ATSTK94
VCC
R11 4.7K
JP21 JP22 JP23
VCC
C
VCC
2
B
0.1 uF
SW12
Label RESET
A
5
2309B-FPSLI-01/02
R8 R7 R6 R5 R4 R3 R2 R1 COM
9 8 7 6 5 4 3 2 1
D
1
LED
3
3
1
1
LED
3
LED
3
1
LED
B
3
1
LED
3
1
LED
3
1
1
LED
3
2309B-FPSLI-01/02
5 4 3 2 1
LED Circuits
8 RESNET
U6 150R Code 151 GREEN LED same style as Starter Kit LEDs
JP1
LED1_200
D
L1
2
PD0_111
JP2
LED2_196
L2
2
LED
PD1_112
JP3
For Silk screen do not label too many jumpers. Indicate function of jumper by connecting line as shown.
LED3_190
L3
C
2
LED0 PD2_114
JP4
swjmp0 ledjmp0 cap
sw0
C
LED4_186
L4
2
PD3_120
JP5
LED5_178
L5
2
PD4_121
JP6
B
LED6_174
L6
2
PD5_126
JP7
LED7_170
L7
2
PD6_127
JP8
A
LED8_166
ATMEL CORPORATION Title: LED Circuits
L8
A
2
PD7_134
Size: A Document Number: CHW5454 Date: Wednesday, June 27, 2001 Sheet 5 of 8
1
Rev: 4
ATSTK94
5
4
3
2
13
Power Circuits
+ DCPOWER9V 500 mA C22 100 uF
ADJ
1
14
5 4 3 2 1
ATSTK94
2309B-FPSLI-01/02
D
D
Power Socket as on Motherboard P3
Swicth as on Motherboard On Off SW14 1 SPDT 2 3 1N4001
VCC
C
D4 3
LM317T1
IN OUT
3.3V 2 R8 2.2K C20 1 uF R10 3.3K + L10 LED R9 330
C
C21 0.1uF
B
Red LED for Power
B
A
Title: Power Circuits Size: A
ATMEL CORPORATION
A
Document Number: CHW5454 Sheet 6\ of 8
Rev: 4
Date: Wednesday, June 27, 2001
5
4
3
2
1
2309B-FPSLI-01/02
D VCC C13 0.33 uF C B VCC 1 GND A 1
RS232 Circuits
5
4
3
2
1
D VCC VCC R1 2K7 C14 0.68 uF D1 1N6050 1 2 3 4 5 6 7 8 9 10 11 12 U8 LN GND LP V+ VCC R1IN SD R2IN EN R3IN R1OUT R4IN R2OUT R5IN R3OUT T1OUT R4OUT T2OUT R5OUT T3OUT T1IN VT2IN T3IN MAX212CWG 24 23 22 21 20 19 18 17 16 15 14 13 R2 2K7 P1 5 9 4 8 3 7 2 6 1
UART0
CONNECTOR DB9 C
L9 15 uH RX0_140 RX1_149 D2 1N6050 TX0_141 TX1_150
P2 5 9 4 8 3 7 2 6 1
C15 0.33 uF
UART1
CONNECTOR DB9 B
TP5 VCC TEST POINT 1
TP6 VCC TEST POINT 1
TP7 VCC TEST POINT 1
TP8
TEST POINT
TP1 GND TEST POINT 1
TP2 GND TEST POINT 1
TP3 GND TEST POINT 1
TP4
TEST POINT Title: RS232 Circuits Size: A
ATMEL CORPORATION
A
ATSTK94
Document Number: CHW5454 Sheet 7 of 8 1
Rev: 4
5
4
3
Date: Wednesday, June 27, 2001 2
15
Switch Circuits
R8 R7
R6
R5 R4 R3 R2 R1 COM
Switches similar to FPGA Starter Kit SW1 JP9
1
2
9 8 7 6 5 4 3 2 1
SW2
2
C6 10 nF
3
R13 1k INTP1_145 JP11 SW3_192
SW3 C7 10 nF
3
R14 1k INTP2_146 JP12 SW4_188
C
1
1
SW4
2
1
C8 10nF
3
SW5
1
2
C9 10 nF
3
B
2
SW6
1
C10 10 nF
3
SW7 C11 10 nF R18 1k
3 1
2
SW8
3
1
ATSTK94
4 3 2 1
C5 10 nF
3
16
U7 330R VCC Jumpers similar to FPGA Starter Kit Clock Jumpers SW1_202 R12 1k INTP0_135 JP10 SW2_198
D
2
5
8 RESNET
D
C
R15 1k INTP3_152 JP13 SW5_180 LED0
For Silk screen do not label too many jumpers for LED and Switches. Indicate function of jumper by connecting line as shown.
swjmp0 ledjmp0 cap
sw0
R16 1k
PE0_109 JP14 SW6_176
B
R17 1k
PE1_110 JP15 SW7_172
PE2_113 JP16
2
SW8_168
A
C12 10 nF
R19 1k
ATMEL CORPORATION PE3_122 Tit le: Switch Circuits
A
Siz e: A
Document Number: CHW5454 Date: Wednesday, June 27, 2001 Sheet 8 of 8
3 2 1
Rev: 4
5
4
2309B-FPSLI-01/02
ATSTK94
Device Pinout and Board Connection Summary
Table 8 shows the pin number for the FPSLIC device, the corresponding function of the FPSLIC pin and then the function as it is laid out on the Starter Kit. Any pin that does not have a board Function assigned may be used as a wire wrap or probe connection into the FPSLIC device. All probe pins on the board are connected to the corresponding IO of the chip. Pins that connect to the Switches or LEDs may also be used as user-specific inputs or outputs simply by leaving the corresponding Jumper disconnected. Table 8. Pinout and Board Connection
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 FPSLIC IO Type No Connect GND No Connect GCK1(IO) IO IO IO IO IO IO IO IO IO GND FCK1(IO) IO IO IO IO IO IO IO IO IO GND VCC IO IO IO GND VCC GND GND Board Function Hardware
17
2309B-FPSLI-01/02
Table 8. Pinout and Board Connection
Pin 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 FPSLIC IO Type IO IO IO IO IO IO FCK2(IO) GND IO IO IO IO IO IO IO IO OTS(IO) GCK2(IO) AVRRESET GND M0 No Connect No Connect No Connect No Connect VCC M2 GCK3(IO) HDC(IO) IO IO IO LDC(IO) IO IO ALPHANUMERIC 1 P ALPHANUMERIC 1 Cathode 1 LED1 P LED1 Cathode 1 ALPHANUMERIC 1 E ALPHANUMERIC 1 F ALPHANUMERIC 1 M LED1 E LED1 F LED1 M GND AVR RESET GND GND JP19, SW12 GND Board Function Hardware
18
ATSTK94
2309B-FPSLI-01/02
ATSTK94
Table 8. Pinout and Board Connection
Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 FPSLIC IO Type IO IO GND IO IO IO IO IO IO IO IO IO INIT(IO) VCC GND IO IO IO IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO IO Board Function ALPHANUMERIC 1 L ALPHANUMERIC 1 G GND ALPHANUMERIC 1 K ALPHANUMERIC 1 H ALPHANUMERIC 1 J ALPHANUMERIC 1 N ALPHANUMERIC 1 D ALPHANUMERIC 1 A ALPHANUMERIC 1 DP ALPHANUMERIC 1 Cathode 2 ALPHANUMERIC 1 C INIT VCC GND ALPHANUMERIC 1 B ALPHANUMERIC 0 E ALPHANUMERIC 0 F ALPHANUMERIC 0 M ALPHANUMERIC 0 P ALPHANUMERIC 0 Cathode 1 ALPHANUMERIC 0 L ALPHANUMERIC 0 G ALPHANUMERIC 0 K ALPHANUMERIC 0 H GND ALPHANUMERIC 0 J ALPHANUMERIC 0 N ALPHANUMERIC 0 D ALPHANUMERIC 0 A ALPHANUMERIC 0 DP ALPHANUMERIC 0 Cathode 2 ALPHANUMERIC 0 C ALPHANUMERIC 0 B LED0 J LED0 N LED0 D LED0 A LED0 DP LED0 Cathode 2 LED0 C LED0 B LED1 B LED0 E LED0 F LED0 M LED0 P LED0 Cathode 1 LED0 L LED0 G LED0 K LED0 H LED1 K LED1 H LED1 J LED1 N LED1 D LED1 A LED1 DP LED1 Cathode 2 LED1 C AT17 RESET/OE Hardware LED1 L LED1 G
19
2309B-FPSLI-01/02
Table 8. Pinout and Board Connection
Pin 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 FPSLIC IO Type IO GCK4 (IO) GND No Connect CON No Connect No Connect VCC No Connect RESET PE0 PE1 PD0 PD1 PE2 PD2 No Connect No Connect No Connect No Connect No Connect PD3 PD4 PE3 CS0 SDA SCL PD5 PD6 PE4 PE5 VCC GND PE6 PE7 PD7 2 Wire Serial Data 2 Wire Serial Clock PortD 5 PortD 6 PortE 4 PortE 5 VCC GND PortE 6 PortE 7 PortD 7 JP8 A AT17 Data AT17 Clock JP6 A JP7 A PortD 3 PortD 4 PortE 3 JP4 A JP5 A JP16 A FPSLIC Device RESET PortE 0 PortE 1 PortD 0 PortD 1 PortE 2 PortD 2 JP19, SW12 JP13 A JP14 A JP1 A JP2 A JP15 A JP3 A VCC Configuration Control AT17 /CE GCK4 - 4 MHz Clock GND 4 MHz Oscillator Board Function Hardware
20
ATSTK94
2309B-FPSLI-01/02
ATSTK94
Table 8. Pinout and Board Connection
Pin 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 FPSLIC IO Type INTP0 No Connect No Connect XTAL1 XTAL2 RX0 TX0 GND No Connect No Connect INTP1 INTP2 TOSC1 TOSC2 RX1 TX1 D0 INTP3 CCLK VCC No Connect No Connect No Connect No Connect IO GND IO0 GCK7(IO) IO IO IO IO IO IO IO Switch 8 JP16 F LED 8 JP8 F GCK7 Manual Clock MAN CLK (SW) External Interrupt 1 External Interrupt 2 Oscillator Input Oscillator Pair UART 1 Receive UART 1 Transmit Configuration Data Input External Interrupt 3 Configuration Clock JP10 A JP11 A Y2 Y2 UART 1 pin 2 UART 1 pin 3 AT17 Data JP12 A AT17 Clock AVR System Clock Input AVR System Clock Pair UART 0 Receive UART 0 Transmit GND JP17, Y1 JP18, Y1 UART 0 pin3 UART 0 pin 2 Board Function External Interrupt 0 Hardware JP9 A
21
2309B-FPSLI-01/02
Table 8. Pinout and Board Connection
Pin 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 FPSLIC IO Type IO GND IO IO IO IO IO IO IO IO IO IO GND VCC IO IO IO IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO IO IO GCK8(IO) VCC Switch 1 JP9 F LED 1 JP1 F Switch 2 JP10 F LED 2 JP2 F Switch 3 JP11 F LED 3 JP3 F Switch 4 JP12 F LED 4 JP4 F Switch 5 JP13 F LED 5 JP5 F Switch 6 JP14 F LED 6 JP6 F Switch 7 JP15 F Board Function LED 7 Hardware JP7 F
22
ATSTK94
2309B-FPSLI-01/02
ATSTK94
Table 8. Pinout and Board Connection
Pin 206 207 208 FPSLIC IO Type No Connect No Connect No Connect Board Function Hardware
23
2309B-FPSLI-01/02
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel(R), AVR (R) and AVR Studio (R) are the registered trademarks of Atmel; FPSLIC TM and System DesignerTM are the trademarks of Atmel. Windows (R) and WindowsNT (R) are the registered trademarks of Microsoft Corporation; ModelSim (R) is the registered trademark of Mentor Graphics Corporation; LeonardoSpectrum TM and Model TechnologyTM are the trademarks of Mentor Graphics Corporation; Synplify(R) is the registered trademark of Synplicity; FPGA ExpressTM is the trademark of Synopsys. Other terms and product names may be the trademarks of others. Printed on recycled paper.
2309B-FPSLI-01/02 xM

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