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June 2005 rev 0.3 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
Output frequency range: 8.33MHz to 200MHz Input frequency range: 6.25MHz to 125MHz 2.5V or 3.3V operation Split 2.5V / 3.3V outputs 2%( max ) Output duty cycle variation 12 Clock outputs: drive up to 24 clock lines One feedback output Three reference clock inputs: LVPECL or LVCMOS 300pS ( max ) output-output skew Phase-locked loop (PLL) bypass mode `SpreadTrak' Output enable/disable Pin-compatible with CY29773, MPC9773 and MPC973 Industrial temperature range: -40C to +85C 52pin 1.0mm TQFP package RoHS Compliance
ASM5I9773A
The ASM5I9773A features one LVPECL and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides the VCO output per SEL(A:C) settings (see Table 2. Function Table (Configuration Controls)). These dividers allow output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each LVCMOS-compatible output can drive 50 series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces, giving the device an effective fanout of 1:24. The PLL is ensured stable, given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies, from 8 MHz to 200 MHz. For normal operation, the external feedback input FB_IN is connected to the feedback output FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider (see Table 1. Frequency Table). When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.
Functional Description
The ASM5I9773A is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high speed clock distribution applications.
Alliance Semiconductor 2575, Augustine Drive * Santa Clara, CA * Tel: 408.855.4900 * Fax: 408.855.4999 * www.alsc.com
Notice: The information in this document is subject to change without notice.
June 2005 rev 0. 3
Block Diagram
PECL_CLK PECL_CLK# VCO_SEL PLL_EN REF_SEL 0 TCLK0 TCLK1 TCLK_SEL FB_IN 0 1 LPF D Q Sync Frz Phase Detector VCO 1 D Q Sync Frz
ASM5I9773A
QA0 QA1 QA2 QA3
FB_SEL2
QB0 QB1 QB2 QB3
MR#/OE Power-On Reset /4,/6,/8,/12 /4,/6,/8,/10 SELA(0,1) SELB(0,1) SELC(0,1) 2 2 2 /2,/4,/6,/8 0 /4,/6,/8,/10 /2 Sync Pulse FB_SEL(0,1) SCLK SDATA Output Disable Circuitry 2 Data Generator D 12 Q Sync Frz SYNC 1 D Q D Q Sync Frz QC2 QC3 FB_OUT D Q Sync Frz QC0 QC1
Sync Frz
INV_CLK
VCO_SEL
Pin Configuration
VDDQA
VDDQA
SELA0
SELA1
QA0
VSS
VSS
QA1
AVSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 PECL_CLK PECL_CLK# AVDD
1 2 3 4 5 6 7 8 9 10 11 12 13
52 51 50 49 48 47 46 45 44 43 42 41 40
QA2
QA3
SELB0
SELB1 39 38 37 36 35 34 33 32 31 30 29 28 27
VSS QB0 VDDQB QB1 VSS QB2 VDDQB QB3 FB_IN VSS FB_OUT VDD FB_SEL0
ASM5I9773A
14 15 16 17 18 19 20 21 22 23 24 25 26
VDDQC
SYNC
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
INV_CLK
FB_SEL1
VDDQC
SELC1
QC2
SELC0
QC1
QC3
QC0
VSS
VSS
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Pin Configuration1 Pin
11 12 9 10 44,46,48,50 32,34,36,38 16,18,21,23 29 31 25 6 2 8 7 52 14 5,26,27 42,43 40,41 19,20 3 4 45,49 33,37 22,17 13 28 1 15,24,30,35, 39,47,51
ASM5I9773A
Name
PECL_CLK PECL_CLK# TCLK0 TCLK1 QA(3:0) QB(3:0) QC(3:0) FB_OUT FB_IN SYNC PLL_EN MR#/OE TCLK_SEL REF_SEL VCO_SEL INV_CLK FB_SEL(2:0) SELA(1,0) SELB(1,0) SELC(1,0) SCLK SDATA VDDQA VDDQB VDDQC AVDD VDD AVSS VSS
I/O
I, PU I I, PU I, PU O O O O I, PU O I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU I, PU Supply Supply Supply Supply Supply Supply Supply
Type
LVPECL LVPECL LVCMOS
Description
LVPECL reference clock input. LVPECL reference clock input. LVCMOS/LVTTL reference clock input.
LVCMOS LVCMOS/LVTTL reference clock input. LVCMOS Clock output bank A. LVCMOS Clock output bank B. LVCMOS Clock output bank C. LVCMOS Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This LVCMOS input should be at the same voltage rail as input reference clock. See Table 1. Frequency Table. Synchronous pulse output. This output is used for system LVCMOS synchronization. PLL enable/bypass input. When Low, PLL is disabled/bypassed and LVCMOS the input clock connects to the output dividers. Master reset and Output enable/disable input. LVCMOS See Table 2. Function Table (Configuration Controls). LVCMOS Clock reference select input. LVCMOS See Table 2. Function Table (Configuration Controls). LVCMOS/LVPECL Reference select input. LVCMOS See Table 2. Function Table (Configuration Controls). VCO Operating frequency select input. LVCMOS See Table 2. Function Table (Configuration Controls). QC(2,3) Phase selection input. LVCMOS See Table 2. Function Table (Configuration Controls). LVCMOS Feedback divider select input. See Table 6. Frequency select input, Bank A. LVCMOS See Table 3. Function Table (Bank A). Frequency select input, Bank B. LVCMOS See Table 4. Function Table (Bank B). Frequency select input, Bank C. LVCMOS See Table 5. Function Table (Bank C). LVCMOS Serial clock input. LVCMOS Serial data input. VDD VDD VDD VDD VDD Ground Ground 2.5V or 3.3V Power supply for bank A output clocks2,3. 2.5V or 3.3V Power supply for bank B output clocks2,3. 2.5V or 3.3V Power supply for bank C output clocks2,3. 2.5V or 3.3V Power supply for PLL2,3. 2.5V or 3.3V Power supply for core and inputs2,3. Analog Ground. Common Ground.
Notes: 1. PU = Internal pull up, PD = Internal pull down. 2. A 0.1F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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June 2005 rev 0. 3
`SpreadTrak'
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. ASM5I9773A is designed so as not to filter off the Spread Spectrum feature of the Reference Input, assuming it exists.
ASM5I9773A
When a zero delay buffer is not designed to pass the Spread Spectrum feature through, the result is a significant amount of tracking skew which may cause problems in the systems requiring synchronization.
Table 1: Frequency Table Feedback Output Divider
/4 /6 /8. /10 /12 /16 /20 /24 /32 /40
VCO
Input Clock * 4 Input Clock * 6 Input Clock * 8 Input Clock * 10 Input Clock * 12 Input Clock * 16 Input Clock * 20 Input Clock * 24 Input Clock * 32 Input Clock * 40
Input Frequency Range (AVDD = 3.3V)
50 MHz to 125 MHz 33.3 MHz to 83.3 MHz 25 MHz to 62.5 MHz 20 MHz to 50 MHz 16.6 MHz to 41.6 MHz 12.5 MHz to 31.25 MHz 10 MHz to 25 MHz 8.3 MHz to 20.8 MHz 6.25 MHz to 15.625 MHz 5 MHz to 12.5 MHz
Input Frequency Range (AVDD = 2.5V)
50 MHz to 95 MHz 33.3 MHz to 63.3 MHz 25 MHz to 47.5 MHz 20 MHz to 38 MHz 16.6 MHz to 31.6 MHz 12.5 MHz to 23.75 MHz 10 MHz to19 MHz 8.3 MHz to 15.8 MHz 6.25 MHz to 11.8 MHz 5 MHz to 9.5 MHz
Table 2. Function Table (Configuration Controls) Control
REF_SEL TCLK_SEL VCO_SEL PLL_EN INV_CLK
Default
1 1 1 1 1 TCLK0, TCLK1 TCLK0
0
PECL_CLK
1
TCLK1 VCO/1 (high input frequency range) PLL enabled. The VCO output connects to the output dividers QC2 and QC3 are inverted (180 phase shift) with respect to QC0 and QC1 Outputs enabled
VCO/2 (low input frequency range) Bypass mode, PLL disabled. The input clock connects to the output dividers QC2 and QC3 are in phase with QC0 and QC1 Outputs disabled (three-state) and reset of the device. During reset/output disable the PLL feedback loop is open and the VCO running at its minimum frequency. The device is reset by the internal power-on reset (POR) circuitry during power-up.
MR#/OE
1
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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June 2005 rev 0. 3
Table 3. Function Table (Bank A) VCO_SEL
0 0 0 0 1 1 1 1
ASM5I9773A
Table 5. Function Table (Bank C) QA(0:3)
/8 /12 /16 /24 /4 /6 /8 /12
SELA1
0 0 1 1 0 0 1 1
SELA0
0 1 0 1 0 1 0 1
VCO_SEL
0 0 0 0 1 1 1 1
SELC1
0 0 1 1 0 0 1 1
SELC0
0 1 0 1 0 1 0 1
QC(0:3)
/4 /8 /12 /16 /2 /4 /6 /8
Table 4. Function Table (Bank B) VCO_SEL
0 0 0 0 1 1 1 1
Table 6. Function Table (FB_OUT) QB(0:3)
/8 /12 /16 /20 /4 /6 /8 /10
SELB1
0 0 1 1 0 0 1 1
SELB0
0 1 0 1 0 1 0 1
VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0 FB_OUT
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 /8 /12 /16 /20 /16 /24 /32 /40 /4 /6 /8 /10 /8 /12 /16 /20
Absolute Maximum Conditions Parameter
VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT
Description
DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch-up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time
Condition
Functional Relative to VSS Relative to VSS Functional Ripple Frequency < 100 kHz Non-functional Functional Functional Functional Functional Manufacturing test
Min
-0.3 2.375 -0.3 -0.3 200 -65 -40
Max
5.5 3.465 VDD+ 0.3 VDD+ 0.3 VDD /2 150 +150 +85 +150 23 55 10
Unit
V V V V V mA mVp-p C C C C/W C/W V ppm
2000
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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June 2005 rev 0. 3
DC Electrical Specifications (VDD = 2.5V 5%, TA = - 40C to + 85C) Parameter
VIL VIH VPP VCMR VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT
ASM5I9773A
Description
Input Voltage, Low Input Voltage, High Peak-Peak Input Voltage 4 Common Mode Range 5 Output Voltage, Low Output Voltage, High 5 Input Current, Low 5 Input Current, High6 PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance
Condition
LVCMOS LVCMOS LVPECL LVPECL IOL= 15 mA IOH= -15 mA VIL= VSS VIL= VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz
Min
1.7 250 1.0 1.8 14
Typ
5 135 4 18
Max
0.7 VDD+0.3 1000 VDD - 0.6 0.6 -100 100 10 8 22
Unit
V V mV V V V A A mA mA mA pF
DC Electrical Specifications (VDD = 3.3V 5%, TA = - 40C to + 85C) Parameter
VIL VIH VPP VCMR VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT
Description
Input Voltage, Low Input Voltage, High Peak-Peak Input Voltage Common Mode Range4 Output Voltage, Low5 Output Voltage, High5 Input Current, Low
6
Condition
LVCMOS LVCMOS LVPECL LVPECL IOL= 24 mA IOL= 12 mA IOH= -24 mA VIL= VSS VIL= VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz
Min
2.0 250 1.0 2.4 12
Typ
5 225 4 15
Max
0.8 VDD+0.3 1000 VDD- 0.6 0.55 0.30 -100 100 10 8 18
Unit
V V mV V V V A A mA mA mA pF
Input Current, High6 PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance
Notes: 4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 5. Driving one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 series terminated transmission lines. 6. Inputs have pull-up or pull-down resistors that affect the input current.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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June 2005 rev 0. 3
AC Electrical Specifications (VDD = 2.5V 5%, TA = -40C to +85C)7 Parameter
fVCO
ASM5I9773A
Description
VCO Frequency
Condition
/4 Feedback /6 Feedback /8 Feedback /10 Feedback /12 Feedback
Min
200 50 33.3 25 20 16.6 12.5 10 8.3 6.25 5 0 25 500 1.2 100 50 33.3 25 20 16.6 12.5 10 8.3 47.5 45 0.1 -125 -125
Typ
-
Max
380 95 63.3 47.5 38 31.6 23.75 19 15.8 11.8 9.5 200 75 1000 VDD- 0.6 1.0 190 95 63.3 47.5 38 31.6 23.75 19 15.8 20 52.5 55 1.0 125 125
Unit
MHz
fin
Input Frequency
/16 Feedback /20 Feedback /24 Feedback /32 Feedback /40 Feedback Bypass mode (PLL_EN = 0)
MHz
frefDC VPP VCMR tr, tf
Input Duty Cycle Peak-Peak Input Voltage Common Mode Range8 TCLK Input Rise/FallTime LVPECL LVPECL 0.7V to 1.7V /2 Output /4 Output /6 Output /8 Output
% mV V nS
fMAX
Maximum Output Frequency
/10 Output /12 Output /16 Output /20 Output /24 Output
MHz
fSCLK DC tr, tf t()
Serial Clock Frequency Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) fMAX < 100 MHz fMAX > 100 MHz 0.6V to 1.8V TCLK to FB_IN PCLK to FB_IN
MHz % nS pS
Notes: 7. AC characteristics apply for parallel output termination of 50 to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. 8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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AC Electrical Specifications (VDD = 2.5V 5%, TA = - 40C to + 85C)9 Parameter
tsk(O) tsk(B) tPLZ, HZ tPZL, ZH
ASM5I9773A
Description
Output-to-Output Skew Bank-to-Bank Skew Output Disable Time Output Enable Time
Condition
Skew within Bank A Skew within Bank B Skew within Bank C
Min
-
Typ
1.3 - 2.0 0.7 - 1.3 0.9 - 1.3 0.6 - 1.1 0.6 - 0.9 0.4 - 0.6 0.6 - 0.9 7 6 45 -
Max
75 100 150 400 10 10 30 150 435 30 75 235 150 1
Unit
pS pS nS nS
/4 Feedback /6 Feedback /8 Feedback BW PLL Closed Loop Bandwidth (-3dB) /10 Feedback /12 Feedback /16 Feedback /20 Feedback Same frequency (125 MHz) RMS (1) Same frequency Multiple frequencies Same frequency (125 MHz) RMS (1) Same frequency Multiple frequencies tJIT() tLOCK I/O Phase Jitter Maximum PLL Lock Time
-
MHz
tJIT(CC)
Cycle-to-Cycle Jitter
pS
tJIT(PER)
Period Jitter
pS
pS mS
Notes: 9. AC characteristics apply for parallel output termination of 50 to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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June 2005 rev 0. 3
AC Electrical Specifications (VDD = 3.3V 5%, TA = - 40C to + 85C)10 Parameter
fVCO
ASM5I9773A
Description
VCO Frequency
Condition
/4 Feedback /6 Feedback /8 Feedback /10 Feedback /12 Feedback
Min
200 50 33.3 25 20 16.6 12.5 10 8.3 6.25 5 0 25 500 1.2 -
Typ
-
Max
500 125 83.3 62.5 50 41.6 31.25 25 20.8 15.625 12.5 200 75 1000 VDD-0.9 1.0
Unit
MHz
fin
Input Frequency
/16 Feedback /20 Feedback /24 Feedback /32 Feedback /40 Feedback Bypass mode (PLL_EN = 0)
MHz
frefDC VPP VCMR tr, tf
Input Duty Cycle Peak-Peak Input Voltage Common Mode Range8 TCLK Input Rise/FallTime LVPECL LVPECL 0.8V to 2.0V
% mV V nS
Notes: 10. AC characteristics apply for parallel output termination of 50 to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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June 2005 rev 0. 3
AC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C)11 Parameter Description Condition
/2 Output /4 Output /6 Output /8 Output fMAX Maximum Output Frequency /10 Output /12 Output /16 Output /20 Output /24 Output fSCLK DC tr, tf t() Serial Clock Frequency Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) fMAX < 100 MHz fMAX > 100 MHz 0.55V to 2.4V TCLK to FB_IN, same VDD PCLK to FB_IN, same VDD Skew within Bank A Skew within Bank B Skew within Bank C tsk(B) tPLZ, HZ tPZL, ZH Bank-to-Bank Skew Output Disable Time Output Enable Time /4 Feedback /6 Feedback /8 Feedback BW PLL Closed Loop Bandwidth (-3 dB) /10 Feedback /12 Feedback /16 Feedback /20 Feedback Same frequency (125 MHz) RMS (1) Same frequency Multiple frequencies Same frequency (125 MHz) RMS (1) Same frequency Multiple frequencies tJIT() tLOCK I/O Phase Jitter Maximum PLL Lock Time I/O same VDD
ASM5I9773A
Min
100 50 33.3 25 20 16.6 12.5 10 8.3 48 45 0.1 -125 -125 -
Typ
1.3-2.0 0.7-1.3 0.9-1.3 0.6-1.1 0.6-0.9 0.4-0.6 0.6-0.9 7 6 45 -
Max
200 125 83.3 62.5 50 41.6 31.25 25 20.8 20 52 55 1.0 125
Unit
MHz
MHz
MHz % nS pS
125 75 100 150 325 8 8 30 100 375 30 75 225 150 1 pS mS pS pS MHz pS nS nS pS
tsk(O)
Output-to-Output Skew
tJIT(CC)
Cycle-to-Cycle Jitter
tJIT(PER)
Period Jitter
Notes: 11. AC characteristics apply for parallel output termination of 50 to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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June 2005 rev 0. 3
SYNC Output
In situations where output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system synchronization. The ASM5I9773A monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement
ASM5I9773A
of the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for the SYNC output. Note that the SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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Power Management
ASM5I9773A
data. An output is frozen when a logic `0' is programmed The individual output enable/freeze control of the ASM5I9773A allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic `0' state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs can not be frozen with the serial port, this avoids any potential lock up situation, should an error occur in the loading of the serial and enabled when a logic `1' is written. The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial "runt" clocks. The serial input register is programmed through the SDATA input by writing a logic `0' start bit followed by 12 NRZ freeze enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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June 2005 rev 0. 3
ASM5I9773A
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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June 2005 rev 0. 3
Package Information 52-lead TQFP Package
ASM5I9773A
SECTION A-A
Dimensions Symbol
A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e
Inches Min Max
.... 0.0020 0.0374 0.4646 0.3898 0.4646 0.3898 0.0177 0.0035 0.0038 0.0102 0.0106 0.0031 0 0.0472 0.0059 0.0413 0.4803 0.3976 0.4803 0.3976 0.0295 0.0079 0.0062 0.0150 0.0130 0.0079 7
Millimeters Min Max
... 0.05 0.95 11.8 9.9 11.8 9.9 0.45 0.09 0.097 0.26 0.27 0.08 0 1.2 0.15 1.05 12.2 10.1 12.2 10.1 0.75 0.2 0.157 0.38 0.33 0.2 7
0.03937 REF
1.00 REF
0.0256 BASE
0.65 BASE
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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June 2005 rev 0. 3
Ordering Information Part Number
ASM5I9773A-52-ET ASM5I9773A-52-ER ASM5I9773AG-52-ET ASM5I9773AG-52-ER
ASM5I9773A
Marking
ASM5I9773A ASM5I9773A ASM5I9773AG ASM5I9773AG
Package Type
52-pin TQFP, Tray 52-pin TQFP - Tape and Reel 52-pin TQFP, Tray, Green 52-pin TQFP - Tape and Reel, Green
Operating Range
Industrial Industrial Industrial Industrial
Device Ordering Information
ASM5I9773AG-52-ET
R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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June 2005 rev 0. 3
ASM5I9773A
Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: ASM5I9773A Document Version: 0.3
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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