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ASAHI KASEI
[AK4368]
AK4368
PLL & HP-AMP DAC
AK4368 PLL & I/F 16
24bit D/A AK4368 3D Stereo Enhancement ON/OFF 41pin BGA
PLL
50mW
DAC
- 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz FIR : 20kHz : 0.02dB : 54dB : 32kHz, 44.1kHz, 48kHz PLL: : 27MHz, 26MHz, 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz, 14.4MHz, 13MHz, 12MHz, 11.2896MHz AC I/F : MSB First, 2's Compliment 2 - I S, 24bit , 24bit/20bit/16bit : LR, LL, RR, (L+R)/2 ALC 8
3D Stereo Enhancement :3 /I2C
: 50mW x 2ch @16, 3.3V - S/N: 92dB@3.3V ON/OFF : 1.6V 3.6V : 4.0mA @2.4V (HP-AMP ) Ta: -30 85C : 41pin BGA (4mm x 4mm, 0.5mm pitch)
MS0409-J-01 -1-
2005/08
ASAHI KASEI
[AK4368]
PVDD
PVSS
MCKO
MCLK
VCOC
LIN
MIN
BICK LRCK SDATA DVDD DVSS
AVDD Audio Interface PLL VCOM AVSS VCOM
DAC
(Lch)
HDP Amp
MUTE
HPL
ALC DEM ATT Bass Boost Digital Filter 3D Stereo Enhancement LOUT 3DCAP1 3DCAP2 3DCAP3 ROUT HDP Amp
PDN I2C CAD0/CSN SCL/CCLK SDA/CDTI Serial I/F
DAC
(Rch)
MUTE
HPR
HVDD HVSS MUTET RIN
Figure 1.
MS0409-J-01 -2-
2005/08
ASAHI KASEI
[AK4368]
AK4368VG AKD4368
-30 +85C AK4368
41pin BGA (0.5mm pitch)
7 6 5
AK4368VG
4 3 2 1 Top View
A
B
C
D
E
F
G
7 6 5 4 3 2 1
NC HPL MIN RIN VCOC PVDD NC A
HPR HVSS NC NC LIN PVSS MCKO B
HVDD AVSS
AVDD MUTET
VCOM ROUT
LOUT
NC
3DCAP2 3DCAP3 NC 3DCAP1 NC CAD0/ CSN SCL/ CCLK NC G
Top View NC DVSS DVDD C I2C MCKI D LRCK BICK E
PDN NC SDATA SDA/ CDTI F
MS0409-J-01 -3-
2005/08
ASAHI KASEI
[AK4368]
AK4365, AK4367
AK4365 PLL PLL I/F 19.8/19.68/19.2/15.36/ 14.4/13/12/11.2896MHz 8/11.025/16/22.05/24/32/ 44.1/48kHz 20bit 16/20bit I2S Available N/A N/A Mono 3-wire +6dB (L+R)/2 10mW 2.7 3.3V 28QFN(5.2mm x 5.2mm) AK4367 N/A N/A 24bit 16/20/24bit I2S N/A N/A N/A Mono 3-wire/I2C +16dB (L+R)/2 50mW 2.2 3.6V 20QFN(4.2mm x 4.2mm) AK4368 27/26/19.8/19.68/19.2/ 15.36/14.4/13/12/11.2896 MHz 8/11.025/12/16/22.05/24/ 32/44.1/48kHz
ALC 3D Stereo Enhancement
Available Available Available Stereo
LL, RR, (L+R)/2 50mW 1.6 3.6V 41BGA(4mm x 4mm)
MS0409-J-01 -4-
2005/08
ASAHI KASEI
[AK4368]
No. B1 C2 C1 D2 D1 E2 E1 F2 F1 G2 G3 MCKO DVSS DVDD I2C MCKI LRCK BICK SDATA SDA CDTI SCL CCLK CAD0 CSN PDN 3DCAP1 3DCAP2 3DCAP3 LOUT ROUT VCOM AVDD AVSS MUTET HVDD HVSS HPR HPL MIN RIN LIN VCOC PVSS PVDD
I/O O I I I/O I/O I I/O I I I I I I O O O O O O O O O I I I O HVSS pin L/R "H": I2C , "L": 3
0 & "L"
(I2C pin = "H") (I2C pin = "L") (I2C pin = "H") (I2C pin = "L") (I2C pin = "H") (I2C pin = "L")
F4 G5 F6 G6 F7 E6 E7 D7 C6 D6 C7 B6 B7 A6 A5 A4 B3 A3 B2 A2
"L" 3D Stereo Enhancement 3DCAP2 pin 4.7nF 3D Stereo Enhancement 3DCAP1 pin 4.7nF 470nF 3D Stereo Enhancement 3DCAP3 pin 470nF Lch Rch AVSS pin 2.2F
1 2 3DCAP3 pin 3
Rch HP-Amp Lch HP-Amp Rch Lch PLL PVSS PLL PLL
AVSS AVDD
MS0409-J-01 -5-
2005/08
ASAHI KASEI
[AK4368]
No. A1 A7 B4 B5 C3 F3 F5 G1 G4 G7 Note:
NC
I/O -
No Connect Pin No internal bonding. These pins should be connected to ground
(I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) PDN pin = "L"
Note: MCKI pin
Analog Digital
LOUT, ROUT, MUTET, HPR, HPL, MIN, RIN, LIN CAD0 MCKO
DVSS
MS0409-J-01 -6-
2005/08
ASAHI KASEI
[AK4368]
(AVSS, DVSS, HVSS, PVSS=0V; Note 1) Parameter Symbol min max Power Supplies Analog AVDD 4.6 -0.3 Digital DVDD 4.6 -0.3 PLL PVDD 4.6 -0.3 HP-Amp HVDD 4.6 -0.3 |AVSS - DVSS| (Note 2) 0.3 GND1 |AVSS - HVSS| (Note 2) 0.3 GND2 |AVSS - PVSS| (Note 2) 0.3 GND3 Input Current (any pins except for supplies) IIN 10 Analog Input Voltage (Note 3) VINA AVDD+0.3 or 4.6 -0.3 Digital Input Voltage (Note 4) VIND DVDD+0.3 or 4.6 -0.3 Ambient Temperature Ta 85 -30 Storage Temperature Tstg 150 -65 Note 1. Note 2. AVSS, DVSS, HVSS PVSS Note 3. MIN, LIN, RIN pins. Note 4. SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCLK, PDN, I2C pins.
Units V V V V V V V mA V V C C
:
(AVSS, DVSS, HVSS, PVSS=0V; Note 1) Parameter Symbol Power Supplies Analog AVDD Digital DVDD PLL PVDD HP-Amp HVDD Difference1 AVDD-PVDD Difference2 AVDD-HVDD Note 1.
min 1.6 1.6 1.6 1.6 -0.3 -0.3
typ 2.4 2.4 2.4 2.4 0 0
Max 3.6 AVDD 3.6 3.6 +0.3 +0.3
Units V V V V V V
:
MS0409-J-01 -7-
2005/08
ASAHI KASEI
[AK4368]
( Ta=25C; AVDD=PVDD=DVDD=HVDD=2.4V, AVSS=PVSS=DVSS=HVSS=0V; fs=44.1kHz; EXT mode; BOOST OFF; Slave Mode; Signal Frequency =1kHz; Measurement band width=20Hz 20kHz; Headphone-Amp: RL =16, CL=220F (Figure 45 )) Parameter min typ Max Units 24 bit DAC Resolution Headphone-Amp: (HPL/HPR pins) (Note 5) Analog Output Characteristics THD+N dB -3dBFS Output, 2.4V, Po=10mW@16 -50 -40 -4.8dBFS Output, 3.3V, dB -20 Po=50mW@16 HPG bit= "1" 82 90 dB D-Range -60dBFS Output, A-weighted, 2.4V 92 dB -60dBFS Output, A-weighted, 3.3V S/N A-weighted, 2.4V 82 90 dB A-weighted, 3.3V 92 dB Interchannel Isolation 60 80 dB DC Accuracy Interchannel Gain Mismatch Gain Drift Load Resistance (Note 6) Load Capacitance Output Voltage -3dBFS Output (Note 7) -4.8dBFS Output, 3.3V, Po=50mW@16 HPG bit= "1" Stereo Line Output: (LOUT/ROUT pins, RL=10k) (Note 8) Analog Output Characteristics: THD+N 0dBFS Output S/N A-weighted DC Accuracy Gain Drift Load Resistance (Note 6) Load Capacitance Output Voltage 0dBFS Output (Note 9) Output Volume: (LOUT/ROUT pins) Step Size Gain Control Range 16 1.01 0.3 200 1.13 0.89 0.5 300 1.25 dB ppm/C pF Vpp Vrms
80 10 1.32 1 -30
-60 87 200 1.47 2 -
-50 25 1.61 3 0
dB dB ppm/C k pF Vpp dB dB
Note 5. DACHL=DACHR bits = "1", MINHL=MINHR=LINHL=RINHR bits = "0" Note 6. AC Note 7. AVDD Vout = 0.47 x AVDD(typ)@-3dBFS. Note 8. DACL=DACR bits = "1", MINL=MINR=LINL=RINR bits = "0" Note 9. AVDD Vout = 0.61 x AVDD(typ)@0dBFS.
MS0409-J-01 -8-
2005/08
ASAHI KASEI
[AK4368]
Parameter LINEIN: (LIN/RIN/MIN pins) Analog Input Characteristics Input Resistance (Figure 23, Figure 24 ) LIN pin LINHL bit = "1", LINL bit = "1" LINHL bit = "1", LINL bit = "0" LINHL bit = "0", LINL bit = "1" RIN pin RINHR bit = "1", RINR bit = "1" RINHR bit = "1", RINR bit = "0" RINHR bit = "0", RINR bit = "1" MIN pin MINHL=MINHR=MINL=MINR bits = "1" MINHL bit = "1", MINHR=MINL=MINR bits = "0" MINHR bit = "1", MINHL=MINL=MINR bits = "0" MINL bit = "1", MINHL=MINHR=MINR bits = "0" MINR bit = "1", MINHL=MINHR=MINL bits = "0" Gain LIN/MINLOUT, RIN/MIN ROUT LIN/MINHPL, RIN/MIN HPR Power Supplies Power Supply Current Normal Operation (PDN pin = "H") (Note 10) AVDD+PVDD+DVDD HVDD Power-Down Mode (PDN pin = "L") (Note 11)
min
typ
max
Units
35 35 17 -1 -0.24
50 100 100 50 100 100 25 100 100 100 100 0 +0.76
+1 +1.76
k k k k k k k k k k k dB dB
-
3.8 1.2 1
5.5 2.5 100
mA mA A
Note 10. PMDAC=PMHPL=PMHPR=PMLO bits = "1", MUTEN bit = "1", MCKO bit = "0", HP-Amp PMDAC=PMHPL=PMHPR= "1",PMLO bit= "0" , AVDD+PVDD+DVDD+HVDD= 4.0mA. Note 11. (MCKI, BICK, LRCK) DVSS
MS0409-J-01 -9-
2005/08
ASAHI KASEI
[AK4368]
(Ta=25C; AVDD, DVDD, PVDD, HVDD=1.6 3.6V; fs=44.1kHz; De-emphasis = "OFF") Parameter Symbol min typ DAC Digital Filter: (Note 12) Passband (Note 13) PB 0 -0.05dB 22.05 -6.0dB Stopband (Note 13) SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 14) GD 22 Group Delay Distortion 0 GD DAC Digital Filter + Analog Filter: (Note 12) (Note 15) Frequency Response FR 0 20.0kHz 0.5 Analog Filter: (Note 16) Frequency Response FR 0 20.0kHz 1.0 BOOST Filter: (Note 15) (Note 17) Frequency Response 20Hz FR 5.76 MIN 100Hz 2.92 1kHz 0.02 20Hz FR 10.80 MID 100Hz 6.84 1kHz 0.13 20Hz FR 16.06 MAX 100Hz 10.54 1kHz 0.37 Note 12. BOOST OFF (BST1-0 bit = "00") Note 13. fs ( ) PB=0.4535fs(@-0.05dB) SB=0.546fs(@-54dB) Note 14. Note 15. DAC Note 16. MIN Note 17. HPL, HPR, LOUT, ROUT HPL/HPR/LOUT/ROUT, LIN fs
max 20.0 0.02 -
Units kHz kHz kHz dB dB 1/fs s dB dB dB dB dB dB dB dB dB dB dB
HPL/LOUT, RIN
HPR/ROUT
Boost Filter (fs=44.1kHz) 20 15 Level [dB] MID 10 MIN 5 0 -5 10 100 Frequency [Hz] 1000 10000
MAX
Figure 2. Boost Frequency (fs=44.1kHz)
MS0409-J-01 - 10 -
2005/08
ASAHI KASEI
[AK4368]
DC (Ta=25C; AVDD, DVDD, PVDD, HVDD=1.6 3.6V) Parameter Symbol High-Level Input Voltage 2.2VDVDD3.6V VIH 1.6VDVDD<2.2V VIH Low-Level Input Voltage 2.2VDVDD3.6V VIL 1.6VDVDD<2.2V VIL Input Voltage at AC Coupling (Note 18) VAC High-Level Output Voltage VOH (Iout=-200A) Low-Level Output Voltage VOL (Except SDA pin: Iout=200A) (SDA pin: Iout=3mA) VOL Input Leakage Current Iin
Note 18. MCKI pin (Figure 45
min 70%DVDD 80%DVDD 0.4 DVDD-0.2 )
typ -
max 30%DVDD 20%DVDD 0.2 0.4 10
Units V V V V Vpp V V V A
MS0409-J-01 - 11 -
2005/08
ASAHI KASEI
[AK4368]
(Ta=25C; AVDD, DVDD, PVDD, HVDD=1.6 3.6V; CL = 20pF) Parameter Symbol min Master Clock Input Timing Frequency (PLL mode) fCLK 11.2896 (EXT mode) fCLK 2.048 Pulse Width Low (Note 19) tCLKL 0.4/fCLK Pulse Width High (Note 19) tCLKH 0.4/fCLK AC Pulse Width (Note 20) tACW 18.5 LRCK Timing Frequency fs 8 Duty Cycle: Slave Mode Duty 45 Master Mode Duty MCKO Output Timing (PLL mode) Frequency fCLKO 0.256 Duty Cycle (Except fs=32kHz, PS1-0= "00") dMCK 40 (fs=32kHz, PS1-0= "00") dMCK Serial Interface Timing (Note 21) Slave Mode (M/S bit = "0"): BICK Period tBCK 312.5 BICK Pulse Width Low tBCKL 100 Pulse Width High tBCKH 100 tLRB 50 LRCK Edge to BICK "" (Note 22) tBLR 50 BICK "" to LRCK Edge (Note 22) SDATA Hold Time tSDH 50 SDATA Setup Time tSDS 50 Master Mode (M/S bit = "1"): BICK Frequency (BF bit = "1") fBCK (BF bit = "0") fBCK BICK Duty dBCK tMBLR BICK "" to LRCK -50 SDATA Hold Time tSDH 50 SDATA Setup Time tSDS 50 Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN "H" Time tCSW 150 tCSS 50 CSN "" to CCLK "" tCSH 50 CCLK "" to CSN "" Note 19. AC Note 20. MCKI (Figure 3 Note 21. Note 22. LRCK ) BICK ""
typ 44.1 50 33
max 27 12.288 48 55 12.288 60 -
Units MHz MHz ns ns ns kHz % % MHz % %
64fs 32fs 50 -
50 -
ns ns ns ns ns ns ns Hz Hz % ns ns ns ns ns ns ns ns ns ns ns
MS0409-J-01 - 12 -
2005/08
ASAHI KASEI
[AK4368]
Parameter Control Interface Timing (I2C Bus mode): (Note 23) SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 24) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Power-down & Reset Timing PDN Pulse Width (Note 25) Note 23. I2C Philips Semiconductors Note 24. 300ns (SCL Note 25. PDN pin "L"
Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP tPD
min 1.3 0.6 1.3 0.6 0.6 0 0.1 0.6 0 150
typ -
max 400 0.3 0.3 50 -
Units kHz s s s s s s s s s s ns ns
) "H"
MS0409-J-01 - 13 -
2005/08
ASAHI KASEI
[AK4368]
1/fCLK
1000pF MCLK Input 100k DVSS Measurement Point
tACW
tACW
VAC DVSS
Figure 3. MCKI AC Coupling Timing
1/fCLK VIH VIL tCLKH tCLKL
MCKI
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
MCKO tH tL dMCK=tH/(tH+tL) or tL/(tH+tL)
50% DVDD
Figure 4. Clock Timing
MS0409-J-01 - 14 -
2005/08
ASAHI KASEI
[AK4368]
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDATA
VIH VIL
Figure 5. Serial Interface Timing (Slave Mode)
LRCK
50%DVDD
tMBLR
BICK tSDH
50%DVDD
tSDS SDATA
VIH VIL
Figure 6. Serial Interface Timing (Master mode)
MS0409-J-01 - 15 -
2005/08
ASAHI KASEI
[AK4368]
VIH CSN VIL tCSS tCCKL tCCKH VIH VIL tCDS tCDH VIH VIL
CCLK
CDTI
C1
C0
R/W
A4
Figure 7. WRITE Command Input Timing
tCSW VIH CSN VIL tCSH CCLK VIH VIL
CDTI
D3
D2
D1
D0
VIH VIL
Figure 8. WRITE Data Input Timing
VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop
Figure 9. I2C Bus Mode Timing
tPD
PDN
VIL
Figure 10. Power-down & Reset Timing
MS0409-J-01 - 16 -
2005/08
ASAHI KASEI
[AK4368]
1) PLL
(PMPLL bit = "1") PLL PLL3-0 bits, FS3-0 bits (Table 1, Table 2) PS1-0 bits (Table 3) MCKO bit Table 1 (PMDAC bit = "1") 0"
MCKO PLL
ON/OFF
AK4368 M/S bit
M/S bit (PDN pin = "L") "1"
"1"
"0"
26MHz, 27MHz (Figure 11)
11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz, 19.8MHz, PLL MCKO, BICK, LRCK
AK4368
MCKI MCKO BICK LRCK SDATA
27MHz,26MHz,19.8MHz,19.68MHz, 19.2MHz,15.36MHz,14.4MHz,13MHz, 12MHz,11.2896MHz
DSP or P
256fs/128fs/64fs/32fs 32fs, 64fs 1fs
MCLK BCLK LRCK SDTO
Figure 11. PLL Master Mode M/S bit "1" AK4368 LRCK, BICK pin AK4368 100k LRCK, BICK pin
BICK
(M/S bit = "1") PMPLL bit = "0" "1" PMDAC bit = "0" LRCK BICK "L" MCKO bit = "1" MCKO pin MCKO bit = "0" MCKO pin "L" AK4368 (Table 4)
"1" PLL
PLL LRCK
MS0409-J-01 - 17 -
2005/08
ASAHI KASEI
[AK4368]
BICK, LRCK pin MCKO
PLL BICK, LRCK
AK4368
AK4368
MCKI MCKO BICK LRCK SDATA
27MHz,26MHz,19.8MHz,19.68MHz, 19.2MHz,15.36MHz,14.4MHz,13MHz, 12MHz,11.2896MHz
DSP or P
256fs/128fs/64fs/32fs 32fs ~ 64fs 1fs
MCLK BCLK LRCK SDTO
Figure 12. PLL Slave Mode (M/S bit = "0") PMPLL bit = "0" "1" MCKO bit = "1" MCKO pin MCKO pin Table 3 BICK (PMDAC bit = "0") PMDAC bit = "0" "1" PLL (PMDAC bit =
"1")
PLL LRCK
Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14-15
PLL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1
PLL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 Others
PLL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
PLL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MCKI 11.2896MHz 14.4MHz 12MHz 19.2MHz 15.36MHz 13MHz 19.68MHz 19.8MHz 26MHz 27MHz 13MHz 26MHz 19.8MHz 27MHz
fs[kHz]
N/A Table 1. MCKI
44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.0995 10k 48.0007 44.0995 10k 48.0007 44.0995 10k 47.9992 44.0995 10k 47.9997 N/A N/A (PLL mode)
VCOC R,C C[F] R[] 10k 22n 10k 22n 10k 47n 10k 22n 10k 22n 15k 330n 10k 47n 10k 47n 15k 330n 10k 47n 22n 22n 22n 22n N/A
PLL (typ 20ms 20ms 20ms 20ms 20ms 100ms 20ms 20ms 100ms 20ms 20ms 20ms 20ms 20ms Default
MS0409-J-01 - 18 -
2005/08
ASAHI KASEI
[AK4368]
Mode 0 1 2 4 5 6 8 9 10 3, 7, 11-15
FS3 0 0 0 0 0 0 1 1 1
FS2 0 0 0 1 1 1 0 0 0 Others Table 2.
FS1 0 0 1 0 0 1 0 0 1
FS0 0 1 0 0 1 0 0 1 0
fs 48kHz 24kHz 12kHz 32kHz 16kHz 8kHz 44.1kHz 22.05kHz 11.025kHz N/A (PLL mode)
Default
PS1 PS0 MCKO 0 0 256fs Default 0 1 128fs 1 0 64fs 1 1 32fs Table 3. MCKO (PLL mode, MCKO bit = "1")
Master Mode (M/S bit = "1") Power Up Power Down PLL Unlock (PMDAC bit= PMPLL bit= "1") (PMDAC bit= PMPLL bit= "0") MCKI pin Refer to Table 1. Input or Refer to Table 1. fixed to "L" or "H" MCKO pin MCKO bit = "0": "L" "L" MCKO bit = "0": "L" MCKO bit = "1": Output MCKO bit = "1": Unsettling BICK pin BF bit = "1": 64fs output "L" "L" BF bit = "0": 32fs output LRCK pin Output "L" "L" Table 4. Clock Operation in Master mode (PLL mode)
Slave Mode (M/S bit = "0") Power Up Power Down (PMDAC bit= PMPLL bit= "1") (PMDAC bit= PMPLL bit= "0") MCKI pin Refer to Table 1. Input or fixed to "L" or "H" MCKO pin MCKO bit = "0": "L" "L" MCKO bit = "1": Output BICK pin Input Fixed to "L" or "H" externally
PLL Unlock Refer to Table 1.
LRCK pin
Input
MCKO bit = "0": "L" MCKO bit = "1": Unsettling Input or Fixed to "L" or "H" externally Fixed to "L" or "H" externally Input or Fixed to "L" or "H" externally Table 5. Clock Operation in Slave mode (PLL mode)
MS0409-J-01 - 19 -
2005/08
ASAHI KASEI
[AK4368]
2) PMPLL bit "0" DAC PLL3-0 bits bit
(PMPLL bit = "0": Default) (EXT mode) FS3-0 bits MCKO MCKO bit (PMDAC bit = "1") MCKI pin ON/OFF PLL Table 6 PS1-0
DAC "0"
"1")
(M/S bit = "1") MCKI pin DAC
LRCK
BICK
AK4368
(Figure 13)
(PMDAC bit =
(PMDAC bit = "0")
AK4368
MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK SDATA 32fs, 64fs 1fs MCLK BCLK LRCK SDTO
DSP or P
Figure 13. EXT Master Mode (M/S bit = "0") (MCKI, BICK, LRCK) DAC (PMDAC bit = "0") MCKI, BICK, LRCK (Figure 14) MCKI DAC (PMDAC bit = "1") LRCK
AK4368
MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK SDATA 32fs 64fs 1fs MCLK BCLK LRCK SDTO
DSP or P
Figure 14. EXT Slave Mode
MS0409-J-01 - 20 -
2005/08
ASAHI KASEI
[AK4368]
Mode 0 1 2 4 5 6 8 9 10 3, 7, 11-15
FS3 0 0 0 0 0 0 1 1 1
FS2 0 0 0 1 1 1 0 0 0 Others
FS1 0 0 1 0 0 1 0 0 1
FS0 0 1 0 0 1 0 0 1 0
fs 8kHz 48kHz 8kHz 24kHz 8kHz 12kHz 8kHz 48kHz 8kHz 24kHz 8kHz 12kHz 8kHz 48kHz 8kHz 24kHz 8kHz 12kHz N/A
MCKI 256fs 512fs 1024fs 256fs 512fs 1024fs 256fs 512fs 1024fs N/A
Default
Table 6.
MCKI
(EXT mode)
PS1 PS0 MCKO 0 0 256fs Default 0 1 128fs 1 0 64fs 1 1 32fs Table 7. MCKO (EXT mode, MCKO bit = "1") Master Mode (M/S bit = "1") Power Up (PMDAC bit = "1") Power Down (PMDAC bit = "0") MCKI pin Refer to Table 6. Input or fixed to "L" or "H" MCKO pin MCKO bit = "0": "L" "L" MCKO bit = "1": Output BICK pin BF bit = "1": 64fs output "L" BF bit = "0": 32fs output LRCK pin Output "L" Table 8. Clock Operation in Master mode (EXT mode) Slave Mode (M/S bit = "0") Power Up (PMDAC bit = "1") Power Down (PMDAC bit = "0") MCKI pin Refer to Table 6. Input or fixed to "L" or "H" MCKO pin MCKO bit = "0": "L" "L" MCKO bit = "1": Output BICK pin Input Fixed to "L" or "H" externally LRCK pin Input Fixed to "L" or "H" externally Table 9. Clock Operation in Slave mode (EXT mode)
DR, S/N S/N MCKI 256fs 512fs 1024fs Table 10. MCKI
DR, S/N Table 10
MCKI DAC DR,
DR, S/N (BW=20kHz, A-weight) fs=8kHz fs=16kHz 56dB 75dB 75dB 90dB 90dB N/A DR, S/N
(2.4V)
MS0409-J-01 - 21 -
2005/08
ASAHI KASEI
[AK4368]
SDATA, BICK, LRCK 3pin (Table 11) DIF2-0 bits Mode 1 Mode 0 20bit DSP Mode 2 3 16bit LSB 2124bit 4 BICK=32fs(BF bit = "0") Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 0 1 0 1 0
5 Mode 0 16bitDAC Mode 4 Mode 0 24bit Mode 3 I2S LSB 1724bit "0" Mode 2 8 "0" ADC BICK48fs 20bit
Mode 1, 2 BICK
0: 16bit, 1: 20bit, 2: 24bit, 3: I2S 4: 24bit, Table 11.
32fs BICK 64fs 40fs BICK 64fs 48fs BICK 64fs BICK=32fs or 48fs BICK 64fs 48fs BICK 64fs
Figure 15 Figure 16 Figure 17 Figure 18 Figure 16
Default
LRCK BICK (32fs) SDATA Mode 0 BICK SDATA Mode 0
15 14 6 5 4 3 2 1 0 15 14 6 5 4 3 2 1 0 15 14
Don't care 15:MSB, 0:LSB
15
14
0
Don't care
15
14
0
Lch Data
Rch Data
Figure 15. Mode 0
(LRP = BCKP bits = "0")
LRCK BICK SDATA Mode 1 SDATA Mode 4
Don't care 19:MSB, 0:LSB Don't care 23:MSB, 0:LSB 23 22 21 20
19
0
Don't care
19
0
19
0
Don't care
23
22
21
20
19
0
Lch Data
Rch Data
Figure 16. Mode 1, 4
(LRP = BCKP bits = "0")
MS0409-J-01 - 22 -
2005/08
ASAHI KASEI
[AK4368]
LRCK
Lch
Rch
BICK SDATA 16bit SDATA 20bit SDATA 24bit
Figure 17. Mode 2 (LRP = BCKP bits = "0")
23 22 8 3 4 1 0 Don't care 23 22 8 3 4 1 0 Don't care 23 22 19 18 4 1 0 Don't care 19 18 4 1 0 Don't care 19 18 15 14 0 Don't care 15 14 Don't care
0
15
14
LRCK BICK SDATA 16bit SDATA 20bit SDATA 24bit
15 14
Lch
Rch
0
Don't care
15
14
0
Don't care
15
19
18
4
1
0
Don't care
19
18
4
1
0
Don't care
19
23
22
8
3
4
1
0
Don't care
23
22
8
3
4
1
0
Don't care
23
BICK (32fs) SDATA 16bit
0 15 14 6 5 4 3 2 1 0 15 14 6 5 4 3 2 1 0 15
Figure 18. Mode 3
(LRP = BCKP bits = "0")
MS0409-J-01 - 23 -
2005/08
ASAHI KASEI
[AK4368]
ALC
ALC bit = "1" [1] ALC ALC (-6.0dBFS) ALC DAC ALC L/R ATT ALC (LMAT1-0 bits, Table 13) L/R ROTM1-0 bits (Table 12) , fs=24kHz 43ms 85ms 171ms , ALC ALC bit = "0" ALC 0dB
ROTM1 0 0 1 1
ROTM0 0 1 0 1
ALC fs=16kHz fs=22.05kHz 1024/fs 64ms 46ms 2048/fs 128ms 93ms 4096/fs 256ms 186ms Reserved Table 12. ALC
fs=32kHz 32ms 64ms 128ms -
fs=44.1kHz 23ms 46ms 93ms -
fs=48kHz 21ms 43ms 85ms -
Default
LMAT1 0 0 1 1
LMAT0 0 1 0 1
ALC ATT ALC Output ALC Output ALC Output ALC Output 0dBFS +6dBFS +12dBFS -6.0dBFS 1 1 1 1 Default 2 2 2 2 2 2 4 4 2 4 4 8 Table 13. ALC ATT
MS0409-J-01 - 24 -
2005/08
ASAHI KASEI
[AK4368]
[2] ALC ALC DAC ALC ALC (L/R 14) ALC ROTM1-0 bits ROTM1-0 bits ROTM1-0 bits ROTM1-0 bits (-8.5dBFS) ROTM1-0 bits (Table 12) (REF7-0 bits, Table 15)
ALC RATT bit (Table
)
ALC (-6.0dBFS) ALC (ALC (ALC
DAC L/R ALC
ALC
) (DAC ) > (DAC
) < (ALC )
)
ROTM1-0 bits
RATT GAIN STEP 0 1 1 2 Table 14. ALC REF7-0 FFH : C2H C1H C0H BFH : 92H 91H 90H : 73H 72H 71H 70H : 00H Table 15. ALC GAIN(dB) Reserved +18.0 +17.625 +17.25 : +0.375 0 -0.375 : -11.25 -11.625 -12.0 Reserved
Default
Default
MS0409-J-01 - 25 -
2005/08
ASAHI KASEI
[AK4368]
[3] ALC Register Name ROTM1-0 REF7-0 LMAT1-0 RATT ALC Comment fs=16kHz Operation 64ms +18dB 1 step 1 step Enable fs=44.1kHz Operation 46ms +18dB 1 step 1 step Enable
Data Zero crossing timeout period 00 Maximum gain at recovery operation C1H Limiter ATT step 00 Recovery GAIN step 0 ALC enable 1 Table 16. ALC
Data 01 C1H 00 0 1
ALC "0"
ALC PMDAC bit = "0") LMAT1-0, ROTM1-0, RATT, REF7-0
Example:
(ALC bit =
ALC = OFF
Recovery Cycle = 46ms@44.1kHz Limiter and Recovery Step = 1 WR (REF7-0) Maximum Gain = +18dB ALC bit = "1" WR (LMAT1-0, RATT, ROTM1-0; ALC= "1")
ALC Operation Note: WR: Write
(1) Addr=0AH, Data=C1H
(2) Addr=0BH, Data=30H
Figure 19. ALC
MS0409-J-01 - 26 -
2005/08
ASAHI KASEI
[AK4368]
0.5dB DAC (Table 17) DATTC bit "1" DATTC bit "0" Lch, Rch
AK4368
MUTE
256 0dB ATTL7-0 bit Lch, Rch -127dB
(DATT)
ATTL7-0 Attenuation ATTR7-0 FFH 0dB FEH -0.5dB FDH -1.0dB FCH -1.5dB : : : : 02H -126.5dB 01H -127.0dB 00H Default MUTE (-) Table 17. Digital Volume ATT ATT7-0 ATT @fs=44.1kHz) "0" ATS bit 1061/fs 7424/fs 1062 FFH(0dB) PDN pin "L" ATT7-0 00H PMDAC bit "1" (Table 18) ATS bit = "0" 00H(MUTE) 1061/fs (24ms ATT7-0 PMDAC bit
00H
ATS 0 1 Table 18.
ATT speed 0dB to MUTE 1 step 1061/fs 4/fs 7424/fs 29/fs ATT7-0
Default
MS0409-J-01 - 27 -
2005/08
ASAHI KASEI
[AK4368]
xATT - ATT
(Table 18) xATT
SMUTE bit - ("0") ATT
"1"
ATT SMUTE bit - ATT
ATT "0"
SMUTE bit ATS bit ATT Level Attenuation (1) ATS bit (1) (3)
-
GD (2) Analog Output GD
Figure 20. Notes: (1) ATT 3712/fs (2) (3) xATT
(Table 18)
ATS bit = "1" (GD)
ATT
"128"(-63.5dB)
- ATT
MS0409-J-01 - 28 -
2005/08
ASAHI KASEI
[AK4368]
IIR
3 DEM1-0 bit
(32kHz, 44.1kHz, 48kHz)
(50/15s (Table 19) De-emphasis 44.1kHz OFF 48kHz 32kHz
)
DEM1 bit 0 0 1 1 Table 19.
DEM0 bit 0 1 0 1
Default
BST1-0 bit
DAC
(Table 20)
BST1 bit 0 0 1 1
BST0 bit 0 1 0 1 Table 20.
BOOST OFF MIN MID MAX
Default
MONO1-0 bit (Table 21)
DAC
Lch/Rch
MONO1 bit 0 0 1 1
MONO0 bit 0 1 0 1 Table 21.
Lch L L R (L+R)/2
Rch R L R (L+R)/2
Default
PDN pin HPR, LOUT, ROUT
"L" PDN pin
VCOM, DAC, HPL,
DAC MCKI
PMDAC bit
"1"
MCKI
MS0409-J-01 - 29 -
2005/08
ASAHI KASEI
[AK4368]
(HPL, HPR pins)
HVDD PMHPL=PMHPR bits = "1" MUTEN bit "0" tr: tf: (VCOM/2 (VCOM/2 Table 22. C=1F (VCOM/2 (VCOM/2 PMHPL, PMHPR bits "0" HPL, HPR pins HVSS ): tr = 70k x 1 = 70ms(typ) ): tf = 60k x 1 = 60ms(typ) MUTET pin MUTEN bit "1" VCOM(=0.475 x AVDD) HVSS 70k x C (typ) 60k x C (typ)
16
) )
: MUTET pin
PMHPL/R bit
MUTEN bit VCOM VCOM/2 tf (3) (4)
HPL/R pin
tr (1) (2)
Figure 21. (1) (2) (tr) 70k x C(typ) (MUTEN bit = "0") MUTET MUTET pin 60k x C(typ) (PMHPL, PMHPR bits = "1") HVSS "C" (PMHPL, PMHPR bits = "1") HVSS (MUTEN bit = "1") MUTET MUTET pin "C"
VCOM/2
(3)
HVSS VCOM/2 (tf)
(4)
MS0409-J-01 - 30 -
2005/08
ASAHI KASEI
[AK4368]
(fc) (fc) AVDD=2.4, 3.0, 3.3V @-3dBFS
HP-AMP R C
Table 23 RL 16 0.47 x AVDD (Vpp)
Headphone 16
AK4368
Figure 22. Output Power [mW] R [] C [F] 220 100 100 47 100 47 fc [Hz] BOOST=OFF 45 100 70 149 50 106 Table 23. fc [Hz] BOOST=MIN 2.4V 0 6.8 16 17 43 28 78 19 47 , 20 10 5 f HPG=0, 0dB 3.0V 31 15 8 3.3V 38 18 9 HPG=1, 4.8dB 3.3V 50 25 13
ON/OFF "0" (R1=100k)
DACHL, LINHL, MINHL, DACHR, RINHR, MINHR bits +0.76dB(typ) HPG bit = "1" (R1= 50k) +6.76dB(typ)
100k(typ) 100k(typ) 1.09R2
HPG bit = DAC
LIN/RIN pin
LINHL/RINHR bit 100k(typ)
MIN pin
MINHL/MINHR bit R1
-
+
R2
-
+ HP-Amp
HPL/HPR pin
DACL/DACR
DACHL/DACHR bit
Figure 23.
(HPG bit = "0"
)
MS0409-J-01 - 31 -
2005/08
ASAHI KASEI
[AK4368]
(LOUT, ROUT pins)
0.475 x AVDD 10k PMLO bit = "1" ON/OFF DACL, LINL, MINL, DACR, RINR, MINR bits LOG bit = "0"(R1=100k), ATTS3-0 bits = "0FH"(0dB) 0dB(typ) LOG bit = "1" (R1= 50k) DAC +6dB
100k(typ) 100k(typ) R2
LIN/RIN pin
LINL/RINR bit 100k(typ)
MIN pin
MINL/MINR bit R1
-
+
R2
-
+
LOUT/ROUT pin
DACL/DACR
DACL/DACR bit
Figure 24. LOUT/ROUT
(LOG bit = "0"
)
LOUT/ROUT step, Table 24)
LMUTE bit = "0" LOUT/ROUT LMUTE
ATTS3-0 bit
(0dB -30dB, 2dB
ATTS3-0 Attenuation 0FH 0dB 0EH -2dB 0DH -4dB 0CH -6dB 0 : : : : 01H -28dB 00H -30dB 1 x MUTE Default Table 24. LOUT/ROUT Volume ATT (x: Don't care)
MS0409-J-01 - 32 -
2005/08
ASAHI KASEI
[AK4368]
3D Stereo Enhancement
AK4368 3D bits 3D (Table 25) 3D 50ms Figure 25 (3D Stereo Enhancement) DP1-0 bits 3D1-0 bits MUTEN bit 4.7nF 3D1-0 bits (Table 26) 3D1-0
3DCAP1, 3DCAP2, 3DCAP3 pins 20% 20pF 3D1 bit 0 0 1 1 3D0 bit 0 1 0 1 3D OFF ON ON ON Table 25. 3D DP1 bit 0 0 1 1
470nF 3DCAP1, 3DCAP2, 3DCAP3 pins
3D Default LOUT, ROUT HPL, HPR LOUT, ROUT, HPL, HPR
DP0 bit 0 1 0 1 Table 26. 3D
3D Depth 0% 50% 70% 100%
Default
3DCAP1 pin 4.7nF 3DCAP2 pin 470nF 3DCAP3 pin
Figure 25. 3D
MS0409-J-01 - 33 -
2005/08
ASAHI KASEI
[AK4368]
(EXT mode)
1) DAC HP-Amp
Power Supply PDN pin (2) >0 PMVCM bit Don't care Clock Input (3) Don't care Don't care Don't care (1) >150ns (11)
PMDAC bit DAC Internal State SDTI pin DACHL, DACHR bits 3D1-0 bits (when 3D is used) PMHPL, PMHPR bits MUTEN bit "00"(3D OFF) (4) >0 (5) >0 (4) >0 (5) >0 PD Normal Operation PD Normal Operation PD
"10"(3D ON )
"00"
"10"
"00"
(6) >2ms(at 3D OFF), >50ms(at 3D ON)
(6) >2ms, or >50ms
ATTL7-0 ATTR7-0 bits
00H(MUTE)
FFH(0dB) (9) GD (10) 1061/fs (9) (10)
00H(MUTE) (7)
FFH(0dB) (9) (10)
00H(MUTE) (9) (10) (8)
(7) HPL/R pin
(8)
Figure 26. DAC (1) (2) PDN pin (3) DAC 150ns "H"
HP-amp PDN pin "H" PMVCM, PMDAC bit "1" (MCKI, BICK, LRCK) "1"
(Don't care: Hi-Z
)
PMDAC bit = "0" "1" 3D1-0 bits
(4) PMVCM, PMDAC bits (5) 3D (6) 3D 2.2F ) 3D1-0bits (7) (tr) (8) (tf) bits (9) (10) (11) "0" 60k x C(typ) 3D1-0bits 70k x C(typ)
DACHL, DACHR bits DACHL, DACHR bits "1"
"10"
"10"
DACHL, DACHR bits "1" 2ms (VCOM pin PMHPL, PMHPR, MUTEN bits "1" 3D 50ms PMHPL, PMHPR, MUTEN bits "1" MUTET pin (C) tr 70ms(typ) MUTET pin (C) tf 60ms(typ) PMHPL, PMHPR "0" VCOM/2 VCOM/2 DACL, DACR (GD) 1061/fs(=24ms@fs=44.1kHz)
C=1F C=1F "00"
22/fs(=499s@fs=44.1kHz) ATS bit OFF
MS0409-J-01 - 34 -
2005/08
ASAHI KASEI 2) DAC Lineout
Power Supply (1) >150ns PDN pin (2) >0 (6) Clock Input Don't care (5) >0 (at 3D OFF) PMDAC bit DAC Internal State SDTI pin DACL, DACR bits (3) >0 "01"(3D ON) (4) >0 "00" "01" PD(Power-down) (5) >0 (at 3D ON) Normal Operation PD Normal Operation Don't care
[AK4368]
PMVCM bit
Don't care
3D1-0 bits "00"(3D OFF) (when 3D is used) PMLO bit ATTL/R7-0 bits
00H(MUTE)
FFH(0dB)
00H(MUTE)
FFH(0dB)
LMUTE, ATTS3-0 bits
10H(MUTE) (8) GD (9) 1061/fs (8) (9)
0FH(0dB) (8) (7) (Hi-Z) (7) (9)
LOUT/ROUT pins
(Hi-Z)
(7)
Figure 27. DAC (1) 150ns (2) PDN pin "H" (3) PMVCM bit "1" (4) 3D (5) 3D 3D (6) DAC (7) PMLO bit (8) (9)
Lineout PDN pin "H" PMVCM bit "1" DACL, DACR bits "1" DACL, DACR bits "1" DACL, DACR bits "1" 3D1-0bits "01"
(Don't care: Hi-Z
)
3D1-0 bits
"01"
PMDAC, PMLO bits "1" PMDAC, PMLO bits "1"
(MCKI, BICK, LRCK) PMDAC bit = "0" LOUT/ROUT LOUT, ROUT pins 22/fs(=499s@fs=44.1kHz) (GD) ATS bit 1061/fs(=24ms@fs=44.1kHz)
MS0409-J-01 - 35 -
2005/08
ASAHI KASEI 3) LIN/RIN/MIN HP-Amp, Lineout
Power Supply (1) >150ns PDN pin (2) >0 PMVCM bit LINHL, MINHL, RINHR, MINHR LINL, RINR, MINL, MINR bits 3D1-0 bits (when 3D is used) PMHPL/R bits Don't care
[AK4368]
(3) >0
"00" (3D OFF)
(5) >0
"01", "10" or "11" (3D ON)
"00"
"01", "10" or "11" (6) >2ms or >50ms
(6) >2ms(at 3D OFF), >50ms(at 3D ON)
MUTEN bit
PMLO bit
(4) LIN/RIN/MIN pins (Hi-Z) (7) HPL/R pins (8)
(Hi-Z)
(7)
LMUTE, ATTM3-0 bits
10H(MUTE)
0FH(0dB)
MOUT pin
(Hi-Z)
(9)
(9) (Hi-Z)
(9)
Figure 28. LIN/RIN/MIN, HP-amp
LOUT/ROUT (Don't care: Hi-Z
)
150ns PDN pin "H" DAC (MCLK, BICK, LRCK) (2) PDN pin "H" PMVCM bit "1" (3) PMVCM bit "1" LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits
(1)
"1"
(4) LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "1" LIN, RIN, MIN pin 0.475 x AVDD (5) 3D LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "1" 3D1-0bits "01", "10" "11" (Refer to Table 25) (6) 3D LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "1" 2ms (VCOM pin 2.2F ) PMHPL, PMHPR, MUTEN, PMLO bits "1" 3D 3D1-0bits "01", "10" "11" 50ms PMHPL, PMHPR, MUTEN, PMLO bits "1" (7) MUTET pin (C) VCOM/2 (tr) 70k x C(typ) C=1F tr 70ms(typ) (8) MUTET pin (C) VCOM/2 (tf) 60k x C(typ) C=1F tf 60ms(typ) PMHPL, PMHPR bits "0" LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "0" (9) PMLO bit LOUT, ROUT pins
MS0409-J-01 - 36 -
2005/08
ASAHI KASEI
[AK4368]
(PLL Slave mode)
1) DAC HP-Amp
Power Supply PDN pin PMVCM, PMPLL, PMDAC, MCKO bits MCKI pin Unstable MCKO pin Don't care BICK, LRCK pins Unstable DAC Internal State SDTI pin DACHL, DACHR bits 3D1-0 bits (when 3D is used) PMHPL, PMHPR bits MUTEN bit Unstable (6) >0 (7) >0 (6) >0 (7) >0 PD Don't care Normal Operation Unstable PD Unstable Normal Operation PD Don't care (5) Unstable Don't care (4) ~20ms Unstable (4) ~20ms (2) >0 Don't care (3) Don't care (1) >150ns (13)
Don't care
Don't care
"00"(3D OFF)
"10"(3D ON )
"00"
"10"
"00"
(8) >2ms(at 3D OFF), >50ms(at 3D ON)
(8) >2ms, or >50ms
ATTL7-0 ATTR7-0 bits
00H(MUTE)
FFH(0dB) (11) GD (12) 1061/fs (11) (12)
00H(MUTE) (10) (9)
(9) HPL/R pin
FFH(0dB) 00H(MUTE) (11)(12) (11) (12) (10)
Figure 29. DAC (1) (2) (3) (4) (5)
HP-amp
(Don't care: Hi-Z
)
150ns PDN pin "H" PDN pin "H" PMVCM, PMPLL, PMDAC, MCKO bits "1" MCKI pin PLL PLL Table 1 PLL MCKO pin DAC MCKO (BICK, LRCK) DACHL, DACHR bits "1" DACHL, DACHR bits "1"
PMDAC bit = "0" 3D1-0 bits "10"
(6) PLL (7) 3D (8) 3D 2.2F ) 3D1-0bits (9) (tr) (10) (tf) bits (11) (12) (13) "0"
"10"
DACHL, DACHR bits "1" 2ms (VCOM pin PMHPL, PMHPR, MUTEN bits "1" 3D 50ms PMHPL, PMHPR, MUTEN bits "1" C=1F C=1F "00" 22/fs(=499s@fs=44.1kHz) ATS bit OFF (GD) 1061/fs(=24ms@fs=44.1kHz) MUTET pin (C) tr 70ms(typ) MUTET pin (C) tf 60ms(typ) PMHPL, PMHPR "0" VCOM/2 VCOM/2 DACL, DACR
70k x C(typ) 60k x C(typ) 3D1-0bits
MS0409-J-01 - 37 -
2005/08
ASAHI KASEI 2) DAC Lineout
Power Supply (1) >150ns PDN pin PMVCM, PMPLL, PMDAC, MCKO bits MCKI pin Unstable MCKO pin Don't care BICK, LRCK pins Unstable DAC Internal State SDTI pin DACL, DACR bits (6) >0 (7) >0 3D1-0 bits "00"(3D OFF) (when 3D is used) PMLO bit ATTL/R7-0 bits 00H(MUTE) "01"(3D ON) (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) 00H(MUTE) "00" (6) >0 (7) >0 "01" (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) PD Don't care Unstable Normal Operation Unstable PD Unstable Normal Operation Unstable (5) Unstable (4) ~20ms Unstable (4) ~20ms (2) >0 Don't care (3) Don't care
[AK4368]
Don't care
LMUTE, ATTS3-0 bits
10H(MUTE) (10) GD (11) 1061/fs (10) (11) (Hi-Z) (9)
0FH(0dB) (10) (9) (Hi-Z) (9) (11)
LOUT/ROUT pins
Figure 30. DAC (1) (2) (3) (4) (5) 150ns
Lineout
(Don't care: Hi-Z
)
PDN pin "H" PDN pin "H" PMVCM, PMPLL, PMDAC, MCKO bits "1" MCKI pin PLL PLL Table 1 PLL MCKO pin DAC MCKO (BICK, LRCK) PMDAC bit = "0" LOUT/ROUT (6) PLL DACL, DACR bits "1" (7) 3D DACL, DACR bits "1" 3D1-0 bits "01" "1" LOUT, ROUT pins 22/fs(=499s@fs=44.1kHz) ATS bit (GD) 1061/fs(=24ms@fs=44.1kHz)
(8) PMLO bit (9) PMLO bit (10) (11)
MS0409-J-01 - 38 -
2005/08
ASAHI KASEI 3) LIN/RIN/MIN HP-Amp, Lineout
Power Supply (1) >150ns PDN pin (2) >0 PMVCM bit LINHL, MINHL, RINHR, MINHR LINL, RINR, MINL, MINR bits 3D1-0 bits (when 3D is used) PMHPL/R bits Don't care
[AK4368]
(3) >0
"00" (3D OFF)
(5) >0
"01", "10" or "11" (3D ON)
"00"
"01", "10" or "11" (6) >2ms or >50ms
(6) >2ms(at 3D OFF), >50ms(at 3D ON)
MUTEN bit
PMLO bit
(4) LIN/RIN/MIN pins (Hi-Z) (7) HPL/R pins (8)
(Hi-Z)
(7)
LMUTE, ATTM3-0 bits
10H(MUTE)
0FH(0dB)
MOUT pin
(Hi-Z)
(9)
(9) (Hi-Z)
(9)
Figure 31. LIN/RIN/MIN, HP-amp
LOUT/ROUT (Don't care: Hi-Z
)
150ns PDN pin "H" DAC (MCLK, BICK, LRCK) (2) PDN pin "H" PMVCM bit "1" (3) PMVCM bit "1" LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits
(1)
"1"
(4) LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "1" LIN, RIN, MIN pin 0.475 x AVDD (5) 3D LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "1" 3D1-0bits "01", "10" "11" (Refer to Table 25) (6) 3D LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "1" 2ms (VCOM pin 2.2F ) PMHPL, PMHPR, MUTEN, PMLO bits "1" 3D 3D1-0bits "01", "10" "11" 50ms PMHPL, PMHPR, MUTEN, PMLO bits "1" (7) MUTET pin (C) VCOM/2 (tr) 70k x C(typ) C=1F tr 70ms(typ) (8) MUTET pin (C) VCOM/2 (tf) 60k x C(typ) C=1F tf 60ms(typ) PMHPL, PMHPR bits "0" LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "0" (9) PMLO bit LOUT, ROUT pins
MS0409-J-01 - 39 -
2005/08
ASAHI KASEI
[AK4368]
AK4368
1) DAC HP-Amp
Power Supply PDN pin (2) >0 M/S, PMVCM, PMPLL, PMDAC, MCKO bits Don't care (3) MCKI pin Unstable MCKO pin Don't care BICK, LRCK pins Unstable DAC Internal State SDTI pin DACHL, DACHR bits 3D1-0 bits (when 3D is used) PMHPL, PMHPR bits MUTEN bit Unstable (6) >0 (7) >0 PD Don't care "L" (5) (4) ~20ms (1) >150ns
(PLL Master Mode)
(13)
Don't care
Don't care
Don't care
Unstable
(4) ~20ms
Unstable
Don't care
Unstable Normal Operation PD Unstable Normal Operation PD Don't care
(6) >0 (7) >0
"00"(3D OFF)
"10"(3D ON )
"00"
"10"
"00"
(8) >2ms(at 3D OFF), >50ms(at 3D ON)
(8) >2ms, or >50ms
ATTL7-0 ATTR7-0 bits
00H(MUTE)
FFH(0dB) (11) GD (12) 1061/fs (11) (12)
00H(MUTE) (10) (9)
(9) HPL/R pin
FFH(0dB) 00H(MUTE) (11)(12) (11) (12) (10)
Figure 32 DAC (1) (2) PDN pin "H" (3) MCKI pin (4) PLL (5) PLL (6) 3D (7) 3D 2.2F ) 3D1-0bits (8) (tr) (9) (tf) bits (10) (11) (12) "0" 60k x C(typ) 3D1-0bits 70k x C(typ) 150ns
HP-amp
(Don't care: Hi-Z
)
PDN pin "H" PMVCM, PMPLL, PMDAC, MCKO, M/S bits "1" PLL Table 1 PLL BICK, LRCK, MCKO pin DACHL, DACHR bits "1" DACHL, DACHR bits "1" 3D1-0 bits "10"
"10"
DACHL, DACHR bits "1" 2ms (VCOM pin PMHPL, PMHPR, MUTEN bits "1" 3D 50ms PMHPL, PMHPR, MUTEN bits "1" C=1F C=1F "00" 22/fs(=499s@fs=44.1kHz) ATS bit OFF (GD) 1061/fs(=24ms@fs=44.1kHz) MUTET pin (C) tr 70ms(typ) MUTET pin (C) tf 60ms(typ) PMHPL, PMHPR "0" VCOM/2 VCOM/2 DACL, DACR
MS0409-J-01 - 40 -
2005/08
ASAHI KASEI 2) DAC Lineout
Power Supply (1) >150ns PDN pin M/S, PMVCM, PMPLL, PMDAC, MCKO bits MCKI pin Unstable MCKO pin Don't care BICK, LRCK pins Unstable DAC Internal State SDTI pin DACL, DACR bits (6) >0 (7) >0 3D1-0 bits "00"(3D OFF) (when 3D is used) PMLO bit ATTL/R7-0 bits LMUTE, ATTS3-0 bits 00H(MUTE) "01"(3D ON) (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) 00H(MUTE) "00" (6) >0 (7) >0 "01" (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) PD Don't care Unstable Normal Operation Unstable PD Unstable Normal Operation "L" (5) Unstable (4) ~20ms Unstable (4) ~20ms (2) >0 (3) Don't care
[AK4368]
Don't care
Don't care
10H(MUTE) (10) GD (11) 1061/fs (10) (11) (Hi-Z) (9)
0FH(0dB) (10) (9) (Hi-Z) (9) (11)
LOUT/ROUT pins
Figure 33. DAC (1) (2) PDN pin "H" (3) MCKI pin (4) PLL (5) PLL (6) 3D (7) PMLO bit (8) PMLO bit (9) (10) "1" 150ns
Lineout
(Don't care: Hi-Z
)
PDN pin "H" PMVCM, PMPLL, PMDAC, MCKO, M/S bits "1" PLL Table 1 PLL BICK, LRCK, MCKO pin DACL, DACR bits "1" DACL, DACR bits "1"
3D1-0 bits "01"
LOUT, ROUT pins 22/fs(=499s@fs=44.1kHz) ATS bit
(GD) 1061/fs(=24ms@fs=44.1kHz)
MS0409-J-01 - 41 -
2005/08
ASAHI KASEI 3) LIN/RIN/MIN HP-Amp, Lineout
Power Supply (1) >150ns PDN pin (2) >0 PMVCM bit LINHL, MINHL, RINHR, MINHR LINL, RINR, MINL, MINR bits 3D1-0 bits (when 3D is used) PMHPL/R bits Don't care
[AK4368]
(3) >0
"00" (3D OFF)
(5) >0
"01", "10" or "11" (3D ON)
"00"
"01", "10" or "11" (6) >2ms or >50ms
(6) >2ms(at 3D OFF), >50ms(at 3D ON)
MUTEN bit
PMLO bit
(4) LIN/RIN/MIN pins (Hi-Z) (7) HPL/R pins (8)
(Hi-Z)
(7)
LMUTE, ATTM3-0 bits
10H(MUTE)
0FH(0dB)
MOUT pin
(Hi-Z)
(9)
(9) (Hi-Z)
(9)
Figure 34. LIN/RIN/MIN, HP-amp
LOUT/ROUT (Don't care: Hi-Z
)
150ns PDN pin "H" DAC (MCLK, BICK, LRCK) (2) PDN pin "H" PMVCM bit "1" (3) PMVCM bit "1" LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits
(1)
"1"
(4) LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "1" LIN, RIN, MIN pin 0.475 x AVDD (5) 3D LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "1" 3D1-0bits "01", "10" "11" (Refer to Table 25) (6) 3D LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "1" 2ms (VCOM pin 2.2F ) PMHPL, PMHPR, MUTEN, PMLO bits "1" 3D 3D1-0bits "01", "10" "11" 50ms PMHPL, PMHPR, MUTEN, PMLO bits "1" (7) MUTET pin (C) VCOM/2 (tr) 70k x C(typ) C=1F tr 70ms(typ) (8) MUTET pin (C) VCOM/2 (tf) 60k x C(typ) C=1F tf 60ms(typ) PMHPL, PMHPR bits "0" LINHL, MINHL, RINHR, MINHR, LINL, MINL, RINR, MINR bits "0" (9) PMLO bit LOUT, ROUT pins
MS0409-J-01 - 42 -
2005/08
ASAHI KASEI
[AK4368]
(1) 3
3 address(2bits, "01" data(MSB first, 8bits) CCLK 16 PDN pin = "L"
(I2C pin = "L") I/F : CSN, CCLK, CDTI I/F Chip ), Read/Write(1bit, Fixed to "1", Write only), Register address(MSB first, 5bits), Control CCLK CCLK 5MHz(max)
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: R/W: A4-A0: D7-D0: Figure 35. 3
Chip Address (Fixed to "01") READ/WRITE (Fixed to "1", Write only) Register Address Control Data I/F
MS0409-J-01 - 43 -
2005/08
ASAHI KASEI
[AK4368]
(2) I2C AK4368
(I2C pin = "H")
I2C (max:400kHz, Ver1.0)
(2)-1. WRITE I2C (Start Condition) (Figure 42) 8bit IC AK4368 SDA "1" 2 (Figure 38) (Figure 39) "L" AK4368 "0CH" "00H" "H" SDA
S T A R T
SCL (R/W) CAD0 pin
Figure 36 "H"
SDA 6bit "001000" (Figure 37)
IC "H"
"L" 7bit 1bit
(Acknowledge) (Figure 43) R/W "0" R/W
( 3 AK4368
)
8bit MSB first
3bit 8bit MSB first "H" SDA
"0"
"H"
(Stop Condition) (Figure 42)
SCL
1
SDA SCL
"L"
(Figure 44)
"H" SCL
"L" "H"
R/W= "0"
S T O P Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P
SDA
S
Slave Address A C K
Sub Address(n)
Figure 36. I2C
0
0
1
0
0 )
0
CAD0
R/W
(CAD0 pin Figure 37. 1
0
0
0
A4 2
A3
A2
A1
A0
Figure 38.
D7
D6
D5 Figure 39.
D4 3
D3
D2
D1
D0
MS0409-J-01 - 44 -
2005/08
ASAHI KASEI
[AK4368]
(2)-2. READ R/W "1"
AK4368
READ "0CH"
"00H" AK4368 (2)-2-1. AK4368 (READ WRITE "n+1" (R/W = "1") ) "n" 2 READ
AK4368
READ
1 READ
S T A R T R/W= "1" S T O P Data(n+1) A C K A C K Data(n+2) A C K A C K Data(n+x) A C K P
SDA
S
Slave Address A C K
Data(n)
Figure 40. CURRENT ADDRESS READ (2)-3-2. READ "0") READ (R/W bit= "1") AK4368 (R/W bit= "1") WRITE WRITE AK4368 1 READ
S T A R T S T A R T S A C K Slave Address A C K S T O P Data(n+1) A C K A C K A C K Data(n+x) A C K P
(R/W =
R/W= "0"
R/W= "1"
SDA
S
Slave Address A C K
Sub Address(n)
Data(n)
Figure 41. RANDOM ADDRESS READ
MS0409-J-01 - 45 -
2005/08
ASAHI KASEI
[AK4368]
SDA
SCL S start condition P stop condition
Figure 42.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S clock pulse for acknowledgement
1
2
8
9
START CONDITION
Figure 43. I2C
SDA
SCL
data line stable; data valid
change of data allowed
Figure 44. I2C
MS0409-J-01 - 46 -
2005/08
ASAHI KASEI
[AK4368]
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH
Register Name Power Management PLL Control Clock Control Mode Control 0 Mode Control 1 DAC Lch ATT DAC Rch ATT Headphone Out Select Lineout Select Lineout ATT ALC Mode Control 1 ALC Mode Control 2 3D Control
D7 0 FS3 0 0 ATS ATTL7 ATTR7 0 0 0 REF7 0 0
D6 PMPLL FS2 0
MONO1 DATTC
D5 PMLO FS1 M/S
MONO0
LMUTE
D4
MUTEN
D3
PMHPR
D2
PMHPL PLL2
D1
PMDAC
D0
PMVCM
FS0
MCKAC
BCKP
SMUTE
ATTL6 ATTR6 HPG LOG 0 REF6 0 0
ATTL5 ATTR5
MINHR MINR
ATTL4 ATTR4
MINHL MINL
PLL3 BF LRP BST1 ATTL3 ATTR3
RINHR RINR ATTS3
PS0 DIF2 BST0 ATTL2 ATTR2
LINHL LINL ATTS2
PLL1 PS1 DIF1 DEM1 ATTL1 ATTR1
DACHR DACR ATTS1
PLL0 MCKO DIF0 DEM0 ATTL0 ATTR0
DACHL DACL ATTS0
0 REF5 ALC 0
0 REF4
ROTM1
REF3
ROTM0 DP1
REF2
LMAT1 DP0
REF1
LMAT0 3D1
REF0
RATT 3D0
0
PDN pin = "L" PDN pin "L" 0DH 1FH "0"
"1"
MS0409-J-01 - 47 -
2005/08
ASAHI KASEI
[AK4368]
Addr 00H
Register Name Power Management R/W Default
D7 0 RD 0
D6 PMPLL R/W 0
D5 PMLO R/W 0
D4
MUTEN
D3
PMHPR
D2
PMHPL
D1
PMDAC
D0
PMVCM
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
PMVCM: VCOM 0: Power OFF (Default) 1: Power ON PMDAC: DAC 0: Power OFF (Default) 1: Power ON OFF ON PMHPL: Lch 0: Power OFF (Default) 1: Power ON PMHPR: Rch 0: Power OFF (Default) 1: Power ON MUTEN: 0: 1: PMLO: 0: Power OFF (Default) 1: Power ON Hi-Z
ATT
(Default) DC
HVSS(0V) 0.475 x AVDD
PMPLL: PLL 0: Power OFF: EXT mode (Default) 1: Power ON: PLL mode ON/OFF PDN pin "L" "0" "1" /"0"
PMVCM, PMDAC, PMHPL, PMHPR, PMLO, PMPLL, MCKO bits 20A(typ) Addr 01H Register Name PLL Control R/W Default FS3-0: PLL mode: Table 2 EXT mode: Table 6 D7 FS3 R/W 1 (typ. 1A) D6 FS2 R/W 0 D5 FS1 R/W 0 PDN pin = "L" D4 FS0 R/W 0 D3 PLL3 R/W 0
D2
PLL2
R/W 0
D1 PLL1 R/W 0
D0 PLL0 R/W 0
PLL3-0: MCKI PLL mode: Table 1 EXT mode:
MS0409-J-01 - 48 -
2005/08
ASAHI KASEI
[AK4368]
Addr 02H
Register Name Clock Control R/W Default
D7 0 RD 0
D6 0 RD 0
D5 M/S R/W 0
D4
MCKAC
R/W 0
D3 BF R/W 0
D2 PS0 R/W 0
D1 PS1 R/W 0
D0 MCKO R/W 0
MCKO: MCKO 0: Disable (Default) 1: Enable PS1-0: MCKO PLL mode: Table 3 EXT mode: Table 7 BF: BICK 0: 32fs (Default) 1: 64fs
MCKAC: MCLK 0: CMOS 1: AC M/S: 0: 1: /
(Default)
(Default)
Addr 03H
Register Name Mode Control 0 R/W Default
D7 0 RD 0
D6
MONO1
D5
MONO0
R/W 0
R/W 0
D4 BCKP R/W 0
D3 LRP R/W 0
D2 DIF2 R/W 0
D1 DIF1 R/W 1
D0 DIF0 R/W 0
DIF2-0: Default: "010" (Mode 2) LRP: LRCK 0: 1: ( (Default) )
(Table 11)
BCKP: BICK ( 0: (Default) 1: MONO1-0: Default: "00" (LR) (Table 21)
)
MS0409-J-01 - 49 -
2005/08
ASAHI KASEI
[AK4368]
Addr 04H
Register Name Mode Control 1 R/W Default
D7 ATS R/W 0
D6
DATTC
D5
LMUTE
D4
SMUTE
R/W 0
R/W 1
R/W 0
D3 BST1 R/W 0
D2 BST0 R/W 0
D1 DEM1 R/W 0
D0 DEM0 R/W 1
DEM1-0: Default: "01" (OFF) BST1-0: (Table 20) Default: "00" (OFF) SMUTE: DAC 0: 1: DAC
(Table 19)
(Default)
LMUTE: LOUT/ROUT 0: ATTS3-0 bits 1: Mute ATTS3-0 bits DATTC: 0: Independent (Default) 1: Dependent "0" Lch, Rch DATTC bit = "1"
(Table 24) (Default)
"1" Lch ATT ATTR7-0 bit ATTL7-0 bit
Rch
ATT
ATS: 0: 1061/fs (Default) 1: 7424/fs
(Table 18)
Addr 05H 06H
Register Name DAC Lch ATT DAC Rch ATT R/W Default
D7 ATTL7 ATTR7 R/W 0
D6 ATTL6 ATTR6 R/W 0
D5 ATTL5 ATTR5 R/W 0
D4 ATTL4 ATTR4 R/W 0
D3 ATTL3 ATTR3 R/W 0
D2 ATTL2 ATTR2 R/W 0
D1 ATTL1 ATTR1 R/W 0
D0 ATTL0 ATTR0 R/W 0
ATTL7-0: DACL ATTR7-0: DACR Default: "00H" (MUTE)
(Table 17) (Table 17)
MS0409-J-01 - 50 -
2005/08
ASAHI KASEI
[AK4368]
Addr 07H
Register Name Headphone Out Select R/W Default
D7 0 RD 0
D6 HPG R/W 0
D5
MINHR
D4
MINHL
D3
RINHR
D2
LINHL
D1
DACHR
D0
DACHL
R/W 0 Lch
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
DACHL: DAC Lch 0: OFF (Default) 1: ON DACHR: DAC Rch 0: OFF (Default) 1: ON LINHL: LIN pin 0: OFF (Default) 1: ON RINHR: RIN pin 0: OFF (Default) 1: ON MINHL: MIN pin 0: OFF (Default) 1: ON MINHR: MIN pin 0: OFF (Default) 1: ON HPG: DAC HPL/R Gain 0: +0.76dB (Default) 1: +6.76dB
Rch
Lch
Rch
Lch
Rch
MS0409-J-01 - 51 -
2005/08
ASAHI KASEI
[AK4368]
Addr 08H
Register Name Lineout Select R/W Default
D7 0 RD 0 LOUT
D6 LOG R/W 0
D5
MINR
D4
MINL
D3
RINR
D2
LINL
D1
DACR
D0
DACL
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
DACL: DAC Lch 0: OFF (Default) 1: ON DACR: DAC Rch 0: OFF (Default) 1: ON LINL: LIN pin 0: OFF (Default) 1: ON RINR: RIN pin 0: OFF (Default) 1: ON MINL: MIN pin 0: OFF (Default) 1: ON MINR: MIN pin 0: OFF (Default) 1: ON
ROUT
LOUT
ROUT
LOUT
ROUT
LOG: DAC LOUT/ROUT Gain 0: 0dB (Default) 1: +6dB
Addr 09H
Register Name Lineout ATT R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 RD 0
D4 0 RD 0
D3
ATTS3
D2
ATTS2
D1
ATTS1
D0
ATTS0
R/W 0
R/W 0
R/W 0
R/W 0
ATTS3-0: LOUT/ROUT (Table 24) Default: LMUTE bit = "1", ATTS3-0 bits = "0000" (MUTE) ATTS3-0 bit LMUTE bit "0"
MS0409-J-01 - 52 -
2005/08
ASAHI KASEI
[AK4368]
Addr 0AH
Register Name ALC Mode Control 1 R/W Default
D7 REF7 R/W 1
D6 REF6 R/W 0
D5 REF5 R/W 0
D4 REF4 R/W 1
D3 REF3 R/W 0
D2 REF2 R/W 0
D1 REF1 R/W 0
D0 REF0 R/W 1
REF7-0: ALC
, 0.375dB step, 81 level, Default: "91H" (Table 15)
Addr 0BH
Register Name ALC Mode Control 2 R/W Default
D7 0 RD 0
D6 0 RD 0 (Table 14)
D5 ALC R/W 0
D4
ROTM1
D3
ROTM0
D2
LMAT1
D1
LMAT0
D0
RATT
R/W 0
R/W 1
R/W 0
R/W 0
R/W 0
RATT: ALC LMAT1-0: ALC ROTM1-0: ALC ALC: ALC 0: ALC Disable (Default) 1: ALC Enable ATT ,
(Table 13) (Table 12)
Addr 0CH
Register Name 3D Control R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 RD 0
D4
0
D3
DP1
D2
DP0
D1
3D1
D0
3D0
RD 0
R/W 0
R/W 0
R/W 0
R/W 0
3D1-0: 3D Stereo Enhancement Enable (Table 25) Default: "00" (Disable) DP1-0: 3D Depth (Table 26) Default: "00" (0%)
MS0409-J-01 - 53 -
2005/08
ASAHI KASEI
[AK4368]
Figure 45
Analog Supply 1.63.6V
220 + + 220 16 16
NC HPR HVSS HVDD AVDD VCOM LOUT NC
+
10
0.1 2.2 0.1 1
Speaker
SPK-Amp
Headphone
HPL
AVSS
MUTET
ROUT 3DCAP2 3DCAP3
470n 4.7n
MIN
NC
NC
3DCAP1
RIN
NC
Top View
NC
PDN
NC
Cp
Rp 0.1 10
VCOC
LIN
NC
CAD0/ CSN SCL/ CCLK NC
PVDD NC
PVSS MCKO
DVSS DVDD
I2C MCKI
LRCK BICK
SDATA
SDA/ CDTI
0.1 1000p
Audio Controller
P
: - AK4368 - EXT - PLL -
AVSS, PVSS, DVSS, HVSS (PMPLL bit = "0") (PMPLL bit = "1") VCOC pin Cp Rp Table 1 M/S bit "1" AK4368 LRCK, BICK pins AK4368 LRCK, BICK pins 100k
Figure 45.
(MCLK
AC
)
MS0409-J-01 - 54 -
2005/08
ASAHI KASEI
[AK4368]
1. AVDD, PVDD, HVDD DVDD AVDD 10 AVDD DVSS, PVSS, HVSS PC HVDD PVDD AVDD DVDD AVDD HVDD OFF HVDD AVSS,
2. AVDD VCOM 0.475 x AVDD VCOM pin AVDD pin 3. DAC VCOM VCOM 0.47xAVDD(typ)@-3dBFS LOUT/ROUT 0.61xAVDD(typ)@0dBFS 2's 800000H(@24bit) VCOM (typ) 2.2F VCOM pin AVSS AVDD AVSS 0.1F
(
VCOM (2 ) 7FFFFFH(@24bit) 000000H(@24bit) )
VCOM+ mV
DC
DC
MS0409-J-01 - 55 -
2005/08
ASAHI KASEI
[AK4368]
0.05
M S AB
7 6 5 4 3 2 1 A B
A
4.0 0.1
41 - 0.3 0.05
B
4.0 0.1
C
3.0
D E F G
0.5 3.0
0.5
S
: : BT : SnAgCu
MS0409-J-01 - 56 -
0.25 0.05
0.08 S
1.0MAX
2005/08
ASAHI KASEI
[AK4368]
4368
XXXX
XXXX: Date code (4 digit) Pin #1 indication
Date (YY/MM/DD) 05/08/29 05/08/31
Revision 00 01
Reason
Page 5
Contents
AVSS pin AVSS pin 55 2.
2.2F 2.2F
0.1F
2.2F 0.1F AVSS 2.2F AVSS
MS0409-J-01 - 57 -
2005/08
ASAHI KASEI
[AK4368]
*
* * * ( )
* *
MS0409-J-01 - 58 -
2005/08

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