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| YMF795 APL-2 Automobile sound Player-2 Outline YMF795 is a sound source LSI to reproduce high quality melody and effect sound for in-car product. Yamaha's original FM synthesizer embedded as a sound source can create various timbres, and also a sequencer embedded can simultaneously generate up to four sounds with four different timbres without giving load to the controller. Serial port is prepared as a controller interface, and no restriction of data capacity is present because melody data is reproduced in real-time through FIFO. A built-in amplifier to drive the dynamic speaker with 500mW power allows connecting a speaker directly. This LSI is equipped with an analog-output pin also for the earphone jack. In addition, supporting the standby mode can reduce the consumption current to 1 A during the standby. Features YAMAHA's original FM sound source function Built-in sequencer Capable of producing up to 4 different sounds simultaneously (4 independent timbres available). 500mW output speaker amplifier Sound quality correcting equalizer circuit Serial interface Arbitrary frequency of input clock from 2.685 MHz to 27.853 MHz in 55.93 kHz steps, as well as 2.688, 8.4, 12.6, 14.4, 19.2, 19.68, 19.8, and 27.82 MHz clock inputs Analog output for earphone Power-down mode (Typ. 1A or less) Supply voltage (Digital and Analog): 3.3V10 % 24-pin SSOP. The plating of pins is lead-free. (YMF795-EZ) YAMAHA CORPORATION YMF795 CATALOG CATALOG No.:LSI-4MF795A20 2005. 11 YMF795 Contents General Description of YMF795 .................................................................................................................. 3 Block Description ......................................................................................................................................... 4 Pin Configuration.......................................................................................................................................... 5 Pin Description ............................................................................................................................................. 6 Block Diagram.............................................................................................................................................. 7 Register Map................................................................................................................................................. 8 Explanation of Registers............................................................................................................................... 9 Musical score data register .................................................................................................................... 9 Timbre data register............................................................................................................................. 14 Other control data ................................................................................................................................ 17 Power-down control division diagram........................................................................................................ 21 Explanation of each bit ............................................................................................................................... 21 On Reset ..................................................................................................................................................... 24 Settings and Procedure required for a piece generation.............................................................................. 24 Clock Frequency Setting............................................................................................................................. 24 On Interrupt Sequence ................................................................................................................................ 25 State Transition ........................................................................................................................................... 26 Operation in FIFO empty condition............................................................................................................ 28 Reproduction method assuming occurrence of empty state........................................................................ 28 Example of peripheral circuit...................................................................................................................... 29 (1) Circuit diagram and wiring diagram when two power supplies are used: ............................................... 30 (2) Circuit diagram and wiring diagram when one power supply and one voltage regulator IC are used: ... 31 Volume level Adjustment in monophonic sound and 4-sound generation ................................................. 33 Sound Quality Correction Circuit ............................................................................................................... 35 Serial I/F Specifications.............................................................................................................................. 37 Electrical Characteristics ............................................................................................................................ 38 General description of FM sound generator ............................................................................................... 43 External dimensions.................................................................................................................................... 44 -2- YMF795 General Description of YMF795 YMF795 is controlled through the serial interface. Internal configuration the LSI has is shown below. Volume, power management, etc. SDIN SYNC SCLK Serial interface Timbre Data Musical score data Timbre register Tempo START/STOP Timbre allocation HPOUT /IRQ FIFO 32word Sequencer FM Synthesizer D/A + Volume AMP SPOUT Data inputted to the serial interface is converted into the parallel data and transferred to each function block according to its index address. The musical score data is stored in the 32-word FIFO first and then transferred to the sequencer which interprets data to control sound generation of the FM synthesizer. The timbre register is where up to 8 timbre data can be stored. And, as the sequencer controlling register, registers for start/stop and tempo are provided. In order to have sound generate, the following controls must be performed to this LSI. 1) Initial status setting (cancellation of power-down, clock selection, etc). 2) Timbre data setting. 3) Writing of the musical score data into FIFO before starting the sequence. 4) To write the next musical score data write before the FIFO becomes empty, and to receive the interrupt signal from FIFO during reproduction. (For the details, refer to "Settings and procedure required for a piece generation" (P.24). -3- YMF795 Block Description 1) Serial interface block The block receives serial data and then identifies its Index data to send control data to each function block. 2) FIFO block FIFO temporarily stores musical score data. Musical score data up to 32 can be stored. The musical score data are processed in the sequencer when they are generated as sounds and those processed are deleted one after another. When the amount of remaining data amount in FIFO reaches the value or less of register setting (IRQ point), it outputs an interrupt signal to the outside to request the subsequent musical score data. 3) Sequencer block When the sequencer receives the START command, it sequentially starts reading the musical score data which have been stored in FIFO. The processed musical score data are deleted. 4) Timbre register block The block stores timbre data in this register which can set up to 8 timbres. Settings of this register must be completed before sound generation. The register is initialized by hardware reset; however, in the following operations, contents of a register are not cleared, and the value written last is held. * Software reset (CLR bit of Index32h) * During power-down mode, and after its cancellation. 5) FM synthesizer block The block synthesizes and generates timbres according to settings. Four sounds can be generated at the same time. 6) D/A, volume, and amplifier blocks The output from the synthesizer is D/A-converted, and volume processing is performed. After that, the data is output from the speaker or the earphone output pin. -4- YMF795 Pin Configuration CLK_I 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 TESTO /RST SDIN SYNC SCLK /TESTI /IRQ DVDD DVSS SPOUT2 SPOUT1 SPVSS SPVSS AVDD AVDD < 24-pin SSOP TOP VIEW > -5- YMF795 Pin Description No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Note : Pin CLK_I I/O Ish I I Ish A AO AO AI AO Clock input pin Be sure to use in no-connection. Function The pin is nowhere connected in the chip. Serial I/F data input Serial I/F synchronous signal input Serial I/F bit clock input Be sure to use in no-connection. The pin is nowhere connected in the chip. Analog ground Analog reference voltage pin Connect a 0.1 F capacitor between this pin and analog ground pin. Analog output pin for earphone Equalizer pin 1 Equalizer pin 2 Equalizer pin 3 Analog power supply (+3.3V) Connect 0.1 F and 4.7 F capacitors between this pin and analog ground pin Analog ground exclusively used for speaker Speaker output pin 1 Speaker output pin 2 Digital ground Digital power supply (+3.3 V) Connect 0.1 F and 4.7 F capacitors between this pin and digital ground pin. Interrupt signal output LSI test input pin (Be sure to connect to DVDD.) Hardware reset pin LSI TEST output pin (Be sure to use in no-connection) A0 = Analog output pin SPVSS SPOUT1 SPOUT2 DVSS DVDD /IRQ /TESTI /RST TESTO Ish = Schmitt input pin AO AO O I I O AI = Analog input pin -6- YMF795 Block Diagram HPOUT DVDD CLK_I AVDD DVSS Timing Generator Power down Control HPVOL 32-step AVSS SCLK SYNC SDIN Register Serial VREF + I/F FIFO 16bx32w Sequencer Simultaneous sound generation 4-tone - EQ3 /IRQ VREF SPVOL 32-step SPOUT1 AMP SPOUT2 /RST VREF SPVSS Concerning AIN signal inputted into equalizer circuit It is possible to make the analog mixing between synthesizer output and other analog source in the equalizer circuit and output the resulting sound through the speaker. -7- CR circuit for EQ FM Synthesizer DAC FMVOL 32-step EQ1 EQ2 AIN * YMF795 Register Map Index $00h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 TI3 TI3 b5 TI2 TI2 b4 TI1 TI1 b3 TI0 b2 b1 b0 Description Note data Rest data Timbre data (for 1 Operator) Timbre allocation data Tempo data FM Control CLK_I select IRQ Control BL1 BL0 NT3 NT2 NT1 NT0 CH1 CH0 VIB 0 0 1 1 0 0 CH1 CH0 VCHE TK2 TK1 TK0 TI0 VCH2 VCH1 VCH0 $10 - 2Fh ML2 ML1 ML0 VIB EGT SUS RR3 RR2 RR1 RR0 DR3 DR2 DR1 DR0 AR3 AR2 AR1 AR0 SL3 $30h $31h $32h $33h $34h $35h $36h $37h $38h $39h $40 - EFh $F0 - FFh 0 0 0 0 0 0 0 0 0 0 SL2 SL1 0 0 0 0 0 0 0 0 0 0 SL0 TL5 TL4 TL3 0 T7 0 0 0 0 0 0 0 TL2 TL1 TL0 WAV FL2 0 T3 0 0 FL1 FL0 V32 V31 V30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V22 V21 V20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V12 V11 V10 T6 0 0 0 0 0 0 0 T5 0 0 IRQE V02 V01 V00 T2 0 T1 CLR CLKSEL IRQ Point T0 ST T4 0 0 0 0 0 0 V4 V4 V4 V3 V3 V3 V2 V2 V2 V1 V1 V1 V0 V0 V0 DP Speaker Volume FM Volume HPOUT Volume Power Management CLK_I Select Reserved LSI TEST AP4 AP3 AP2 AP1 CLKSET Reserved (access prohibited) For LSI TEST(access prohibited) Note : Access to the spaces of "Reserved" and "For LSI TEST" in the above table is prohibited. Be sure to write "0" to the empty bit, although writing "1" there will not affect the LSI operation. -8- YMF795 Explanation of Registers The YMF795 has three types of control registers: musical score data, timbre data, and other control data. Musical score data register $00h Musical score data The musical score data are written into the 32-word FIFO. There are two types of musical score data: note data and rest data. Note data Index $00h Default: 0000h B15 BL1 b14 BL0 b13 NT3 b12 NT2 b11 NT1 b10 NT0 b9 CH1 b8 CH0 b7 VIB b6 TI3 b5 TI2 b4 TI1 b3 TI0 b2 TK2 b1 TK1 b0 TK0 BL1 - BL0 : Octave block setting Three octave blocks are available for sound range setting. The setting range is 1 to 3. Do not set "0." In addition, the sound generation range is affected by the coefficient called "Multiple (multiplying factor for sound generation frequency)." By combining the octave block and Multiple settings, sounds can be generated in the range as listed in the table blow. Since the setting range of "Multiple" coefficient is 0 to 7, actually, sounds wider than those given in the table below can be generated. Multiple = 1 (x1) C#3 (139Hz) D3 (147Hz) D#3 (156Hz) E3 (165Hz) F3 (175Hz) F#3 (185Hz) G3 (196Hz) G#3 (208Hz) A3 (220Hz) A#3 (233Hz) B3 (247Hz) C4 (262Hz) C#4 (277Hz) D4 (294Hz) D#4 (311Hz) E4 (330Hz) F4 (349Hz) F#4 (370Hz) G4 (392Hz) G#4 (415Hz) A4 (440Hz) A#4 (466Hz) B4 (494Hz) C5 (523Hz) C#5 (554Hz) D5 (587Hz) D#5 (622Hz) E5 (659Hz) F5 (698Hz) F#5 (740Hz) G5 (784Hz) G#5 (831Hz) A5 (880Hz) A#5 (932Hz) B5 (988Hz) C6 (1046Hz) Multiple = 2 (x2) C#4 (277Hz) D4 (294Hz) D#4 (311Hz) E4 (330Hz) F4 (349Hz) F#4 (370Hz) G4 (392Hz) G#4 (415Hz) A4 (440Hz) A#4 (466Hz) B4 (494Hz) C5 (523Hz) C#5 (554Hz) D5 (587Hz) D#5 (622Hz) E5 (659Hz) F5 (698Hz) F#5 (740Hz) G5 (784Hz) G#5 (831Hz) A5 (880Hz) A#5 (932Hz) B5 (988Hz) C6 (1046Hz) C#6 (1109Hz) D6 (1175Hz) D#6 (1245Hz) E6 (1319Hz) F6 (1397Hz) F#6 (1480Hz) G6 (1568Hz) G#6 (1661Hz) A6 (1760Hz) A#6 (1865Hz) B6 (1976Hz) C7 (2093Hz) Multiple = 4 (x4) C#5 (554Hz) D5 (587Hz) D#5 (622Hz) E5 (659Hz) F5 (698Hz) F#5 (740Hz) G5 (784Hz) G#5 (831Hz) A5 (880Hz) A#5 (932Hz) B5 (988Hz) C6 (1046Hz) C#6 (1109Hz) D6 (1175Hz) D#6 (1245Hz) E6 (1319Hz) F6 (1397Hz) F#6 (1480Hz) G6 (1568Hz) G#6 (1661Hz) A6 (1760Hz) A#6 (1865Hz) B6 (1976Hz) C7 (2093Hz) C#7 (2217Hz) D7 (2349Hz) D#7 (2489Hz) E7 (2637Hz) F7 (2794Hz) F#7 (2960Hz) G7 (3136Hz) G#7 (3322Hz) A7 (3520Hz) A#7 (3729Hz) B7 (3951Hz) C8 (4186Hz) BL[1:0] = 01b BL[1:0] = 10b BL[1:0] = 11b -9- YMF795 NT3 - NT0 : Pitch setting Four bits from NT3 to 0 are used to specify the pitch. The bit assignment is as follows. NT[3:0] 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh Pitch Setting Prohibited C# D D# Setting Prohibited E F F# Setting Prohibited G G# A Setting Prohibited A# B C About "Setting Prohibited." Although LSI never hangs, unusual sound may be generated. Never set it. CH1 - CH0 : Part setting As the sound source section can simultaneously generate sounds in 4 parts, set the part of a note by using CH1 and 0 bits. CH[1:0] 00b 01b 10b 11b Part setting 0 1 2 3 VIB : Vibrato setting This bit is used to set ON/OFF of Vibrato function for each note: "0" for OFF and "1" for ON. The vibrato frequency is 6.4 Hz and the modulation depth is 13.47 cent. Note that Vibrato function becomes OFF when VIB bit of timbre data ($10-2Fh) is "0." -10- YMF795 TI3 - TI0 : Interval setting These bits are used to set the interval time before the processing of the next note and rest. The interval "48" represents the time for the whole note. TI [3:0] 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh Interval 0 2 3 4 6 8 9 12 18 24 48 0 16 24 36 48 TK2 - TK0 : Note (sound length) designation These 3 bits are used to designate the note (sound length). Depending on the value of interval setting (TI3 - 0), the length varies as shown in the following table. The interval "48" represents the time for the whole note. TI [3:0] = 0 to Ah TK[2:0] Sound length 0 1 1 2 2 3 3 5 4 7 5 8 6 11 7 17 0 15 1 23 2 29 TI [3:0] 3 32 = B to Fh 4 35 5 41 6 47 7 Tie, Slur -11- YMF795 Caution When KEY is turned on again while release rate is not completely finished yet in the same channel, timbre may change. This happens in both sustained sound and decaying sound. The reason why it happens is that both envelope and phase in the career side and modulator side of the FM sound source deviate. The hardware creating the phase and envelope of FM sound source starts its operation according to the following two conditions. - End of the release rate. - Occurrence of Key ON. Timbre data is created on the assumption that modulator, phase between careers, and envelope operate at the same timing; therefore, timbre may vary when this condition is not met. Description mentioned above is explained with the envelope waveform. For example, assume that a timbre of which only release time differs between carrier and modulator is present. If operation is in the state completely stopped, it shifts to the Attack rate in conjunction with KEY ON. If the previous sound generation is being released and is not in a state completely stopped, the release settings is forcibly hastened (8.94 ms) and a stopped state is shifted to the attack rate state. (Dotted line of A) Although envelope indicated in a solid line changes to the attack rate state soon at the second KEY ON, shifting to the attack rate state is not immediately performed because sound indicated in a dotted line is not completely stopped. The release time is hastened to stop the state, and then the state stopped is shifted to the attack rate state. The starting time deviation of both envelopes and phase caused by this deviation causes a change of timbre. Timbre varies. A TK TI TK How to avoid this symptom: Be sure to observe "Try to pronounce under the condition that the release is completely stopped." -12- YMF795 Rest data Index $00h Default: 0000h b15 0 b14 0 b13 1 b12 1 b11 0 b10 0 b9 CH1 b8 CH0 b7 b6 b5 TI2 b4 TI1 b3 TI0 b2 b1 b0 VCHE TI3 VCH2 VCH1VCH0 CH1 - CH0 : Part setting Using CH1 or 0 bit, set the part of each rest. CH[1:0] 00b 01b 10b 11b Part designation 0 1 2 3 TI3 - TI0 : Interval setting These bits are used to set the interval time before the processing of the next note and rest. The interval "48" represents the time for the whole note. The following table is exactly the same as that for the note data. TI [3:0] 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh Interval 3 2 3 4 6 8 9 12 18 24 48 1 16 24 36 48 VCHE, VCH2 - VCH0 : Timbre change function Although the maximum number of timbres that can be simultaneously used is four, the timbre can be changed during sound reproduction by setting these bits. Set VCHE to "1" and set a timbre number by using VCH2 to VCH0. Switching of timbre in rest data is made according to the designated time of the sequence data. After the next note to generate, the timbre in a part specified by CH0 and CH1 will be changed. Make the change of a timbre after sound generation of a part to change is completely stopped. The state at which sound generation is completely stopped is not a state where TK (sound length) is ended but a state where release time of envelope is completed. Note that unusual sound may be instantaneously generated if switching the timbre while sound generation is not completely stopped. If the timbre allocation is changed by using this function, the $30h register itself will be rewritten. -13- YMF795 Timbre data register $10 - 2Fh Timbre data Eight timbre data can be registered into the register and four data out of them can be simultaneously reprodu ced. Timbre is made by setting both [parameters for the modulator] and [parameters for the carrier]. (For details of the modulator and the carrier, please refer to "General description of FM sound generator" (page 41)). Index 10h, 11h ...... 1st timbre_ timbre data for the modulator Index 12h, 13h ...... 1st timbre_ timbre data for the carrier Index 14h, 15h ...... 2nd timbre_ timbre data for the modulator Index 16h, 17h ...... 2nd timbre_ timbre data for the carrier ...............Omitted................ Index 2Ch, 2Dh ...... 8th timbre_ timbre data for the modulator Index 2Eh, 2Fh ...... 8th timbre_ timbre data for the carrier The following bit assignment is used for both modulator and carrier. The setting must be completed before any sound is generated. Change of the timbre parameter during sound generation is prohibited. Timbre data Index EVEN ODD B15 ML2 AR1 Default: 0000h b14 ML1 AR0 b13 ML0 SL3 b12 VIB SL2 B11 EGT SL1 b10 SUS SL0 B9 RR3 TL5 b8 RR2 TL4 b7 RR1 TL3 b6 RR0 TL2 b5 DR3 TL1 b4 DR2 TL0 b3 DR1 WAV b2 DR0 FL2 b1 AR3 FL1 b0 AR2 FL0 ML2 - ML0 : Multiple setting "Multiple" is the multiplying factor for sound generating frequency. The output frequency is determined by the octave, pitch, and multiple settings on the carrier side. Adjusting the Multiple on the Modulator side allows various timbre creation. ML [2:0] 0h 1h 2h 3h 4h 5h 6h 7h Multiplying factor for frequency X 1/2 X1 X2 X3 X4 X5 X6 X7 -14- YMF795 VIB : Vibrato This bit is used to set ON/OFF of vibrato function. "0" for OFF, "1" for ON. The vibrato frequency is 6.4 Hz and the modulation depth is 13.47cent. EGT : Envelope waveform type This bit is used to select the type of the envelope waveform. "0" for the decaying sound and "1" for the sustained sound. Envelope waveforms shown below are for the decaying sound and sustained sound. EGT=0 Decaying sound DR AR RR SL When SUS=ON 0dB -48dB Length of Sound generated EGT=1 Sustained sound DR AR SL RR -48dB When SUS=ON 0dB Length of Sound generated AR3 - AR0 : Attack Rate setting "Attack Rate" is a time interval from the time sound starts generating (-48dB) to the time sound reaches at the maximum volume (0dB). The table on the next page is shown as the time taken from -48dB to 0dB. DR3 - DR0 : Decay Rate setting "Decay Rate" is a time interval taken for decay from 0 dB to the time it reaches at the Sustain Level (SL). The table on the next page is shown as the time taken from 0 dB to -48 dB. RR3 - RR0 : Release Rate setting Definition of the Release Rate differs between decaying sound and sustained sound. * Decaying sound: Decaying time from the Sustain Level to the end of the sound generation. The sound decays taking 286 ms (time taken from 0 dB to -48 dB) after the end of the sound generation. * Sustained sound: Decaying time from the end of the sound generation. -15- YMF795 SL3 - SL0 : Sustain level setting The Sustain Level, in the case of decaying sound, is the transition level from the Decay Rate to the Release Rate, and in the case of sustained sound, is a level held. SL Weighted bit (dB) AR[3:0] DR[3:0] RR[3:0] Fh Eh Dh Ch Bh Ah 9h 8h 7h 6h 5h 4h 3h 2h 1h 0h SL3 -24 SL2 -12 SL1 -6 SL0 -3 Attack rate -48 to 0dB (ms) 0 4.65 9.30 18.59 37.19 74.38 148.76 297.51 595.03 1190.05 2380.10 4760.21 9520.42 19040.84 Decay Rate, Release Rate 0 to -48dB (ms) 2.23 8.94 17.88 35.76 71.52 143.04 286.07 572.14 1144.25 2288.56 4577.12 9154.25 18308.50 36617.00 TL5 - TL0 : Total level setting This function is used to set the envelope level. TL Weighted bit (dB) TL5 -24 TL4 -12 TL3 -6 TL2 -3 TL1 -1.5 TL0 -0.75 SUS : Sustain On/OFF setting "0" : OFF "1" : ON The Release Rate changes to "6" (2.29s) when the sound length comes to the end. WAV : Waveform selection The modulator and carrier can generate a sine wave; however, can generate a half-wave rectified waveform by setting this bit. Setting this bit allows creation using wider timbres. "0" : Sine wave "1" : Half-wave rectified waveform of a sine wave. WAV=0 WAV=1 FL2 - FL0 : Feed-back setting This function is available only for the operator of Modulator. These bits specify the feedback modulation depth. Be sure to set "0" to the operator of the carrier side. This is effective function for generating the strings timbres. FL [2:0] Modulation rate 0 0 1 /16 2 / 8 3 / 4 4 / 2 5 6 2 7 4 -16- YMF795 Other control data $30h Timbre allocation data One piece can be generated at the same time up to four parts, and timbre can be assigned for each part. The data is used by allocating four timbres out of eight timbres registered in the timbre data register to each part. Default: 0000h Index $30h b15 0 b14 V32 b13 V31 b12 V30 b11 0 b10 V22 b9 V21 b8 V20 b7 0 b6 b5 b4 b3 0 b2 b1 b0 V12 V11 V10 V02 V01 V00 "x" of Vx[2:0] indicates the part No. Vx[2:0] and timbre data are as follows. Vx[2:0] 0h 1h 2h 3h 4h 5h 6h 7h Timbre data to use Timbre set in the Index of 10 to 13h is used. Timbre set in the Index of 14 to 17h is used. Timbre set in the Index of 18 to 1Bh is used. Timbre set in the Index of 1C to 1Fh is used. Timbre set in the Index of 20 to 23h is used. Timbre set in the Index of 24 to 27h is used. Timbre set in the Index of 28 to 2Bh is used. Timbre set in the Index of 2C to 2Fh is used. $31h Tempo data This register sets "tempo" for reproduction of a piece. Setting data is equal to (8739/TEMPO)-1. TEMPO is the number of crotchets that can be reproduced in one minute. Default: 0000h Index $31h b15 0 b14 0 b13 0 b12 0 b11 0 b10 0 b9 0 b8 0 b7 T7 b6 T6 b5 T5 b4 T4 b3 T3 b2 T2 b1 T1 b0 T0 $32h FM section control Default: 0000h Index $32h b15 0 b14 0 b13 0 b12 0 b11 0 b10 0 b9 0 b8 0 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 CLR b0 ST ST : This bit is used to control start/stop of a piece. "1" for start and "0" for stop. FIFO becomes empty when ST is set to "0." CLR : This bit is used to initialize the whole LSI by the software. All the registers except " Timbre data register" of Index 10 to 2Fh are initialized. Bit CLR itself is not cleared even if setting to "1." In normal operation, write "0" into the bit CLR.. -17- YMF795 $33h Clock selection Default: 0000h Index $33h b15 0 b14 0 b13 0 b12 0 b11 0 b10 0 b9 0 b8 0 b7 0 b6 0 b5 0 b4 0 b3 0 b2 b1 CLKSEL b0 This register is used to set the clock frequency inputted through CLK_I pin when making the clock setting in the preset mode. A clock with any frequency can be input during the reset period. (For details of the clock setting, see "On clock frequency setting" (page 24)). CKSEL [2:0] 0h(*) 1h 2h 3h 4h 5h 6h 7h Clock frequency (MHz) 2.688 19.200 19.680 19.800 8.400 14.400 27.821 12.600 (*)When clock is set in the programmable mode, set CLKSEL[2:0] to "0h". $34h Interrupt control Default: 0000h Index $34h b15 0 b14 0 b13 0 b12 0 b11 0 b10 0 b9 0 b8 0 b7 0 b6 0 b5 IRQE b4 b3 IRQ b2 point b1 b0 The musical score data is taken into the FIFO which has a capacity for 32 data. As the sounds are reproduced, the data in FIFO are processed and deleted. And when the amount of data remaining in FIFO becomes less than the setting value of IRQ point, an interrupt signal is generated. At this point, set "0" to IRQE and then write the subsequent musical score data into FIFO. Be sure to write data in excess of the IRQ point. After writing the data, reset IRQE to "1" and wait another interrupt signal. IRQ point can be set in 32 ways from 0 (empty) to 31 (1 data vacancy). IRQE is the interrupt enable bit. "1" indicates Enable. -18- YMF795 $35h $36h $37h Speaker volume control FM volume control Earphone output volume control Default: 0000h Index $35-7h b15 0 b14 0 b13 0 b12 0 b11 0 b10 0 b9 0 b8 0 b7 0 b6 0 b5 0 b4 V4 b3 V3 b2 V2 b1 V1 b0 V0 These bits are used to set the volume of each source. The volume setting consists of 31 steps and MUTE state, and can be set in 1dB steps. As the MUTE is selected in the default state, cancel and use the MUTE state before sound generation. And, be sure to power down the volume after muting it. Relation between register setting value and volume. V[4:0] 00h 01h 02h 03h 04h 05h 06h 07h Volume(dB) MUTE -30 -29 -28 -27 -26 -25 -24 V[4:0] 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Volume(dB) -23 -22 -21 -20 -19 -18 -17 -16 V[4:0] 10h 11h 12h 13h 14h 15h 16h 17h Volume(dB) -15 -14 -13 -12 -11 -10 -9 -8 V[4:0] 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Volume(dB) -7 -6 -5 -4 -3 -2 -1 0 $38h Power Management control Default: 001Eh Index $38h b15 0 b14 0 b13 0 b12 0 b11 0 B10 0 b9 0 b8 0 b7 0 b6 0 b5 0 b4 AP4 b3 AP3 b2 AP2 b1 AP1 b0 DP These bits are used to control the power-down. 1 digital line and 4 analog lines can be independently controlled. (For details, refer to "Power-down control division diagram".) Setting all bits to "1" will minimize the power of the entire LSI. DP : Setting of "1" can power down the entire digital section. AP1 : Setting of "1" can power down the VREF circuit in the analog section. AP2 : Setting of "1" can power down the FM volume, speaker volume, equalizer circuit, and the non-inverted amplifier side of speaker output section. AP3 : Setting of "1" can power down the inverted amplifier side of the speaker output section. AP4 : Setting of "1" can power down the DAC and earphone output volume. After initialization, the analog section (AP1 to AP4) is in the power-down state. -19- YMF795 $39h Clock setting Default: 0000h Index $39h b15 0 b14 0 b13 0 b12 0 b11 0 b10 0 b9 0 b8 b7 b6 b5 b4 CLKSET b3 b2 b1 b0 The register is used to set the clock frequency that is input through the CLK_I pin when the setting is made in the programmable mode. Be sure to complete the setting before its sound generation. A clock with any frequency can be input during the reset period. For details of the clock setting, see "Clock Frequency Setting" (page 24). CLKSET [8:0] 000000000b 000000001b : 000101111b 000110000b 000110001b : 111110001b 111110010b 111110011b : 111111111b Clock frequency(MHz) (Preset mode) Prohibition : Prohibition 2.684658000 2.740588375 : 27.797396375 27.853326750 Prohibition : Prohibition The values that can be set to CLKSET are "000000000b", and "000110000b" to "111110010b." When other value is set, the operation is not guaranteed. A value to set to CLKSET can be found by using the following formula. CLKSET = Clock frequency [KHz] / 447.443 x 8 For example, when the clock frequency is 3 MHz: CLKSET = 3000 / 447.443 x 8 is about 54 = 000110110b And, actual clock frequency to be set is as follows. Clock frequency [kHz] = 54 x 447.443 / 8 = 3020.24[kHz] = 3.02024[MHz] -20- YMF795 Power-down control division diagram Power-down of the LSI can be controlled for each divided internal function. The power-down is controlled by Index 38h. Controlled by using DP bit HPOUT Controlled by using AP4 bit Controlled by using AP2 bit AVDD DVDD CLK_I DVSS Timing Generator Power down Control VOL 32-step SCLK SYNC SDIN Register RAM FM Synthesizer Simultaneous Sound Generation 4-tone DAC VOL 32-step AVSS EQ1 EQ2 EQ3 SPOUT1 SPOUT2 Serial I/F FIFO 16b x 32w EQ VOL 32-step /IRQ VREF AMP /RST VREF SPVSS Controlled by using AP1 bit Controlled by using AP3 bit Explanation of each bit DP0 This is the bit to power off the whole digital section. Consumption current of the digital part can be minimized because internal clock stops. Contents of the registers are held but data in the FIFO are cleared. AP1 This is the bit to power off the VREF circuit. If AP1 is set to "1", the whole analog section stops. Because an analog center voltage is made by VREF circuit. AP2 This is the bit to power off the FM volume section, EQ circuit, speaker volume, and non-inverted amplifier side of speaker output section. -21- YMF795 AP3 This is the bit to power off the inverted amplifier side of the speaker output section. Turning the inverted amplifier side power on after turning the VREF circuit and a non-inverted amplifier power on can reduce pop noise. AP4 This is the bit to power off the DAC and the HP Volume section. Cautions for transition to the power-down 1. Be sure to shift a state to the power-down after the sound generation stops. 2. Power-down of the digital and analog section can be made at the same time. Be sure to mute FM Volume and HP Volume in advance for the reduction of noise during power-down transition. The registers to which the digital section cannot access during the power-down are as follows. Index $00h $10-2Fh $30h $31h $34h Register functions Musical score data Timbre data Timbre allocation Tempo data IRQ Control Cautions for cancellation of the power-down 1. The time of 64xCLK_I is necessary from the setting of DP=0 until the digital section returns to the normal operation. Be sure to access the registers after waiting for the time. 2. Perform the return procedure in this order when the whole analog section was powered off or the analog power supply is OFF. * Set AP1 to "0." VREF goes up at the maximum of 50ms. Do not set AP2 to AP4 to "0" until VREF goes up. * Set AP2 to "0." * Set AP3 and AP4 to "0" after at least 10s. * Here, analog section is made available. Consumption current can be reduced more, by setting AP4 to "1" when only speaker amplifier section is used, and by setting AP2 and AP3 to "1" when only headphone is used without speaker amplifier. Analog power supply OFF mode Analog power supply can be powered off only when sound generation is being stopped. Be sure to set AP1 to AP4 to "1" before powering off the analog power supply. Or, pop noise may occur. -22- YMF795 Example of the setting in each case. Depending on how the function is used, bit settings can be combined as shown below. Analog section whole power-down Use of only earphone output. Use of only speaker. AP1 1 0 0 AP2 1 1 0 AP3 1 1 0 AP4 1 0 1 Caution Be sure to set all volumes to "MUTE" first, then set all bits to "1" simultaneously. Set the FM and speaker volumes to "MUTE." Set the HP and FM volumes to "MUTE." -23- YMF795 On Reset This LSI can be initialized by setting /RST pin to "L." And, CLR bit is provided in $32h to allow the software to initialize the LSI. Hardware reset initializes the LSI and returns it to the default condition. All the registers except the timbre data register of Index 10h to 2Fh are initialized by the software reset. A counter for the amount of FIFO data is cleared to "Empty" state. Input of CLK_I is required during reset. Be sure to control so that CLK_I is input at least more than 100 clocks during the reset. After the reset cancellation, access a register after waiting at least 64 clocks of CLK_I. Settings and Procedure required for a piece generation Necessary settings and procedure are as follows. 1. Set the CLKSEL ($33h) or CLKSEL ($39h) according to the clock frequency inputted for CLK_I. 2. Cancel the power-down mode of the analog section. (See "Cautions for cancellation of the power-down" (page22). 3. Set the timbre data ($10-2Fh), timbre allocation data ($30h), tempo data ($31h) and volumes ($35-37h) as required. 4. Write musical score data ($00h) for 32 data (that is, to FIFO_FULL). 5. Set the IRQ point value of $34h. 6. Set the IRQE of $34h to "1." 7. Set the ST bit of $32h to "1" to start the melody. Clock Frequency Setting Two modes for clock frequency setting are supported: "Preset mode" and "Programmable Mode." Preset mode: a clock is selected from 2.688 / 8.4 / 12.6 / 14.4 /19.2 / 19.68 / 19.8 / 27.82 MHz. Programmable mode: a clock is selected from 2.685 MHz to 27.853 MHz in 55.93 kHz steps. 1) When the preset mode is used: Clock frequency setting can be made in the preset mode by setting a value to $33h. In this case, set $39h to "000000000b." Operation is not guaranteed if other value is set. When a value is not set to both $33h and $39h (default condition), a condition that 2.688 MHz is set in the preset mode is given. 2) When the programmable mode is used: Clock frequency setting can be made in the programmable mode by setting a value to $39h. In this case, set $33h to "000b." Operation is not guaranteed if other value is set. A value that can be set to $39h is "000000000b" and "000110000b" to "111110010b." Operation is not guaranteed if other value is set. -24- YMF795 On Interrupt Sequence An interrupt from LSI (/IRQ-"L") occurs when the amount of data in the FIFO becomes less than the setting value. For example, supposing that 10h (16b) is set to the IRQ point of $34h, the FIFO becomes full before starting a piece as described in "Settings and procedure required for a piece generation." Once a piece is started, the data in the FIFO decreases as the musical score data is processed. When the amount of remaining data becomes 16 bytes or less, /IRQ pin becomes "L" and occurrence of an interrupt is sent to the external microprocessor. When an interrupt signal is detected, set IRQE to "0" and write the musical score data into the FIFO before it becomes empty. As overwriting the data into the filled FIFO is prohibited, write the data into FIFO by the amount not causing the overwriting (16 data in this case). Flow chart Set each register according to the explanation of "Settings and procedure required for a piece generation." Start the playback. As a piece is played back, the musical score data are processed in the LSI. The remaining data in FIFO is lower than IRQ point set in the $34h ? No Yes Set the IRQ enable bit (IRQE) to "0" and write data into the FIFO. Cautions for the write operation is the following two points: Be sure to write data before FIFO becomes empty. Overwriting the data into the filled FIFO is prohibited. Do you want to stop the piece? No Yes Stop the piece. (ST=0) -25- YMF795 State Transition The figure shown below is a state transition diagram of the YMF795. Digital PowerON Ready Analog PowerON Ready Power On Hardware Reset Power On Power Off Initialized Write Setup Data Analog PowerDown mode STOP FIFO Data Write STOP Digital PowerDown mode PLAY Standby START Play Sequence to turn the power supply on. A way to turn the analog side power on after turning the digital side power on to initialize the hardware is ideal. If the analog power supply is turned on before the hardware is initialized, noise may be generated. -26- YMF795 Description of each state Digital Power ON Ready This is a state before turning on the digital power supply. Hardware Reset Input the hardware reset to the LSI in conjunction with the power-on of the digital power supply. Analog Power ON Ready This is a state before turning on the analog power supply. Turn on the analog power supply after the initialization of the digital section. Analog Power Down mode This is a state in which power consumption of the analog section is the minimum. Operation state is shifted to this operation mode after the analog power supply is turned on. In order to proceed to the next step "Initialized" state, follow the procedure described on page 22. Be sure to shift from the "Initialized" state in order to shift to this operation mode from a state except Analog Power ON. (That is, each volume must be set to "MUITE.") A point to power down can be selected according to the usage. For details, refer to the description of Power-down on pages of 21, 22, and 23. Be sure to power off the analog power supply from this state. Initialized This state is given after the Power Down mode of the analog and the digital section. And, shift to the power-down mode from this state. STOP This is a state in which volume mute cancellation and the timbre data setting has been completed. In this state, the FIFO is empty. This state returns when the melody reproduction is stopped. And, transition to the power-down of the digital section is possible from this state. This state will return when the power-down is cancelled. PLAY Standby This is a state that is given immediately before the playback of a piece after the write of musical score data into FIFO. Setting bit ST to "1" will shift to the next "PLAY" state. Transition to the power-down of the digital section is possible from this state. However, the state will return to "STOP" state after the power-down cancellation. PLAY This is a state in which a piece is being played back. Setting bit ST to "0" will shift to the "STOP" state. Transition to the power-down of the digital section from this state is prohibited. (Noise may be generated.) Digital Power Down mode This is a state in which the digital section is in the power-down state. (DP bit = "1") This state can reduce the power consumption of the digital section because a clock is not input to the LSI even if it is input to CLK_I pin. Make the HP Volume and FM Volume mute state before shifting to this mode. -27- YMF795 Operation in FIFO empty condition If FIFO become empty during reproduction the musical score data written last is processed continuously until the next data is written. If the last data written is a note data, that note is reproduced continuously. If the last data written is a rest data, the rest state is held. Reproduction method assuming occurrence of empty state In the normal reproduction, occurrence of FIFO Empty is prohibited; however, even simple processing can generate a short tone if the above features are effectively used. Processing for interrupt is not required. Make the processing according to the following flow. Short tone is 1 to 32 word data block. If data block exceeds 33 words, make the processing by the usual reproduction flow using interrupt. 1) Complete the following procedure in advance: Power ON Analog Power Down mode Initialized STOP (See the figure of "State Transition" (page 26). 2) Start the reproduction in the FIFO Empty state. 3) Write the data block to be reproduced into FIFO. 4) Immediately after writing (after 0 to 20s), the musical score data are internally processed and its reproduction starts. As reproduction goes on, the data in FIFO are processed and cleared. 5) When FIFO becomes empty, if the last data in the data block is a note data, that note is reproduced continuously and if it is a rest data, the rest state is held until the next data block is written into FIFO. 6) When reproducing the next data block, go to step 3). To stop the reproduction set ST to "0." Then, the data counter of FIFO will be cleared and the state returns to a state of step 1). -28- YMF795 Example of peripheral circuit Amp. Headphone HPOUT EQ1 C1 R1 SCLK SYNC SDIN SCLK SYNC SDIN EQ3 EQ2 R2 AIN C2 YMF795 RESET# IRQ# /RST /IRQ SPOUT1 Speaker SPOUT2 AVDD AVSS VREF SPVSS CLK 0.1uF 4.7uF CLK_I DVSS DVDD +3.3V +3.3V 4.7uF 0.1uF 0.1uF On /RST pin A schmitt circuit is not used for /RST pin in this device; therefore, please design a board in consideration of noise to the /RST line. -29- YMF795 Precautions for the use of separate power supplies: A LSI with multiple power supply inputs needs to pay attention to the followings for [Power supply connection] and [Ground connection]. We explain it here by giving an analog circuit power supply and a digital circuit power supply as an example. [Power supply connection] When a power supply for analog circuits of this LSI and a power supply for digital circuits of this LSI can be separately prepared (including a case where a power supply for the LSI's analog circuits is shared with analog circuits of the later stage) please refer to "(1) Circuit diagram and wiring diagram when two power supplies are used:" On the contrary, when multiple power supplies cannot be prepared, please refer to "(2) Circuit diagram and wiring diagram when one power supply and one voltage regulator IC are used:" And, when "(1) Circuit diagram and wiring diagram when two power supplies are used:" is selected, room for improvement of analog performance becomes big, but you need to consider avoidance of time interval difference between power supplies at the time of power-on (power-off). [Ground connection] The ground connection is common to "(1) Circuit diagram and wiring diagram when two power supplies are used:" and "(2) Circuit diagram and wiring diagram when one power supply and one voltage regulator IC are used:" In each case, grounds must not be separated. (1) Circuit diagram and wiring diagram when two power supplies are used: Be sure to connect VSS pin to AVSS pin near the LSI. Excessive inductance between VSS pin and AVSS pin may cause malfunctions and failures. -30- YMF795 (2) Circuit diagram and wiring diagram when one power supply and one voltage regulator IC are used: Be sure to connect VSS pin to AVSS pin near the LSI. Excessive inductance between VSS pin and AVSS pin may cause malfunctions and failures. Connect the ground pin of the voltage regulator IC used for analog circuits near AVSS pin to prevent influence of digital circuit's current change. The later analog circuits shall consider the AVSS pin as a reference potential. -31- YMF795 Warning for the device which makes sound through speaker A speaker radiates heat in a voice-coil by air flow accompanying vibration of a diaphragm. When DC signal (several Hz or less) is input, heat radiation characteristics falls rapidly. In addition, even if it is used lower than the rated input, it may lead to voice-coil burnout, smoke, or ignition of a speaker. In order to avoid such situations, be sure to implement one or more preventive measures from the followings. 1. Don't select settings (sound creation) which may generate DC signal. (Since thoroughness of this preventive measure is generally difficult, we recommend the combined use with the following 2, 3, and 4) 2. Add the equivalent of DC cut digital filter for cutting DC signal into a digital section. (As long as "Built-in" is not mentioned in the manual, there is no such built-in circuit inside of a device). 3. Add a DC cut capacitor for cutting DC signal into an analog section. (When addition is specified in the example of a recommended circuit diagram, be sure to add) 4. When a latter stage device exists in the signal path from this device to speaker, be sure to realize the DC cut is realized in a latter stage device. In addition, the above-mentioned measures are based on the assumption that the device itself, DC cut capacitor, and a latter stage device will be in a normal operation. Therefore, it is also necessary to implement measures based on the assumption of these part failures. Warning for short circuit at speaker pins Overcurrent breakdown, extraordinary heat, or package melting is caused if a short circuit is made between two outputs, between output and power supply, and between output and Ground, because of high drive performance of the speaker amplifier output. In order to avoid such situations, be sure to implement one or more preventive measures from the followings. 1. Adoption of a power supply with overcurrent protection circuit for the speaker amplifier. 2. Provision of an overcurrent protection circuit in the speaker amplifier circuit. (This device does not have the circuit) 3. Provision of a thermal shutdown circuit in the speaker amplifier section. (This device does not have the circuit) In addition, the above-mentioned measures are based on the assumption that overcurrent circuit or thermal shutdown circuit will work normally. Therefore, it is also necessary to take measures based on the assumption of these part failures. Moreover, consider the followings as well. - Design the board so that speaker amplifier output is not short-circuited easily even if foreign body or solder bridge is present. - Warning to customers of risk that may be caused by a short circuit of the speaker amplifier output. -32- YMF795 Volume level Adjustment in monophonic sound and 4-sound generation The volume level outputted from DAC varies depending on the number of the pronunciation. When one tone (*) is output from the FM sound source, output voltage amplitude from DAC becomes 0.4125 Vp-p. When multiple sounds are pronounced at the same time, output voltage amplitude varies depending on phase of each waveform, but when the waveforms with the same phase are overlapped, it becomes 0.825 Vp-p in 2-tone, 1.2375 Vp-p in 3-tone, and 1.65 Vp-p in 4-tone. (*: This explanation is made on the assumption that volume adjustment (Total Level of Carrier) of one tone is 0 dB.) HP VOL HPOUT EQ1 R1 FM sound source DAC FM VOL VREF EQ2 +- R2 EQ3 SP VOL BTL Driver +11.6dB SPOUT1 SPOUT2 RL=8 An assumption of 300 mW output. Output power of 300 mW can be obtained from the speaker when RL is 8 and a voltage between SPOUT1 and 2 is 1.55 Vrms. At this time, BTL output amplitude becomes 1.55x2x1.414=4.38 Vp-p, and EQ3 pin is 4.38/3.8=1.15 Vp-p. (Gain with the speaker amplifier is +11.6 dB= 3.8 times.) Assurance of volume level in monophonic sound. "Gain adjustment in the EQ amplifier section" is recommended as a way to assure the volume level in monophonic sound. The Gain depends on the resistance ratio between R1 and R2, and Gain is equal to R2/R1. The Gain of 3 times to 4 times is recommended. -33- YMF795 Example of the recommended level adjustment in all the system Turn down either FM or SP volume a little as a default (-3 dB to -6 dB or so). This is made for previously assuring a volume of which Gain is increased, because either volume may be controlled by user EQ amplifier Gain of 3 times to 4 times or so is recommended to secure the output level to some extent in monophonic sound. (For example, R1=22 k, R2=82 k). When monophonic sound is generated in this condition (FM volume as 0dB), EQ1 is 0.4125 Vp-p, and if Gain of the EQ amplifier is four times, EQ3 becomes 1.65 Vp-p. When -4 dB is given by SPVOL, voltage between SPOUT1 and 2 becomes 3.96 Vp-p, and resultantly 245 mW output power can be obtained with the speaker (RL=8). A level adjustment of 4-sound simultaneous generation When normal music is played back, the amplitude of DAC seldom swings to 1.65 Vp-p. Therefore, the same Gain settings as that of monophonic sound can be made but if distortion of its sound is a little significant, turn down the Gain of EQ amplifier or adjust the FM and/or SP volume. A level adjustment of HPOUT Adjust the GAIN outside the LSI to increase Gain of the HPOUT side. -34- YMF795 Sound Quality Correction Circuit Sound quality and Gain can be corrected by using an external circuit connected to EQ1 to 3 pins. The internal circuit configuration of EQ1 to 3 pin and example of the external circuit are as follows. C3 AIN C1 R1 R2 EQ1 FM VOL EQ2 EQ3 Rx C2 + VREF Gain and filter characteristic can be controlled by a value of C1, C2, R1, and R2. Gain = R2 / R1. The recommended values: R1 = 22 k and R2 = 82 k (Gain = 3.7 times). Filter cutoff frequency of f1 and f2 is: f1 = 1/ (2xR1xC1). f2 = 1/ (2xR2xC2). If C1 = 0.022 F and C2 = 120 pF, the cutoff frequency of f1 = 330 Hz and f2 = 16 kHz. Gain Gain1 Gain1 -3dB f1 f2 Freq Moreover, the circuit enclosed with the dotted line is required when mixing with analog signal from AIN is desired. The level adjustment for mixing depends on the resistance ratio R2/Rx of Rx and R2. The value of Rx should be 82 k when mixing of amplitude of one time is required. -35- YMF795 Using a resister R3 can obtain the following frequency characteristic. C2 C1 R1 R2 EQ2 EQ3 R3 EQ1 FM VOL + VREF Gain1= (R2+R3) /R1. Gain2=R3/R1. Filter cutoff frequency of f1 and f2 is: f1=1/ (2xR1xC1). f2=1/ (2xR2xC2). Gain Gain1 Gain1-3dB Gain2 f1 f2 Freq -36- YMF795 Serial I/F Specifications 8 clk 16 clk SCLK SYNC Type1 SYNC Type2 MSB LSB 10 MSB 15 Control Data (16bit) LSB 10 MSB 76 SDIN 76 Index Data (8bit) YMF795 is controlled by the three serial interface lines of SCLK, SYNC, and SDIN. Relation between SDIN and SCLK The LSI takes in the value of SDIN at the rising edge of SCLK. Input the SDIN so that Setup/Hold time is assured with respect to the rising edge of SCLK. (For details of timing specification, see "4. AC characteristics" in "Electric Characteristics") About SDIN The above figure has the period at which no data is transferred between Index data and Control data, but this period is not necessarily required. Data of 24-bit can be transferred in succession. When transfer in 8 bits is required, divide the Control data in two of high-order 8 bits and low-order 8 bits. The interval between the first high-order 8 bits and the next low-order 8 bits transfer is not especially defined. However, if excessive interval is given, time taken to complete one transfer becomes long. Pay attention so that FIFO does not become empty when writing the musical score data into the FIFO. About SYNC Both Type1 and Type2 in the above figure are available. The LSI considers the rising edge of SYNC as the completion of one data transfer.. The LSI sees SDIN for 24xSCLK before the rising edge of SYNC as valid data. (SDIN for 16xSCLK are valid data when only Control Data is transferred.) The length of the period of "H" is not especially defined, but for the waveform of Type 2, control so that the period of "L" is assured at least 100 ns. Malfunction may be caused when a rising edge of SYNC comes close to a rising edge of SCLK. Consider so that a rising edge of SCLK does not generate within 50ns with respect to a rising edge of SYNC. About the data transfer only Control Data. When the SDIN for SCLKx16 is input between a rising edge of SYNC and the next rising edge of SYNC, the LSI judges it as the musical score data ($00h) to take it in. Use this transfer when transferring musical score data fast. -37- YMF795 Electrical Characteristics 1. Absolute maximum ratings Parameter Supply voltage (analog) Supply voltage (digital) Symbol AVDD DVDD VINA VIND TSTG Min. -0.3 -0.3 -0.3 -0.3 -50 Max. 4.6 4.6 AVDD+0.3 DVDD+0.3 125 Unit V V V V C Analog input voltage Digital input voltage Storage temperature Note) DVSS = AVSS= SPVSS = 0V 2. Recommended operating conditions Parameter Operating voltage (analog) Operating voltage (digital) Symbol AVDD DVDD TOP Min. 3.0 3.0 -40 Typ. 3.3 3.3 25 Max. 3.6 3.6 85 Unit V V C Operating ambient temperature Note) DVSS = AVSS = SPVSS = 0V 3. DC characteristics Parameter High-level input voltage Low-level input voltage High-level output voltage Symbol VIH VIL VOH VOL Vsh IL CI DVDD=3.30.3V, Condition Min. 0.7 x DVDD - Typ. 1.0 Max. 0.2 x DVDD 0.4 10 10 Unit V V V V V A IOUT = -1mA 0.8 x DVDD IOUT = 1mA -10 Capacitor load=50pF Low-level output voltage Schmitt width Input leakage current Input capacity Note) TOP=-40 to 85C, pF -38- YMF795 4. AC characteristics Conditions: Input signal of VIH=0.8xDVDD, VIL=0.1xDVDD. Timing measurement at VIH=0.7xDVDD, VIL=0.2xDVDD. 4-1. CLK_I ,Reset Parameter CLK_I clock period CLK_I "L" pulse width CLK_I "H" pulse width /RST active "L" pulse width SCLK start delay time (after /RST inactive) Symbol Tcclk_period Tcclk_low Tcclk_high Trst_low Trst2clk Min. 35.8 12 12 100 64 Typ. Max. Unit ns ns ns x CLK_I x CLK_I Note) TOP=-40 to 85C, DVDD=3.30.3V, Capacitor load=50pF "x CLK_I" indicates the number of clocks inputted through the CLK_I pin. CLK_I Duty Hardware Reset -39- YMF795 4-2. Serial Interface Parameter SCLK clock period SCLK "L" pulse width SCLK "H" pulse width SCLK rise time SCLK fall time SYNC "H" pulse width SYNC rise time SYNC fall time SYNC delay time SYNC "L" pulse width SYNC SCLK setup time SDIN setup time SDIN hold time SDIN rise time SDIN fall time Symbol Tsclk_period Tsclk_low Tsclk_high Trise_sclk Tfall_sclk Tsync_high Trise_sync Tfall_sync Tdelay_SYNC SYNC_low Tsetup_SYNC Tsetup_SDIN Thold_SDIN Trise_din Tfall_din Min. 430 200 200 Typ. Max. Unit ns ns ns 20 20 100 20 20 0 100 50 50 50 20 20 ns ns ns ns ns ns ns ns ns ns ns ns Note) TOP=-40 to 85C, DVDD=3.30.3V, Capacitor load=50pF -40- YMF795 5. Power consumption Parameter Digital part in normal operation Analog part without sound generation Analog part at output 300mW, 8 load Min. Typ. 550 10 186 0.1 Max. 2200 13 1 Unit A mA mA A In power-down mode Note) TOP=-40 to 85C, DVDD= AVDD = 3.30.3V, Capacitor load=50pF 6. Analog characteristics SP Amplifier Parameter Min. Typ. 1.9 8 5.5 500 0.025 -90 Max. Unit times Vp-p mW % dBV Gain setting (fixed) Minimum resister load (RL) Maximum output voltage amplitude (RL=8) Maximum output power (RL=8, THD+N1.0%) THD + N (RL=8, f=1kHz, 300mW output) Noise level without signal (A-filter) Note) TOP=25C, DVDD = AVDD = 3.3V EQ Amplifier Parameter Min Typ 3.0 Max. 30 0.05 Unit dB Vp-p % dBV M k Gain setting range Maximum output voltage amplitude THD + N (f=1kHz) -90 10 20 Noise level without signal (A-filter) Input impedance Feedback resistance EQ2-EQ3 Note) TOP=25C, DVDD = AVDD = 3.3V SP Volume Parameter Min -30 Typ 1 Max 0 Unit dB dB dB Volume setting range Volume step width Decay rate in MUTE Note) TOP=25C, DVDD = AVDD = 3.3V 80 -41- YMF795 FM Volume Parameter Min -30 1 80 20 3.0 300 600 Typ Max 0 Unit dB dB dB k Vp-p Volume setting range Volume step width Decay rate in MUTE Minimum load resistance Maximum output voltage amplitude Output impedance Note) TOP=25C, DVDD = AVDD = 3.3V HP Volume Parameter Min -30 Typ 1 Max 0 Unit dB dB dB k Vp-p Volume setting range Volume step width Decay rate in MUTE Minimum load resistance Maximum output voltage amplitude Output impedance Note) TOP=25C, DVDD = AVDD = 3.3V VREF Parameter 80 20 3.0 300 600 Min Typ 0.5xAVDD Max Unit V VREF voltage Note) TOP=25C, DVDD = AVDD = 3.3V DAC Parameter Min Typ Max Unit Resolution Full-scale analog output (*1) THD+N (f= 1kHz) Noise level without signal (f=400Hz to 20kHz) Frequency characteristic (f=50Hz to 20kHz) Note) TOP=25C, DVDD = AVDD = 3.3V 12 1.65 0.5 -90 -3.0 (2*) +0.5 Bit Vp-p % dBV dB *1: When four FM tones are simultaneously generated in the same phase. *2: Degradation of high-frequency response due to aperture effect. -42- YMF795 General description of FM sound generator "FM" stands for Frequency Modulation. The FM sound generator utilizes the higher harmonic wave produced by the frequency modulation for synthesis of the musical sounds With the use of this FM system enables a comparatively simple circuit to produce such waveform that has a harmonic wave including disharmonious sounds, it is possible to create a wide range of sounds from the synthesized sounds of the natural musical instruments to the electronic sounds. The diagram below shows the most basic configuration of the FM system. Sin Wave Table Sin Wave Table f A m Phase Generator Envelope Generator I c c Phase Generator Envelope Generator Operator 1 : Modulator Operator 2 : Carrier The "Operator" refers to the section where a sine wave is generated and the combination of the operators is called "algorithm". The operator in the front stage is called "modulator" and that in the rear stage "carrier". Each operator is capable of setting the frequency and the envelope waveform. The configuration in the above diagram can be expressed in the formula as follows. FM(t) = A sin(ct + B sin mt ) A : Amplitude of the carrier. B : Amplitude of the modulator. m : Angle frequency of the modulator In addition, a system called "feedback FM" is available to create a wider range of sounds. In this system, the frequency modulation is fed back as shown in the diagram in the following page. B is called "feed-back ratio". Using the feed-back FM function, it is possible to produce the strings type sounds. c : Angle frequency of the carrier -43- YMF795 External dimensions -44- YMF795 |
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