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| Semiconductor HI5865 12-Bit, 65 MSPS A/D Converter Description The HI5865 is a monolithic, 12-bit, 65 MSPS Analog-toDigital Converter fabricated in an advanced CMOS process. It is designed for high speed, high resolution applications where wide bandwidth, low power consumption and excellent SINAD performance are essential. With a 250MHz full power input bandwidth and high frequency accuracy, the converter is ideal for many types of communication systems employing digital IF architectures. The HI5865 is designed with a fully differential pipelined architecture using a front end differential-in-differential-out Sample-and-Hold amplifier (S/H). The HI5865 has excellent dynamic performance while consuming 450mW of power at 65 MSPS. Data output latches are provided which present valid data to the output bus with a low data latency of 9 clock cycles. PRELIMINARY June 1998 Features * Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . 65 MSPS * Low Power at 65 MSPS . . . . . . . . . . . . . . . . . . . .450mW * Internal Sample and Hold * Fully Differential Architecture * Full Power Input Bandwidth . . . . . . . . . . . . . . . 250MHz * Low Data Latency * TTL Compatible Clock Input * CMOS Compatible Digital Data Outputs Applications * Multichannel Digital Communication Receivers * Cellular/PCS Basestation Receivers * Undersampling Digital IF * Digital Subscriber Line (VDSL) * Medical Ultrasound * Reference Literature - AN9214, Using Harris High Speed A/D Converters Ordering Information PART NUMBER HI5865IN HI5865EVAL1 TEMP. RANGE (oC) -40 to 85 25 PACKAGE 44 Ld MQFP PKG. NO. Q44.10x10 Evaluation Platform Pinout HI5865 (MQFP) TOP VIEW DGND3 DGND DGND DGND DGND DGND DVCC3 DVCC CLK D11 NC DVCC DGND AGND AVCC AGND AVCC AVCC1 AGND1 VINVIN+ VDC 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 31 30 29 28 27 26 25 24 D10 D9 D8 D7 DGND DVCC D6 D5 D4 D3 D2 10 11 23 12 13 14 15 16 17 18 19 20 21 22 DGND1 DGND2 VREF+ VREF- DVCC1 DVCC2 D0 NC NC D1 NC CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1998 File Number 4538 1 HI5865 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) D D1 -D- Q44.10x10 (JEDEC MO-108AA-2 ISSUE A) 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL A A1 A2 INCHES MIN 0.004 0.077 0.012 0.012 0.510 0.390 0.510 0.390 0.026 44 0.032 BSC MAX 0.093 0.010 0.083 0.018 0.016 0.530 0.398 0.530 0.398 0.037 MILLIMETERS MIN 0.10 1.95 0.30 0.30 12.95 9.90 12.95 9.90 0.65 44 0.80 BSC MAX 2.35 0.25 2.10 0.45 0.40 13.45 10.10 13.45 10.10 0.95 NOTES 6 3 4, 5 3 4, 5 7 Rev. 1 1/94 NOTES: 0.10 0.004 -AE E1 -B- B B1 D D1 E e PIN 1 SEATING A PLANE E1 L N e -H- 5o-16o 0.40 0.016 MIN 0o MIN 0o-7o A2 A1 0.20 M C A-B S 0.008 -CDS B B1 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. "N" is the number of terminal positions. L 5o-16o 0.13/0.23 0.005/0.009 2 |
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