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SY58606U
4.25Gbps Precision, 1:2 CML Fanout Buffer with Internal Termination and Fail Safe Input
General Description
The SY58606U is a 2.5/3.3V, high-speed, fully differential 1:2 CML fanout buffer optimized to provide two identical output copies with less than 15ps of skew and less than 10pspp total jitter. The SY58606U can process clock signals as fast as 3GHz or data patterns up to 4.25Gbps. The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals, (AC- or DC-coupled) as small as 100mV (200mVpp) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an integrated voltage reference (VREF-AC) is provided to bias the VT pin. The outputs are 400mV CML, with extremely fast rise/fall times guaranteed to be less than 85ps. The SY58606U operates from a 2.5V 5% supply or 3.3V 10% supply and is guaranteed over the full industrial temperature range (-40C to +85C). For applications that require LVPECL or LVDS outputs, consider Micrel's SY58607U and SY58608U, 1:2 fanout buffers with 800mV and 325mV output swings respectively. The SY58606U is part of Micrel's highspeed, Precision Edge(R) product line. Data sheets and support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge(R)
Features
* Precision 1:2, 400mV CML fanout buffer * Guaranteed AC performance over temperature and voltage: - DC-to > 4.25Gbps throughput - <320ps propagation delay (IN-to-Q) - <15ps within-device skew - <85ps rise/fall times * Fail Safe Input - Prevents outputs from oscillating when input is invalid * Ultra-low jitter design - <1psRMS cycle-to-cycle jitter - <10psPP total jitter - <1psRMS random jitter - <10psPP deterministic jitter * High-speed CML outputs * 2.5V 5% or 3.3V 10% power supply operation * Industrial temperature range: -40C to +85C * Available in 16-pin (3mm x 3mm) MLF(R) package
Applications Functional Block Diagram
* * * * Data Distribution: OC-48, OC-48+FEC, XAUI SONET clock and data distribution Fibre Channel clock and data distribution Gigabit Ethernet clock and data distribution
Markets
* * * * * * * Storage ATE Test and measurement Enterprise networking equipment High-end servers Access Metro area network equipment
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
September 2006
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SY58606U
Ordering Information(1)
Part Number SY58606UMG SY58606UMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
Package Type MLF-16 MLF-16
Operating Range Industrial Industrial
Package Marking 606U with Pb-Free bar-line indicator 606U with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
16-Pin MLF(R) (MLF-16)
Pin Description
Pin Number 1, 4 Pin Name IN, /IN Pin Function Differential Input: This input pair is the differential signal input to the device. Input accepts DC-coupled differential signals as small as 100mV (200mVPP). Each pin of this pair internally terminates with 50 to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See "Input Interface Applications" subsection. Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" subsection. Reference Voltage: This output biases to VCC-1.2V. It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR capacitor to VCC. Maximum sink/source current is 1.5mA. See "Input Interface Applications" subsection. Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCC pins as possible. Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pins. CML Differential Output Pairs: Differential buffered copies of the input signal. The output swing is typically 400mV. Unused output pair may be left floating with no impact on jitter. See "CML Output Termination" subsection.
2
VT
3
VREF-AC
5, 8,13, 16 6, 7, 14, 15 9, 10 11, 12
VCC GND, Exposed pad /Q1, Q1 /Q0, Q0
September 2006
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SY58606U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................... -0.5V to +4.0V Input Voltage (VIN) .......................................-0.5V to VCC CML Output Voltage (VOUT) .......... VCC-1.0V to VCC+0.5V Current (VT) Source or sink on VT pin .............................100mA Input Current Source or sink Current on (IN, /IN) ................50mA Current (VREF) Source or sink current on VREF-AC(4) ..............1.5mA Maximum operating Junction Temperature .......... 125C Lead Temperature (soldering, 20sec.) .................. 260C Storage Temperature (Ts) ....................-65C to +150C
Operating Ratings(2)
Supply Voltage (VIN)........................ +2.375V to +3.60V Ambient Temperature (TA) ................... -40C to +85C Package Thermal Resistance(3) MLF(R) Still-air (JA) ............................................ 60C/W Junction-to-board (JB) ......................... 33C/W
DC Electrical Characteristics(5)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RDIFF_IN VIH VIL VIN VDIFF_IN VIN_FSI VREF-AC VT_IN
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB and JA values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. Due to the limited drive capability, use for input of the same package only. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN(max) is specified when VT is floating.
Parameter Power Supply Voltage Range Power Supply Current Differential Input Resistance (IN-to-/IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing (|IN - /IN|) Input Voltage Threshold that Triggers FSI Output Reference Voltage Voltage from Input to VT
Condition
Min 2.375 3.0
Typ 2.5 3.3 60
Max 2.625 3.6 77 110 VCC VIH-0.1 1.7
Units V mA V V V V
No load, max. VCC 90 IN, /IN IN, /IN see Figure 3a, Note 6 see Figure 3b 1.2 0 0.1 0.2
100
30 VCC-1.3 VCC-1.2
100 VCC-1.1 1.28
mV V V
September 2006
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Micrel, Inc.
SY58606U
CML Outputs DC Electrical Characteristics(7)
VCC = +2.5V 5% or +3.3V 10%, RL = 100 across the outputs; TA = -40C to +85C, unless otherwise stated.
Symbol VOH VOUT VDIFF_OUT ROUT
Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Output HIGH Voltage Output Voltage Swing Differential Output Voltage Swing Output Source Impedance
Condition RL = 50 to VCC See Figure 3a See Figure 3b
Min VCC-0.020 325 650 45
Typ VCC-0.010 400 800 50
Max VCC
Units V mV mV
55
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Micrel, Inc.
SY58606U
AC Electrical Characteristics
VCC = +2.5V 5% or +3.3V 10%, RL = 100 across the outputs, Input tr/tf: <300ps; TA = -40C to +85C, unless otherwise stated.
Symbol fMAX tPD tSkew tJitter Parameter Maximum Frequency Propagation Delay Within Device Skew Part-to-Part Skew Data Clock tR tF Random Jitter Deterministic Jitter Cycle-to-Cycle Jitter Total Jitter Output Rise/Fall Times (20% to 80%) Duty Cycle
Notes: 8. 9. Within device skew is measured between two different outputs under identical input transitions. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
23
Condition NRZ Data VOUT > 200mV IN-to-Q VIN: 100mV-200mV VIN: 200mV-800mV Note 8 Note 9 Note 10 Note 11 Note 12 Note 13 At full output swing. Differential I/O Clock
Min 4.25 2.5 150 120
Typ 3.0 270 220 3
Max
Units Gbps GHz
400 320 15 100 1 10 1 10
ps ps ps ps psRMS psPP psRMS psPP ps %
30 47
50
85 53
10. Random jitter is measured with a K28.7 pattern, measured at fMAX. 11. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 -1 PRBS pattern. 12. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn -Tn+1, where T is the time between rising edges of the output signal. 13. Total jitter definition: with an ideal clock input frequency of fMAX (device), no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value.
12
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SY58606U
Functional Description
Fail-Safe Input (FSI) The input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mVPK (200mVPP), typically 30mVPK. Maximum frequency of SY58606U is limited by the FSI function.
Input Clock Failure Case If the input clock fails to a floating, static, or extremely low signal swing, then the FSI function will eliminate a metastable condition and guarantee a stable output. No ringing and no undetermined state will occur at the output under these conditions. Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to "Typical Characteristics" for detailed information.
Timing Diagrams
Figure 1a. Propagation Delay
Figure 1b. Fail Safe Feature
September 2006
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SY58606U
Typical Characteristics
VCC = 3.3V, GND = 0V, VIN = 100mV, RL = 100 across the outputs, TA = 25C, unless otherwise stated.
September 2006
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SY58606U
Functional Characteristics
VCC = 2.5V, GND = 0V, VIN = 325mV, Data Pattern: 223-1, RL = 100 across the outputs, TA = 25C, unless otherwise stated.
September 2006
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SY58606U
Functional Characteristics (continued)
VCC = 2.5V, GND = 0V, VIN = 325mV, RL = 100 across the outputs, TA = 25C, unless otherwise stated.
September 2006
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SY58606U
Input and Output Stage
Figure 2a. Simplified Differential Input Buffer
Figure 2b. Simplified CML Output Buffer
Single-Ended and Differential Swings
Figure 3a. Single-Ended Swing Figure 3b. Differential Swing
September 2006
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Micrel, Inc.
SY58606U
Input Interface Applications
Figure 4a. CML Interface (DC-Coupled)
Option: May connect VT to VCC
Figure 4b. CML Interface (AC-Coupled)
Figure 4c. LVPECL Interface (DC-Coupled)
Figure 4d. LVPECL Interface (AC-Coupled)
Figure 4e. LVDS Interface
September 2006
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Micrel, Inc.
SY58606U
CML Output Termination
Figure 5a. CML DC-Coupled Termination
Figure 5b. CML DC-Coupled Termination
Figure 5c. CML AC-Coupled Termination
Related Product and Support Documents
Part Number SY58607U SY58608U HBW Solutions Function 3.2Gbps Precision, 1:2 LVPECL Fanout Buffer with Internal Termination and Fail Safe Input 3.2Gbps Precision, 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input New Products and Termination Application Notes Data Sheet Link http://www.micrel.com/page.do?page=/productinfo/products/sy58607u.shtml http://www.micrel.com/page.do?page=/productinfo/products/sy58608u.shtml http://www.micrel.com/page.do?page=/productinfo/as/HBWsolutions.shtml
September 2006
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M9999-092606-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58606U
Package Information
16-Pin MLF(R) (3mm x3mm) (MLF-16)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated.
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